M2 EEA – Systèmes Microélectroniques Polytech’montpellier ...nouet/homepage/pdf_files/S6-2014.pdf · M2 EEA – Systèmes Microélectroniques Polytech’montpellier – MEA

Circuits Intégrés Analogiques - 2014/2015 - Chapitre 6 12/12/2014

1

M2 EEA – Systèmes Microélectroniques Polytech’montpellier – MEA 4

Analog Integrated Circuits Design Chapter VI

Miller Operational Transconductance Amplifier & Miller Operational Amplifier

Pascal Nouet / 2014-2015

[email protected]

http://www2.lirmm.fr/~nouet/homepage/lecture_ressources.html

Lecture material download

http://www2.lirmm.fr/~nouet/homepage/lecture_ressources.html


2

Introduction

AV2 1

Differential Input Stage

2nd gain stage

Optional output stage

AV1 +

-

−+

−

+

−=

−=

+=

VVv

vVV

vVV

in

inmc

inmc

2

2invout vAV ⋅=

V+ V-

Ibias1

Vdd Vdd

Ibias2

Vout

Ibias3

Vdd

Outline

•  Introduction •  Differential Input Stage •  AOP assembly •  Dynamic behavior •  AOP stability •  AOP compensation


3

Common Source Amplifier Limitations

•  Biasing –  Vin=Veff+Vtn

Current Mirror Biasing

Vdd

T1 Vout

Vin

( )( )21

1211 //

dsds

mdsdsmV gg

grrgA+

−=−=

∞=inr 21 // dsdsout rrr =

T3 T2

Vdd

21 dd II =

1

2

Vout

Vin↗

Vdd

3

Differential Input Stage: Principle

•  Sizing: symmetrical •  Biasing

–  Idsat=Ibias/2 –  Vin+=Vin-=Vmc –  Vs1=Vs2 > Vmin(Ibias) –  Vgs1=Vgs2=Veff+Vtn –  Vout=Vdd-Rload.Ibias/2

•  Small-signal –  vind=Vin+-Vin-

–  vout=Vout+-Vout- –  vmc=(vin++vin-)/2

Vdd

T1

Vout+

Vin+

Vdd

T2

Vin-

Idsat1 Idsat2

Ibias

loadR loadR

Vout-

0=−==

=−

==

−+

−+

mc

outout

mc

outvmc

loadmind

outout

ind

outvd

vVV

vvA

RgvVV

vvA


4

Differential Input Stage: Principle

T1

Vin+

T2

Vin-

Id1 Id2

Ibias

221bias

ddIII ==

mmm ggg == 21

1gsv1gsmvg

sr

+inv

2gsmvg

2gsv −inv

si

Differential mode

2ind

ininvvv =−= −+

21 gsgs vv −=

21 gsmgsm vgvg −=

0=si

1gsv1gsmvg

+inv

2gsmvg

2gsv −inv

2in

mcinvVV +=+

2in

mcinvVV −=−

21 effeff VV =

Differential Input Stage: high gain implementation

•  Active load with a current mirror –  Higher output

resistance –  Referenced output

voltage

•  Biasing –  Vout=Vdd-Vgs3

Vdd

T1

Vout

Vin+

T4 T3

Vdd

T2

Vin-

Id1 Id2

Ibias

0==

==

mc

outvmc

outmind

outvd

vvA

rgvvA


5

2in

mvg1dsr

2in

mvg−

3

1

mg 42 // dsds rr44 gsm vg

4gsv

outv

Differential Input Stage: small-signal output resistance

42 // dsdsout rrr =

0=inv

04 =gsv

044 =gsm vg

Vdd

T1

Vout

Vin+

T4 T3

Vdd

T2

Vin-

Id1 Id2

Ibias

mcin VV =+

mcin VV =−

Differential Input Stage: small-signal output voltage

2in

mvg1dsr

2in

mvg−

3

1

mg 42 // dsds rr44 gsm vg

4gsv

outv

( )4244 //2 dsdsin

mgsmout rrvgvgv ×⎟⎠

⎞⎜⎝

⎛ +=

34

12 m

inmgs gvgv ×≈

( )423

4 //22 dsdsin

min

mm

mout rrvgvg

ggv ×⎟⎟

⎠

⎞⎜⎜⎝

⎛+=

43 mm gg =

( )42 // dsdsmin

out rrgvv

×=

2in

mcinvVV +=+

2in

mcinvVV −=−


6

Differential Input Stage: small-signal gain analysis

Vdd

T1

Vout

Vin+

T4 T3

Vdd

T2

Vin-

Id1 Id2

Ibias

( )42

2,1422,1 //

dsds

mdsdsm

in

out

ggg

rrgvv

+=×=

22

2,1

biasp

biasn

mv II

gA

λλ +=

2,12,12,1

22

eff

bias

eff

bias

m VI

V

I

g =⎟⎠

⎞⎜⎝

⎛

=

( ) 2,1

2

effpnv VA

λλ +=

2,1

2,12,1

2WL

CµI

Voxn

deff =

2,12,1)(2

LW

I

CµA

dpn

oxnv

⋅+=

λλ

Low Veff and large length for large gain

Differential Input Stage: common-mode input range (CMIR)

Vdd

T1 Vmc

T4 T3

Vdd

T2 Vmc

Id1 Id2

Ibias A

B

All transistors must operate in saturation:

min,AA VV >

tpeffddB VVVV −−= 4,3

2,1effAB VVV >−4,3efftp VV +

min,AV>(for correct operation of the current source)

( ) min,2,1 AefftnmcA VVVVV >+−=

2,1min, efftnAmc VVVV ++>2,1effV>

AeffBeffAB VVVVVV +>→>− 2,12,1

( ) AtnAmcB VVVVV +−−>

tnmcB VVV −>

tnBmc VVV +<tntpeffddmc VVVVV +−−< 4,3

Low Veff for large CMIR


7

Outline


AOP assembly

T4

T2

T3

V- V+ T5 T6

Vdd=3.3V

T8 T9

T7

Ids7

T10

T13

Ids13 Vbias

Cf T16

Vout1 T11

Vout

T12

T1 Ids11

Voltage reference

Current sources

Differential pair

Active load

Common source

Common drain


8

AOP assembly: connecting first stage to the second

T4

T2

T3

V- V+ T5 T6

Vdd=3.3V

T8 T9

T7

Ids7

T10

T13

Ids13 Vbias

Vout1 T11

Vout

T12

T1 Ids11

96

611

dsds

m

ind

outv gg

gvv

A+

−==

1310

10

12

dsds

m

out

outv gg

gvv

A+

−==

713 dd II =

9,810 effeff VV =

9,810 2 dds II =

9,8102LW

LW

=

137 effeff VV =

gm10 (and so 2nd stage gain) depends on the first stage design (Veff8,9)

Total dc gain

6

7

6

7

62

2

eff

ds

eff

ds

m VI

V

I

g ==110

1310

2

eff

dsm V

Ig =27

6ds

ndsIg λ=

27

9ds

pdsIg λ=

1310 dspds Ig λ=

1313 dsnds Ig λ=

21 vvv AAA ×=

( ) 10624

effeffpnv

VVA

λλ +=

96

611

dsds

m

ind

outv gg

gvv

A+

−==1310

10

12

dsds

m

out

outv gg

gvv

A+

−==


9

AOP assembly: connecting 2nd stage to the output stage

•  Vgs11 is fixed by connecting T11 gate to the reference voltage stage or to Vout1 which variations are much smaller than those of Vg12

T4

T2

T3

V- V+ T5 T6

Vdd=3.3V

T8 T9

T7

Ids7

T10

T13

Ids13 Vbias

Vout1 T11

Vout

T12

T1 Ids11

1212. goutv vvA =

Outline



10

Dynamic behavior

•  Miller OTA is a two-stage amplifier with high output impedance –  DC gain

•  Open-Loop Dynamic Performances –  Slew-Rate (V/s) : SR –  Unity-gain frequency (MHz) : fu –  Cut-off frequency / bandwidth (kHz) : fc –  Gain-Bandwidth product (MHz) : GBW

for a first order behaviour, GBW=fu

V+ V-

Ibias1

Vdd Vdd

Ibias2

Vout

1

11

out

mv g

gA −≅

2

22

out

mv g

gA −≅

MOSFET intrinsic capacitances

p+ n+

VG>Vt VD>>Veff

Gate

Drain

p-

n+

NMOS

Source

Cgs Cgd

Csb Cdb

Lov

( )oxovoxgs CWLWLCC +!"

#$%

&≈32

( )oxovgd CWLC ≈

Gate Capacitances Junction Capacitance (reverse bias)

( ) jschSsb CAAC +≈

jdddb CAC ≈ 0

0

1ψxb

jjx V

CC

+

≈

10L

Lov ≈


11

MOSFET dynamic small-signal model

gsC

gdC

sbC

dbCgsmvggsv dsv

D G

S S

dsr

MOS Transistor "Small Signal" model for dynamic analysis

First Pole Analysis

Vdd

T7

T1

Vout

Vin+

T4 T3

T2 Vin

-

Ibias

T12

Ibias

T13

A

Vbias

1242

11

indsds

m

in

Av ggg

gvvA

++−==

gsC

gdC ?12 =ing

121212 LWCC oxpg ⋅⋅=

1212 % 10 ggd CC ⋅=

24, dd CC

1212 32

ggs CC ⋅=


12

Miller Transformation

Vout Vin

iE i'E iS

iC

i'S

-A.Vin

C

'ECE iii +−= ( )inoutC VVCpi −=

'EinoutE iCpVCpVi ++−=

( ) '1 EinE iACpVi ++=

Input Current

( ) SinoutSCS iVVCpiii +−=+='

SoutS iA

CpVi +⎟⎠

⎞⎜⎝

⎛+=11'

Output Current

Vin

iE i'E

( )AC +1

Vout

iS i'S

-A.Vin

⎟⎠

⎞⎜⎝

⎛+A

C 11

Miller Transformation

Vin

iE i'E

AC×≈

Vout

iS i'S

-A.Vin

C≈

With A > 0 et |A| >> 1:

( ) ACAC ×≈+1

CA

C ≈⎟⎠

⎞⎜⎝

⎛+11


13

Pole due to First Stage Output

Vdd

T7

T1

Vout

Vin+

T4 T3

T2 Vin

-

Ibias

T12

Ibias

T13

A

Vbias

1242

11

indsds

m

in

Av ggg

gvvA

++−==gsC

gdC pCApCg gdvgsin 212 +=

( ) !!"

#$$%

&

++

×+

−=

pgg

CgggA

dsds

indsds

mv

42

1242

11

1

1

( )pCACg gdvgsin 212 +=

12inC

AC response

-40 dB/decade

-20 dB/decade

1st pole

2nd pole


14

Outline


Voltage follower


15

Voltage follower

T=50ns

à fosc=20MHz

AC response

-40 dB/decade

-20 dB/decade

1st pole

2nd pole


16

Summary

•  Simplified Model –  One stage à One pole –  First stage pole is dominant (Miller Effect) –  A two stage Amplifier should be stable…

•  Simulation –  AC simulations : fc, fu and GBW –  Other poles (current source, …) –  Often, a two stage amplifier is not naturally stable

Outline



17

pFC

Hzf

CAggf

ggCCACCC

f

c

fv

dsdsc

dsds

totalfvtotalgdf

5500.2.227

10.6,3

500 :example

.2.21

61

2

421

42212

==⇒

=

+==⇒

+≈⇒⋅≈⇒>>

−

π

ππτ

τ

Dominant pole adjustment

V- V+ T1 T2

Vdd

T3 T4

T7

Ibias7

T12

T13

Ibias13

Vout

Vbias

Cf

Vout1

•  Idea: 1st pole shifts down to low frequencies by adding Cf in parallel with Cgd12

•  Amplifier behaves like a first order circuit à GBW

Cf = 100fF 1pF 5pF 10pF

fc=519Hz


18

gm2.vin Vout

r1

Cc

C1 gm12.vout1 r2 C2

Vout1

Close-up view of the Miller effect

V- V+ T1 T2

Vdd

T3 T4

T7

Ibias7

T12

T13

Ibias13

Vout

Vbias

Cf

Vout1

12

13122

13122

12421

421

////

//

gdfc

loaddd

loaddsds

gsdd

dsds

CCCCCCCgggr

CCCCggr

+⇒

++⇒

⇒

++⇒

⇒


( )

( )

( )

12

22

1

122

112

11111

12

1

...

),(...

mc

c

outout

outoutcoutout

outm

outinoutoutoutcoutout

inm

gpC

pCCrvv

vvpCvpCrvvg

vvfvvvpCvpCrvvg

−

++=⇒

−++=−

=⇒−++=−

gm2.vinVoutr1

Cc

C1 gm12.vout1 r2 C2

Vout1

gm2.vinVoutr1

Cc

C1 gm12.vout1 r2 C2

Vout1

( ) ( )( )cc

cmcc

CCCCCCrrbCrrgCCrCCra

122121

21121122

++=

++++=

212

21212

1

1

bpapgpCrgrg

vv m

cmm

in

out

++

!"

#$%

&−⋅⋅

=

gm2.vin Vout

r1

Cc

C1 gm12.vout1 r2 C2

Vout1


19


•  Increasing Cc –  fz and fp1 are shifted down accordingly

•  Increase of gm12 à silicon cost, power consumption

•  Design Tip : higher gm12 increases stability

( )

c

12mz

21

12m2p

c212m11p

C2gf

CC2gf

Crgr21f

⋅π

−=

+⋅π=

⋅π=

gm2.vinVoutr1

Cc

C1 gm12.vout1 r2 C2

Vout1

gm2.vinVoutr1

Cc

C1 gm12.vout1 r2 C2

Vout1

!!

"

#

$$

%

&

ω+

!!

"

#

$$

%

&

ω+=++

++

!!"

#$$%

&−⋅⋅

=

2p1p

2

212m

c212m12m

in

out

p1

p1bpap1

bpap1

gpC

1rgrg

vv


gm2.vin Vout

r1

Cc

C1 gm12.vout1 r2 C2

Vout1

•  Solution: adding a serial resistance –  1st and 2nd poles doesn’t move a lot –  Additional 3rd pole @ higher frequencies –  Zero is changed: à Zero can be adjusted

à  to compensate 2nd pole (not robust enough) à  just after the unity gain frequency (viable

solution) Rs

( )smcz RgCf

−⋅−

=1212

1π


20

Zero positioning for stability: first method

•  Step 1: –  First simulation with

random Cf0 (5pF) and Rs=0

–  Choice of a phase margin à extract fu à measure Av(fu)

•  Step 2: –  Calculation of Cf= Cf0.Av(fu) –  Zero positionning @ fu+20% à Rs calculation

V- V+ T1 T2

Vdd

T3 T4

T7

Ibias7

T12

T13

Ibias13

Vout

Vbias

Cf

Vout1

Rs

Zero positioning for stability: 2nd method

•  2nd method: –  Choice of unity-gain frequency:

•  Example: from initial fu=18MHz à

–  Calculation of the capacitance:

–  Zero positionning •  fu + 20% : 12MHz à

( ) 1212

12112

121

mczs

smcz gCf

RMHzRgC

f +⋅

=⇒=−⋅

−=

ππ

MHzfu 10=

u

mf f

gCπ22=

M2 EEA – Systèmes Microélectroniques Polytech’montpellier ...nouet/homepage/pdf_files/S6-2014.pdf · M2 EEA – Systèmes Microélectroniques Polytech’montpellier – MEA

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