55 Kurashina et al.: Low Warpage Coreless Substrate (1/8) 1. Background With a continuous enhancement of performance and feature downsizing of electronic products, the use of Ball grid array (BGA) packages is spreading rapidly as elec- tronic products because of their advantage in higher pin counts. Moreover, in keeping with the IC upsizing pace, even more fine BGAs are necessary, and as a result, the development of high reliability assembly processes for fine-pitch ICs had become essential. We believe that one of the important factors for the BGA performance is dielec- tric materials, which include ceramics[1] and organic materials.[2–4] We have been continuously developing buildup BGA substrates making use of organic materi- als[5] that are more advantageous over ceramics because of their low cost and microfabrication compatibility. Buildup substrate consists of core layers reinforced by glass cloths and buildup layers consisting of resin films. Generally, the thickness of core layers is in a range of 200– 800 μm. Therefore, via plated through holes (PTH), which penetrates through core layers, is needed for interconnec- tion. The minimum limit of PTH pitch is estimated to be 200 μm, but solder bump pitch for ASICs is expected to become around 100 μm.[6] Therefore, the development of finer interconnection technologies for organic BGA sub- strates is highly essential. Whereas vias of buildup layers can be made by a laser process, which is suitable for microfabrication and the minimum via size is estimated to be 30 μm. Therefore, high density wiring can be realized by the adoption of coreless substrate, which doesn’t include core layers.[7, 8] The comparison of properties between coreless and buildup substrate is shown in Fig. 1. In general, the adop- tion of coreless substrates for IC packages has three advantages, including high wiring design flexibility owing to fine via pitch, power source improvement because of low impedance, and large signal integrity. However, core- [Technical Paper] Low Warpage Coreless Substrate for IC Packages Mamoru Kurashina*, Daisuke Mizutani*, Masateru Koide**, Manabu Watanabe**, Kenji Fukuzono**, Nobutaka Itoh**, and Hitoshi Suzuki*** *Fujitsu Laboratories Ltd., 10-1 Morinosato-Wakamiya, Atsugi-shi, Kanagawa 243-0197, Japan **Fujitsu Advanced Technology, Ltd., 1-1, Kamikodanaka 4-chome, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8588, Japan ***Fujitsu Interconnect Technologies, Ltd., 36, Kitaowaribe, Ooaza, Nagano 381-8501, Japan (Received July 26, 2012; accepted October 15, 2012) Abstract Coreless substrate is excellent for fine patterning, small via pitches, and transmission property, and it is a promising IC packaging method for the next generation. Warpage of coreless substrate is generally large compared to the other types of IC packaging substrates because of inadequate rigidity, so the most important problem for the application of coreless substrates for high-end BGAs is warpage reduction during a reflow process. So far, only a limited number of reports have been focused on coreless substrates for large size IC packages. Moreover, very few examples have discussed substrate layer structural designs for warpage reduction and reliability improvement in IC assembly processes. In our study, we focused on the development of coreless substrates for large size ICs. To achieve our goal, we adopted the following development procedure. First, we designed analytical models with different layer structures composed of two kinds of insulating materials and estimated the effective layer structures for warpage reduction by numerical analysis. Next, we prepared the real coreless substrates with the same structure as the analytical models and evaluated their actual thermal behavior. Finally, we investigated the thermal stress reliability of IC mounted substrates. As results of these examinations, we successfully developed low warpage and high reliable coreless substrate by introducing high rigidity materials only in the external layers of the substrate. Keywords: Coreless substrate, Low warpage, IC mounted reliability, Layer structure, Prepreg
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55
Kurashina et al.: Low Warpage Coreless Substrate (1/8)
1. BackgroundWith a continuous enhancement of performance and
feature downsizing of electronic products, the use of Ball
grid array (BGA) packages is spreading rapidly as elec-
tronic products because of their advantage in higher pin
counts. Moreover, in keeping with the IC upsizing pace,
even more fine BGAs are necessary, and as a result, the
development of high reliability assembly processes for
fine-pitch ICs had become essential. We believe that one of
the important factors for the BGA performance is dielec-
tric materials, which include ceramics[1] and organic
materials.[2–4] We have been continuously developing
buildup BGA substrates making use of organic materi-
als[5] that are more advantageous over ceramics because
of their low cost and microfabrication compatibility.
Buildup substrate consists of core layers reinforced by
glass cloths and buildup layers consisting of resin films.
Generally, the thickness of core layers is in a range of 200–
800 μm. Therefore, via plated through holes (PTH), which
penetrates through core layers, is needed for interconnec-
tion. The minimum limit of PTH pitch is estimated to be
200 μm, but solder bump pitch for ASICs is expected to
become around 100 μm.[6] Therefore, the development of
finer interconnection technologies for organic BGA sub-
strates is highly essential. Whereas vias of buildup layers
can be made by a laser process, which is suitable for
microfabrication and the minimum via size is estimated to
be 30 μm. Therefore, high density wiring can be realized
by the adoption of coreless substrate, which doesn’t
include core layers.[7, 8]
The comparison of properties between coreless and
buildup substrate is shown in Fig. 1. In general, the adop-
tion of coreless substrates for IC packages has three
advantages, including high wiring design flexibility owing
to fine via pitch, power source improvement because of
low impedance, and large signal integrity. However, core-
[Technical Paper]
Low Warpage Coreless Substrate for IC PackagesMamoru Kurashina*, Daisuke Mizutani*, Masateru Koide**, Manabu Watanabe**, Kenji Fukuzono**,
Nobutaka Itoh**, and Hitoshi Suzuki***
*Fujitsu Laboratories Ltd., 10-1 Morinosato-Wakamiya, Atsugi-shi, Kanagawa 243-0197, Japan
[9] M. Kurashina, D. Mizutani, M. Koide, M. Watanabe,
K. Fukuzono, and H. Suzuki, “Low Warpage Coreless
Substrate for Large-size LSI Packages,” 2012 Elec-
tronic Components and Technology Conference, pp.
1378–1383, 2012.
[10] D. Fujimoto, K. Yamada, N. Ogawa, H. Murai, H.
Fukai, Y. Kaneko, and M. Kato, “New Fine Line Fab-
rication Technology on Glass-cloth Prepreg without
Insulation Films for Package Substrate,” 2011 Elec-
tronic Components and Technology Conference, pp.
387–391, 2011.
[11] M. Kurashina, D. Mizutani, M. Koide, and N. Itoh,
“Precision Improvement Study of Thermal Warpage
Prediction Technology for LSI Packages,” 2009 Elec-
tronic Components and Technology Conference, pp.
529–534, 2009.
[12] K. Miyake, “Thermo-Viscoelastic Analysis for Warp-
age of Ball Grid Array Packages Taking into Consid-
eration of Chemical Shrinkage of Molding Com-
pound,” Journal of Japan Institute of Electronics
Packaging, Vol. 7, No. 1, pp. 54–61, 2004.
[13] P. Hassell, “Advanced Warpage Characterization:
Location and Type of Displacement Can Be Equally
Important As Magnitude,” Pan Pacific Microelec-
tronics. Symposium Conference, February, 2001.
[14] JEDEC Standard, “High Temperature Package Warp-
age Measurement Methodology,” JESD22B112.
[15] JEITA Standard, “Measurement Methods of Package
Warpage at Elevated Temperature and Maximum
Permissive Warpage,” JEITA ED-7306, March, 2007.
62
Transactions of The Japan Institute of Electronics Packaging Vol. 5, No. 1, 2012
Mamoru Kurashina received his M. S. degree in Inorganic Chemistry from Keio University, Japan, in 1997. He joined Fujitsu Laboratories Ltd. in 1997 as a researcher of electronic materials. He is currently engaged in the quality improvement of various PWB products and especially contributes to evalu-
ate their thermal behaviors.
Daisuke Mizutani received his B.E. degree in Chemical Engineering from Nagoya Insti-tute of Technology, Japan in 1987. He joined Fujitsu Laboratories Ltd. in 1987 and since then he has been engaged in research and development of organic materials for micro-electronics.
Masateru Koide received his B.E. degree in Precision Engineering from Ibaraki Uni-versity, Japan in 1989. He joined Fujitsu Ltd. in 1989. Currently, he is taking charge of the development of advanced processor package structures for next generation UNIX server and supercomputing system as a director of
Fujitsu Advanced Technology, Ltd.
Manabu Watanabe received his B.E. degree from Nihon University, Japan in 1991. He joined Fujitsu Ltd. in 1991. He was involved in the development of PWP and HDD, and currently he is engaged in the development of LSI packaging technology at Fujitsu Advanced Technology, Ltd.
Kenji Fukuzono joined Fujitsu Ltd. in 1992. Currently, he is engaged in the development of advanced processor package structures for next generation UNIX server and super-computing system as a team leader of Fujitsu Advanced Technology, Ltd.
Nobutaka Itoh joined Fujitsu Ltd. in 1968. He was involved in the development of auto-mation design program for transmitting sta-tions and metal molds, and currently, he is engaged in the front-loading business in structural development of various electronic products at Fujitsu Advanced Technology, Ltd.
Hitoshi Suzuki joined Fujitsu Laboratories Ltd. in 1981 as a researcher. After he was involved in the development of materials for PWB, and currently, he is engaged in the development of PWB products at Fujitsu Interconnect Technologies, Ltd.