Low power architecture and HDL coding practices for on-board hardware applications Kaushal D. Buch ASIC Engineer, eInfochips Ltd., Ahmedabad, India Email:

Low power architecture and HDL coding practices for on-board hardware applications

Kaushal D. BuchASIC Engineer, eInfochips Ltd.,

Ahmedabad, IndiaEmail: [email protected]

Abstract

• Power is a critical parameter for all types of on-board hardware. As the processing frequency increases, the number of data transitions also increase. The poster describes certain architectural and HDL coding approaches that tend to reduce redundancy in hardware and can lead to significant reduction of power, especially in high-end signal processing and computation-intensive applications.

Power Dissipation in CMOS Circuits

• Power dissipation in a CMOS transistor depends on the capacitance, supply voltage and the rate at which the data toggles.

Cload is the load capacitance of the CMOS transistor

VDD is the supply voltage

f is the frequency at which the data toggles

Architectural Approaches

• Basic Bus coding techniques• Pipelining • Disabling logic blocks

Bus Invert Coding

• Bus invert coding is a technique in which, if the hamming distance between the current data and the next data is more than N/2 (where N is the bus width), then one can invert the bits and send it, so as to minimize the number of transitions on the bus. In that case a control bit goes along with the data to indicate the receiving end, whether the data is inverted or not.

• Other coding techniques involve partial bus encoding, data re-ordering etc.

Bus Invert Coding : Simulation Results

• The following are the results of a simulation carried out to understand the reduction in the number of transitions due to bus invert coding.

Bus Width Total Random Data Input

Number of Transitions

without coding (A)

Number of transition with

bus invert coding (B)

Percentage improvement in

bus invert coding against

non-coded data (B)/(A)* 100

32-bit 5000000 8005314 6879504 14.06%

64-bit 1000000 32000980 28513273 10.89%

Pipelining

• Pipelining reduces power by registering the inputs at regular intervals and thereby reduces the overall net-lengths and minimizes glitches.

• If latency can be compromised, it is better to have a pipelined architecture for reducing power consumption.

Disabling Logic Blocks• Large combinational blocks tend to dissipate more power

due to higher capacitance. Occasionally these logic blocks have continuous input signal transitions but the output may not be required at that time.

• Hence, these blocks must be enabled only when there is a need. Till then, the input should not be applied, to ensure that there are no unnecessary transitions through the logic.

• This can be taken into consideration at architectural level and such modules can be identified and taken care of in advance.

HDL Coding Techniques

• Avoiding unnecessary data transitions• Avoiding large comparators• Logic optimization techniques

Avoiding Unnecessary Data Transitions

• It has been observed in a number of designs that certain signals transit when they are not required to, but they are not detected during functional verification, as they satisfy the logical and functional requirements.

• Such signals, if handled properly and if the logic is tweaked to suppress these unwanted transitions, can also reduce power dissipation.

HDL Code - Example

Avoiding Large Comparators

• Many designs require large comparators for controlling counters. Such a comparator logic sees continuous transitions at its input leading to power dissipation.

Comparator - Example

• Suppose it is required that the counter re-initializes after a count of 2112 clock cycles.

• In such a case the comparator should be turned on only after 2048 counts (i.e. when the 11th bit goes high) and then a 6-bit comparator should count additional 64 counts to reach to the final value of 2112 counts.

• This would reduce the size of the comparator logic and hence will also significantly reduce power consumption.

Logic Optimization Techniques

• Resource sharing• State machine encoding technique• Design Constraints

Resource Sharing

• The RTL coding should be carried out in a manner that there are no unwanted or redundant logic elements.

• Every logic element contributes to power consumption as it has a capacitance attached to it and transitioning of data through that logic will lead to power dissipation.

Resource Sharing - Example

State Machine Encoding

• One-hot and Gray encoding consume lesser power as compared to binary encoding. This is because one-hot and gray encodings have only a single bit change while going from one state to another.

Design Constraints

• Design constraints help in the removal of redundant logic and hence contribute to reduction in power consumption.

• Synthesis was carried out using ‘synthesis full_case’ for a 16-bit decoder which had only 12 valid options. Using this directive, Xilinx XST was able to optimize up to 4-5 slices.

• The results do vary depending on design and tools, but the results are generally optimistic from the power consumption point of view.

Conclusion

• Transition probability and power estimation simulations carried out for a reference on-board FPGA based hardware design showed that there is an average of 3 to 4 % improvement due to architectural changes and about 5 to 7 % improvement due to HDL coding practices. (These figures may vary with change in application or the input signal transition probability).

• Bus coding for long data paths and on external interfaces can further help reduce power dissipation. Certain optimization constraints to the synthesis can also contribute to power reduction.

References

1. Gary Yeap, “Practical Low power Digital VLSI design”, Kluwer Academic Publishers, 1998.

2. Mircea R. Stan and Wayne P. Burleson, “Bus Invert Coding for Low-Power I/O”, IEEE Transactions on VLSI systems, Vol.3, No. 1, March 1995, pp 49 – 58.

3. Hichem Belhadj, Vishal Aggrawal, Ajay Pradhan, Amal Zerrouki, “Power Aware FPGA design – Part 3”, Programmable Logic Design Line, 17th February, 2009.

4. Roger Woods, John McAllister, Gaye Lightbody and Ying Yi, “FPGA implementation of signal processing systems”, Wiley, 2008.

5. Kaushal Buch, “HDL Coding methods for low-power implementation”, EDA Designline, March 2009. http://www.techonline.com/learning/techpaper/215901414