Low Cost FPGAs March 2006 Bringing the Best Bringing the Best
Low Cost FPGAs
March 2006Bringing the Best TogetherBringing the Best Together
Copyright © Lattice Semiconductor 2006S1 Low-Cost FPGAs - February/March, 2006 – Page 2
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Low Cost, LUT-based FPGA– 6K to 70K LUT4s
– 12K to 136K bits distributed memory
– 95 to 628 I/O
– High volume prices as low as $0.50 per 1K LUTs
Flexible sysIOTM Buffers– LVCMOS 33/25/18/15/12, PCI
– SSTL3/2/18 & HSTL15 & HSTL18
– Bus-LVDS, MLVDS, LVPECL & LVDS
Pre-engineered Source Synchronous I/Os– DDR2 (400Mbps)
sysDSPTM High Performance DSP Support– 12 to 88 18x18 multipliers
sysMEMTM Block Memory– 55K to 1M bits
sysCLOCKTM PLL and DLL
Enhanced Configuration Support– Configuration bitstream encryption
– Transparent updates
– Dual boot support
LatticeECP2 – Low Cost & High Performance
Low Cost
840Mbps Parallel I/O
28 GMAC DSP
Bitstream Encryption
400Mbps DDR2
Copyright © Lattice Semiconductor 2006S1 Low-Cost FPGAs - February/March, 2006 – Page 3
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LatticeECP2 – Architecture
Configuration Port
Programmable Function Units
(PFUs)
Flexible sysIO Buffers:
LVCMOS, HSTL,SSTL,
LVDS, ++
DSP BlocksMultiply and Accumulate
Support
sysMEM Block RAM 18kbit
Dual Port
sysCLOCK PLLs & DLLs
Frequency Synthesis & Clock
Alignment
Config. LogicInc Dual Boot, Encryption & Transparent
Updates
Flexible RoutingOptimized for
Speed, Cost and Routability
Pre-Engineered Source
Synchronous Support
DDR2 – 400MbpsGeneric – 840Mbps
On-Chip Oscillator
Copyright © Lattice Semiconductor 2006S1 Low-Cost FPGAs - February/March, 2006 – Page 4
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Optimized Programmable Function Unit (PFU)
PFU Resources Optimized– Best match to applications
– Best speed
– Best cost
Tools Tuned To Optimally Use Available Resources
SLICE 0LUT4
LUT4
FF
FF
SLICE 1LUT4
LUT4
FF
FF
SLICE 2LUT4
LUT4
FF
FFFromRouting
ToRouting
SLICE 3LUT4
LUT4
Carry Chain
Carry Chain
Logic Block (PFU)
LUT4 ROM Carry FF RAM1
Slice 0
Slice 1
Slice 2
Slice 3
1. Available in 25% of the PFUs
Copyright © Lattice Semiconductor 2006S1 Low-Cost FPGAs - February/March, 2006 – Page 5
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Extensive High Performance Clocking
High Performance Clock Distribution– Eight global clock networks– Eight regional secondary clocks– Two low-skew edge clocks per side
sysCLOCK PLL and DLL Technology– 2 to 6 PLLs per device
» External capacitor allows operation as low as 1MHz» Dynamic phase shift capability
– 2 DLLs per device» Includes slave delay for source synchronous implementations
On-Chip Oscillator (Typ 130MHz)
Edge Clock Divider– X2, X4, X8– For high speed source synchronous implementations
Copyright © Lattice Semiconductor 2006S1 Low-Cost FPGAs - February/March, 2006 – Page 6
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sysCLOCK PLL
Two General Purpose PLLs (GPLLs) Per Device Up To Four Standard PLLs (SPLLs) Per Device Frequency Range 1 to 420MHz Programmable Phase / Duty Cycle (22.5 degree steps) Programmable Dividers Internal and External Feedback PLLs Filter Jitter
Feedback Divider
(CLKFB)
PLLPost Scalar
Divider (CLKOP)
Input Clock Divider (CLKI) Phase &
Duty Select
Secondary Clock
Divider (CLKOK)
Adjust*
Delay
CLOCK IN(From pin or
routing) CLOCK OUT
CLOCK OUT
LOCK
CLOCK OUT
Dynamic Adjust
Feedback(From post scalar divider, clock net or external pin)
Dynamic Adjust
Optional External Capacitor
* GPLL Only
+/- 8 Steps 130ps Nominal
Copyright © Lattice Semiconductor 2006S1 Low-Cost FPGAs - February/March, 2006 – Page 7
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sysCLOCK DLL
Flexible DLL Provides 3 Modes:
– Calibrated delay– Clock injection
removal– Clock match
100 to 500MHz Operation
DLLs Maintain Clock and Data Alignments
Ph
ase C
om
parato
r
Clock In(From pin or routing)
ClockOut
Lock
Feedback(DLL Internal, clock net or external pin) ALU
DelayLine
50%Duty Cycle
50%Duty Cycle
2/4
Clock In(From pin or routing)
Ou
tpu
t Mu
x
ClockOut
sysCLOCK DLL
Matched DelayDelayLine
ClockOut
Note: Simplified diagram
Copyright © Lattice Semiconductor 2006S1 Low-Cost FPGAs - February/March, 2006 – Page 8
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On-Chip Oscillator
On-Chip Oscillator Provides Low Cost Clock
– Ideal for non-timing-critical state machines
Drives Internal Routing– Can be routed off chip
Nominal Frequency Can Be Set 2.5 to 130Mhz
Easily Implemented With ispLEVER Design Tools
COMPONENT OSCD
-- synthesis translate_off
GENERIC (NOM_FREQ: string := 2.5);
-- synthesis translate_on
PORT (OSC:OUT std_logic);
END COMPONENT;
attribute NOM_FREQ : string;
attribute NOM_FREQ of OSCins0: signal is “2.5”;
OSCD
OSC
Oscillator Primitive
Example VHDL Usage
Copyright © Lattice Semiconductor 2006S1 Low-Cost FPGAs - February/March, 2006 – Page 9
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High-Performance sysDSP Block
Programmable Multiplier – One 36x36 or four 18x18 or eight
9x9
Programmable Addition, Subtraction & Accumulate
Programmable Pipelining– Input / Intermediate / Output
325MHz Performance – Provides up to 28.6 GMAC/second per
device
Suitable For Wide Range of DSP Functions Including
– FIR Filters, FFTs and complex arithmetic
X
X+-+-
X
X+-+-
+ +
sysDSP BlocksysDSP Block
Copyright © Lattice Semiconductor 2006S1 Low-Cost FPGAs - February/March, 2006 – Page 10
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DQS/Strobe Delay and Transition Detect*
PIO ATri-state
Register Block(2 Flip/flops)
Input
PIC
Pre-Engineered Source Synchronous I/O
Implement High Speed Memory Interfaces
– DDR1/2
Implement High Speed Source Synchronous Interfaces
– SPI4.2
– ADC/DAC
Pre-Engineered I/O Logic Support
– DDR to SDR conversion
– Gearbox logic
– DQS/Strobe alignment
DDR to SDR Conversion
OutputRegister Block(2 Flip/flops)
InputRegister Block(5 Flip/flops)
PIO B (Detail Not Shown)
* Selectedblocks
2:1 Gearbox(Optional)
Shared With PIO B
Precision Strobe/DQS Alignment
2:1 Gearbox For Operation Up to
840Mbps
Copyright © Lattice Semiconductor 2006S1 Low-Cost FPGAs - February/March, 2006 – Page 11
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sysIO Support
* Includes PCI clamping diode. Bottom I/Os only** HSTL II outputs only supported for 1.8-volts*** Drivers on 50% of pairs left and right side of the device only**** LVPECL and BLVDS can be supported through emulation
Standard Clock Speed
Clock Speed
LVTTL, LVCMOS
3.3/2.5/1.8/1.5/1.2 V
166MHz 333Mbps
PCI* 66MHz 66MHz
SSTL 18/2/3 (I, II) 200MHz 400Mbps
HSTL 18/15 (I, II**) 200MHz 400Mbps
LVDS*** 420MHz 840Mbps
Differential HSTL 200MHz 400Mbps
Differential SSTL 200MHz 400Mbps
sysIO Buffer Support Chip Level Support
Standard Speed
DDR1/2 Memory 400Mbps
PCI 66MHz
Generic Source Synch. 840Mbps
Copyright © Lattice Semiconductor 2006S1 Low-Cost FPGAs - February/March, 2006 – Page 12
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LVCMOS/LVTTL I/O Features
Hotsocketing Capable– Input leakage less than 1mA during power-up/power-down– Power supplies can be sequenced in any order
Programmable Slew Rate
Programmable Drive Strength– 4 to 20mA (3.3-volts)– 4 to 20mA (2.5-volts)– 4 to 16mA (1.8-volts)– 4 to 8mA (1.5-volts)– 2 to 6mA (1.2-volts)
Programmable Pull-up, Pull-down, Bus-friendly
Programmable Open Drain
Copyright © Lattice Semiconductor 2006S1 Low-Cost FPGAs - February/March, 2006 – Page 13
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I/O Banking Scheme
Eight General Purpose I/O Banks Per Device
– Configuration pins in separate bank
Output Standard Support Dependent on VCCIO
Referenced Inputs Dependent on VREF
LVCMOS Inputs– 12, 25 & 33 independent of
VCCIO
– 15 & 18 dependent on VCCIO
Multiple Compatible I/O Standards In A Bank
VREF1(2)
GND
Ban
k 2
VCCIO2
VREF2(2)
VREF1(3)
GND
Ban
k 3
VCCIO3
VREF2(3)
VREF1(7)
GND
Ban
k 7
VCCIO7
VREF2(7)
VREF1(6)
GND
Ban
k 6
VCCIO6
VREF2(6)
V RE
F1(
5)
GN
D
Bank 5
V CC
IO5
VR
EF
2(5)
V RE
F1(
4)
GN
D
Bank 4
V CC
IO4
V RE
F2(
4)
VR
EF
1(0)
GN
D
Bank 0
VC
CIO
0
VR
EF
2(0)
VR
EF
1(1)
GN
D
Bank 1
VC
CIO
1
VR
EF
2(1)
GND
VCCIO8
Ban
k 8
Copyright © Lattice Semiconductor 2006S1 Low-Cost FPGAs - February/March, 2006 – Page 14
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Soft Error Detect (SED) Logic
LatticeECP2 Devices Contain Hard SED Logic
– Not available in Spartan/Cyclone
Checks Configuration Bits In Background
– Compares to CRC
– Ignores EBR and distributed memory
In Case of Error Optionally:– Generates an error flag
– Background reconfigures logic
– Initiates a full reconfiguration
Target This Feature for High Reliability Applications
– SED is a “non-issue” for most applications
ConfigurationLogic
ConfigurationBits
Hard SED Logic
LatticeECP2
Copyright © Lattice Semiconductor 2006S1 Low-Cost FPGAs - February/March, 2006 – Page 15
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Encryption
Design Security Increasingly Important– Overbuilding, reverse engineering and cloning all too common
Encrypt Bitstreams With 128-bit AES Using ispVM
On-Chip OTP 128-bit Decryption Key Storage– Choose your own unique key
On-Chip 128-bit AES Decryption Engine
Configuration Memory
128-bit AES Encrypted Bitstream
LatticeECP2
DecryptionEngine
128-bit Key
128-bit Key In OTP Non-Volatile
Memory
Decrypted Data Configures FPGA
Copyright © Lattice Semiconductor 2006S1 Low-Cost FPGAs - February/March, 2006 – Page 16
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Dual Boot Mode
Store Active and Backup (Golden) Configurations In SPI Configuration Memory
LatticeECP2 Will Automatically Use Golden Configuration If Active Configuration is Invalid
Increase System Reliability When Configurations are Field Updated
Sector 0
Sector 1
Read Data
Control
LatticeECP2
LatticeECP2 Loads Active Configuration (B) at Power Up. If This Fails Configuration A is Used
SPI Configuration Memory
Golden (A)Configuration
Active (B)Configuration
Copyright © Lattice Semiconductor 2006S1 Low-Cost FPGAs - February/March, 2006 – Page 17
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TransFR I/O For Live Field Updates
Field Update FPGAs and Maintain High System Uptime
Config. 1
LatticeECP2
(Config. 2)
Config. Memory
Step 1Load New Config. To Configuration Memory
Step 2Lock The I/Os In
The Desired State
Config. 1
LatticeECP2
(Config. 2)
Config. Memory
Step 3Apply New
Configuration
Config.2
LatticeECP2
(Config. 2)
Config. Memory
Step 4FPGA Regains Control of I/O
Config.2
LatticeECP2
(Config. 2)
Config. Memory
Copyright © Lattice Semiconductor 2006S1 Low-Cost FPGAs - February/March, 2006 – Page 18
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Support Designs Over 300MHz
Element Performance (MHz)
PFU 375MHz*
sysCLOCK PLL Input Range 1 – 420MHz
Global Clock 500MHz
sysMEM EBR 350MHz
sysDSP Block 325MHz
sysIO Buffer400Mbps (DDR1/2 memory)
840Mbps (Generic Source Synch.)* Simple functions (For example 16-bit decoder, 16-bit counter)
Copyright © Lattice Semiconductor 2006S1 Low-Cost FPGAs - February/March, 2006 – Page 19
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Device ECP2 6 ECP2 12 ECP2 20 ECP2 35 ECP2 50 ECP2 70
LUTs (K) 6.0 12 21 32 48 68
sysMEM Blocks 3 12 15 18 21 56
sysMEM (Kbits) 55 221 276 331 387 1,032
Distributed RAM (Kbits) 12 24 42 65 96 136
# 18x18 Multipliers 12 24 28 32 72 88
PLLs/DLLs 2/2 2/2 2/2 2/2 4/2 6/2
Package & IO Combinations
144-pin TQFP (20x20mm) 95 95
208-pin PQFP (28x28mm) 127 127
256-ball fpBGA (17x17mm) 192 192 192
484-ball fpBGA (23x23mm) 297 332 332 339
672-ball fpBGA (27x27mm) 363 452 500 500
900-ball fpBGA (31x31mm) 628
Samples Q4 Q2 Q3 Q3 Q1 Q4
LatticeECP2 Family
Copyright © Lattice Semiconductor 2006S1 Low-Cost FPGAs - February/March, 2006 – Page 20
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Device ECP2M 20 ECP2M 35 ECP2M 50 ECP2M 70 ECP2M 100
LUTs (K) 19 34 48 67 95
sysMEM Blocks 54 98 201 222 264
sysMEM (Kbits) 995 1,806 3,705 4,092 4,866
Distributed RAM (Kbits) 41 71 101 145 202
# 18x18 Multipliers 24 32 88 96 168
PLLs/DLLs 8/2 8/2 8/2 8/2 8/2
Package & IO Combinations
256-ball fpBGA (17x17mm) 163
484-ball fpBGA (23x23mm) 301 301 287
672-ball fpBGA (27x27mm) 402 387
900-ball fpBGA (31x31mm) 455 449 457
1156-ball fpBGA (31x31mm) 601
Samples TBD Q2 TBD TBD TBD
LatticeECP2M Family
Copyright © Lattice Semiconductor 2006S1 Low-Cost FPGAs - February/March, 2006 – Page 21
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ECP2 Timeline
Family Publicly Announced, Collateral Available Now
Limited ECP2-50 Prototypes Available Now– Broad sample availability during Q2
– Whole family planned for production by the end of 2006
Pricing As Low As $0.50 Per KLUT– Lowest speed grade, highest volume
ECP2-50 Supported in ispLEVER 5.1 SP2
Extensive IP Support Planned For 2006
Copyright © Lattice Semiconductor 2006S1 Low-Cost FPGAs - February/March, 2006 – Page 22
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Advanced Configuration Support
Flexible Configuration Options– Low cost SPI boot memory,
microprocessor, JTAG
Encrypted Bit Stream– On-chip 128-bit AES decryption
– Encryption key securely stored on-chip
Automatic SPI Dual Boot– Allows recovery if power or communication
fails during field update
Simple Field Configuration– Define I/O state during field configuration
– Reconfigure FPGA while system operates
Copyright © Lattice Semiconductor 2006S1 Low-Cost FPGAs - February/March, 2006 – Page 23
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ECP2 Compared to ECP
Feature ECP ECP2 Impact
Logic 8 LUTs/PFU8 Registers/PFU25% Dist. Memory
8 LUTs/PFU6 Registers/PFU12.5% Dist. Memory
Lower Cost
Clocks 4 Primary4 Secondary
8 Primary8 Regional2 Edge/side
Higher SpeedClocking
PLLs 2 – 425MHz – 420MHz
2 – 61MHz – 420MHz
Flexibility
DLLs 0 2 Flexibility
Memory 9Kb EBRs 18Kb EBRs Lower Cost
I/O sysIO BufferDDR MuxDQS Alignment
sysIO Buffer (inc DDR2) DDR Mux + GearboxDQS AlignmentGeneric DDR
Higher Speed I/O
Config. SPI PROM SPI PROMDual bootEncryption
Improved Configuration
Copyright © Lattice Semiconductor 2006S1 Low-Cost FPGAs - February/March, 2006 – Page 24
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LatticeECP2 Competitive Comparison
Feature Spartan3E Cyclone II LatticeECP2
DSP Basic 18x18 Multiplier
Basic 18x18 Multiplier
Full-Featured sysDSP Block
DDR / Source Synch
333Mbps DDR2
DDR Registers
333Mbps DDR2
DQS Alignment
400Mbps DDR2
DQS Alignment
DDR Registers
Clock Transfer
Gearbox Logic
Config. SPI PROM Proprietary PROM SPI PROM
Encryption
Dual-boot
TransFR
Distributed Memory
50% - Inefficient None Optimized 12.5%
Logic LUT4 + Register LUT 4 + Register Optimized
75% LUT4+FF
25% LUT
Exceptional Performance
Uncommon Value