Logic Synthesis 1 PavanKV

Logic Synthesis

Pavan Kumar KV

Definition Synthesis is a translation of a behavioral (RTL) representation of a design into a

structural one. Automatic process with user control

Translation

• Converts HDL to functional booleanequivalent HDL syntax/rule checks Optimizes HDL Arithmetic function mapping Sequential function mapping Combinational function mapping

RTL level Optimization• Code related processing is first performed when a model is synthesized. Some of the steps

are:

• Expansion - subprograms are in-lie expanded.

• Constant folding - eg. A + 3 + 2 becomes A + 5

• Loop unrolling - loop statements are unrolled to a series of individual statements.

• Dead code removal - any unused code is discarded.

• Bit minimization - for example, VHDL state encoding, operator bit width, etc.• Different implementations of arithmetic operators have different area and timing

characteristics. E.g. ‘+’ operator can be carry look-forward (fastest), carry look-ahead or ripple carry(smallest).

• Common sub-expression sharing• Operator reordering• Resource sharing, etc.

Logic level optimization• All registered elements are fixed, only combinational logic is optimized.

• Optimization at this level involves restructuring of equations according to the rules of Boolean law.

• The types of logic optimization include:

– minimization

– equation flattening

– equation factorization

• The conversion of multiple boolean equations into a two level sum-of-products form (AND/OR) is called flattening. All the intermediate terms are removed.

• Thus, flattening removes all logic structure from a design.• The result of flattening is a two-level, sum-of-products form. • Before flattening out = t1.t2 t1 = a + b(c + f) t2 = d + e'

• After flattening out = ad + bcd + bdf + ae‘+ bce' + be'f

• Not all designs can be flattened successfully by the tools.

• Small designs of 10 inputs or less can always be flattened.

• Large designs having 20 or more inputs are often impossible to flatten.

• Designs with many XOR and multiplexer gates, such as adders and ALUs, are generally difficult to flatten.

• For example• An N-bit XOR function produces 2 n-1 terms. • A 20-input XOR gate, when flattened, has 219 (524,288) terms.

Flattening

Factorization/Structuring• The factorization of Boolean equations is a process of adding intermediate terms.

• This adds implied logic structure which both reduces the size of implied circuit and reduces large fan-outs.

• Adding structure adds levels of logic which tend to make a circuit smaller but it may be slower.

Logic Level OptimizationL = A.B.C

Y1=L+A.B.D

Y2=A.B+C+D

Y1=A.B.C+A.B.D

Y2=A.B+C+D

flattenequations

M=A.B

N=C+D

Y1=M.N

Y2=M+Nfactorize

M=A.B

L=M.C

Y1=L+M.D

Y2=M+C+D

factorize

• In the above eg. Facorization after flattening gave better results.

• The results may vary from case to case.• The tools will choose the optimal optimization

tecniques to meet the constraints.

Mapping/Optimization• Maps boolean functions to technologyspecific primitive functions• Modifies mapping to meet design goals Design Rules Timing Area Power

Optimization: Constraint-Driven

Synthesis/Physical Synthesis

Synopsys Design Compiler and the Design Flow

Basic Synthesis Flow

Outline: Set Up

DC Setup Files• Setup files automatically read at DC startup .synopsys_dc.setup• Possible locations (read in this order)1. Root setup:$SYNOPSYS/admin/setup/.synopsys_dc.setup2. Home setup:$HOME/.synopsys_dc.setup (optional)3. Local setup:./.synopsys_dc.setup (optional)• Use to customize the work environment

DC Setup Files - example# TCL-subset .synopsys_dc.setup file must# have the # character on the first line of the fileset search_path ". /synopsys/libraries/syn $search_path"set target_library "lsi_10k.db"set synthetic_library "standard.sldb dw_foundation.sldb"set link_library "* $target_library $synthetic_library"set symbol_library "lsi_10k.sdb"define_design_lib MY_WORK -path ./WORK# example: removing high drive inverterset_dont_use lsi_10k/IVP

Library Setup• search_pathAllows files to be read in without specifying directory path in the commandDirectories in which DC will look for library/design .db files during a link• target_libraryTechnology cell library files (i.e. lsi_10k.db)Compile chooses inferred cells from target library

• synthetic_library Library of DesignWare components dw_foundation.sldb• Advanced set of IP components optional to DC• Wide variety moderate/high performance arithmetic architectures• Fifos, stacks, counters, digital PLL, arbiters, priority encoders,SRAM models, ECC, CRC, debugger, decoders/encoders, more...• Macrocells: 8051 microcontroller, 16550 UART, Memory BISTcontroller, AMBA peripherals(I2C, UART, SSI, APB, AHB, …)

• link_libraryUsed during design linking (pre- and post-compile) All cells in a design must be in one of the link libraries• Inferred (chosen during compile based on RTL functionality)• Instantiated (specific cell instance placed in design RTL)• link_library must always start with "*", indicating loaded designs should be searched first when linking• All synthetic and target libraries must be included in link_library

•define_design_lib Directory where DC places intermediate design files (default isdirectory in which DC is run)•set_dont_use <lib>/<cell> Specifies cells of a target library or implementations of a syntheticlibrary to not use during compile

Before RTL Design Compiler could synthesize a design, it is necessary to tell the tool which libraries it should use to pick up the cells.

Setting up libraries for synthesis

There are three types of librariesTechnology libraries, Symbol libraries, and DesignWare libraries.

The technology libraries, which contain information about the characteristicsand functions of each cell, are provided and maintained by the semiconductorvendors and must be in .db format.

The symbol libraries contain graphical symbols for each library cells. Aswith technology libraries, it is also provided and maintained by semiconductorvendors. Design compiler uses it to display symbols for each cell in the designschematic.

The DesignWare libraries are composed of pre-implemented circuits for arithmetic operations in your design, and such designware parts are inferred through arithmetic operators in the HDL code, such as "+- <><=>=". The librariescome with two types: the standard DesignWare library and the Foundation DesignWare library.

Outline : Reading the Design

• Translates HDL to intermediate format• Recommended for reading RTLdc_shell-t> analyze -helpUsage: analyze # analyze[-library library_name](Use this library as the work library)[-work library_name] (Use this library as the work library)-format format string (The format of the hdl files)[-update] (Update analysis from original source)[-schedule] (Analyze the design for scheduling)[-create_update] (Create .update file for use by"analyze -update")[-define macro_names] (list of top-level macros, Verilog only)file_list (Files to read in)

Analyze

• Second step of HDL translation• Builds generic technology(GTECH) database HDL parameters are expanded Registers and latches are inferred Links design• Supports parameter passing/architecture selection• Recommended for reading RTLdc_shell-t> elaborate -helpUsage: elaborate # elaborate[-library library_name](Use this library as the work library)[-work library_name] (Use this library as the work library)[-architecture arch_name](Architecture to build)[-parameters param_list](Parameters for the design)[-file_parameters file_list](Files containing parameters forthe design)[-update] (Automatically update out-dated files)[-schedule] (Build the design for scheduling)[-gate_clock] (Gate clocks)design name (Name of the design to build)

Elaborate

• read_file performs analysis and elaboration(except link) in one step• Parameter passing/architecture selection not supported• Recommended for reading mapped netlistsdc_shell-t> read_file –helpUsage: read_file # read file from disk[-format format_name] (verilog, vhdl, ddc, db)[-single_file file_name](group all designs into this file)[-define macro_names] (list of top-level macros, Verilog and SystemVerilog only)[-library library_name](Use this library as the work library, VHDL only)[-work library_name] (Use this library as the work library, VHDL only)[-names_file file_list](list of files for name changes)[-ilm] (Read from the Milkyway ILM view)[-rtl] (register transfer-level verilog/vhdl format)file_list (list of files to read)

read_file

Outline: Defining Design Environment & Set Design Constraint

Define the Design EnvironmentDefining the operating Conditions• set_operating_conditions

Sets PVT for timing calculations• Process/Voltage/Temperature(PVT) conditions affect timing• Technology libraries are characterized at different PVT corners• Corner specified in technology library (i.e. worst, typical, best)

• Defining Wireload Models (WLM) set_wireload_model, set_wireload_mode Fanout-based statistical model for estimating wire capacitance Needed for non-DCT runs Not as accurate as DCT method Default wireloads provided in technology library generally inaccurate Custom wireload generated from accurate floorplan of the design gives best results

• DC Topographical (DCT) calculates net parasitics based on physical layout Correlates well to place and route timing

Modeling the System Interface • Defining drive characteristics for input ports → set_driving_cell (or) set_drive (or) set_input_transition • Defining loads on input and output ports → set_load • Defining fanout loads on output ports

Specifying Power IntentUPF Commands in Synopsys Tools

Defining Design Constraints

• Two types of constraints Design Rule Constraints

(DRC) Optimization Constraints

Optimization Priority• Design goals often conflict• Optimization engines must resolve conflict• Priority rules• DC priority

DRC Timing Power Area

• Can be modified with set_cost_priority

Constraint Guidelines• Golden rule #1: set realistic constraints

Most critical for timing and DRC constraints• Golden rule #2: validate constraints

check_design check_timing report_timing_requirements

• Corollary: Garbage in, garbage out• Correlation issues

Derate• Adjusting constraints to account for

unmodeled effects Over-constraining

• Modifying constraints to drive optimization to desired goal

Major Design Compiler Constraints

set_max_transition• Largest transition time allowed

set_max_fanout• Largest fanout allowed

set_max[min]_capacitance• Largest/smallest capacitance allowed

Defaults usually set in technology library Highest optimization priority

Design Rule Constraints(DRC)

•create_clock Name, source port, period, duty cycle Constrains timing on all register to register paths•set_clock_uncertainty Estimated network skew•set_clock_latency Estimated source and network delays•set_clock_transition Estimated input slew•set_ideal_network Disables timing calculation and optimization of clock network On by default• Internally generated clocks create_generated_clock• Calculates latency from source port to internal pin• Post-CTS set_propagated_clock• Calculates actual clock tree delays set_dont_touch_network• Prevents clock tree optimization

Optimization Constraints : Clocks

• Virtual clock Create with create_clock with no clock source port Useful for modeling external clocks Used for input/output delay specification• Gated clocks set_clock_gating_checks• Delay constraint to prevent clock glitching

Example

Optimization ConstraintsDerating•set_timing_derate Mechanism to add margin Used to account for unmodeled delay affects Used to adjust for correlation problems

Power•set_max_dynamic_power•set_max_leakage_power•set_max_total_power• Power constraints are lower priority than timing constraints Optimization engines will not reduce power if it creates negative slack

Area•set_max_area Constrains design area Area constraints are lower priority than timing constraints• Optimization engines will not reduce area if it creates negative slack

• set_fix_multiple_port_nets Buffer all net segments connected to an output port• set_dont_touch Prevents optimization Works only for mapped gates• set_dont_touch_network Same as set_dont_touch Applies to all combinational logic in fanout• set_size_only Prevents all optimizations except sizing

Optimization Constraints: Structural

•set_false_path Disables timing calculation for a path More cpu intensive than set_disable_timing

•set_multicycle_path Extend path setup/hold requirement beyond a single clock cycle

•set_case_analysis Applies logic value to ports/pins for timing analysis only Disables timing arcs through affected logic gates Does not affect functionality Logic value is propagated through combinatorial logic

•set_disable_timing Disables timing calculation through specified cells, pins, or ports Use instead of set_false_path when possible

•set_ideal_network Disables timing, optimization, and DRC checking Can be propagated through logic Useful on high-fanout nets which will be fixed in place and route On by default for clocks

•set_max_delay/set_min_delay Overrides default default setup/hold requirement with point to point requirement

Optimization Constraints: Exceptions

Outline : Compile Strategies

Top-Down Compile

Benefits:Benefits:• Optimization engines work on full design, complete paths• Usually get best optimization result• No iteration required• Simpler constraints• Simpler data managementDrawbacks:Drawbacks:• Longer runtime More processing required More memory required

dc_shell-t> current_design TOPdc_shell-t> compile_ultra –timing_high_effort_script

Bottom-Up Compile• • Benefits:Benefits: Divide-and-conquer methodology localizes problem areas Budgeting method enables parallelized synthesis effort Less processing required per run Less memory required per run• • Drawbacks:Drawbacks: Optimization works on sub-designs, hierarchical path segments Optimization result not as good as top-down compile Iterations may be required More hierarchies and data to maintain More work for user More error-prone

Meeting Timing Goals• Enable DC-Ultra optimizations and embedded script compile_ultra –timing_high_effort_script• If runtime excessive compile_ultra

compile –map_effort_high –incr• Use critical range and path groups• Ungroup hierarchy• Register retiming• Use fast DesignWare

compile_ultra

• Advanced datapath synthesis Optimized arithmetic trees Carry save logic• Embedded scripts targeting area/timing• Automatic ungrouping• Automatic boundary optimization• Topographical technology for best timingcorrelation• Library aware structuring and mapping

Setting Critical Range / Group Path

• Critical range > 0 reduces TNS and improves overall timing set_critical_range 2 TOP• Path groups focus optimization effort• Create additional path groups and set a critical range group_path -from [all_inputs] -name input_paths \

-critical_range 0 group_path -to [all_outputs] -name output_paths \

-critical_range 0 group_path -from clk -to clk -name internal_paths \

-critical_range 2• Group critical paths group_path –to top/mem*/data –name memory_inputs \

-critical_range 2

Best Practice:• Use a reasonable amount for critical range (i.e. 10% of the clock period). The larger the critical range, the longer the compile time.

Ungroup Hierarchy

• Optimization works on paths within hierarchical boundaries• Removing hierarchical boundaries allows optimization algorithms towork on larger or entire paths• Produces better optimization results• For best timing results, remove hierarchy on critical paths• For best area results, remove as much hierarchy as possible• compile_ultra automatically ungroups as needed• ungroup allows manual ungrouping

Register Retiming• Moves registers through combinational gates to improve timing/area• optimize_registers/set_optimize_registers Use for pipelined designs and aggressive retiming• pipeline_design Use to pipeline designs• compile_ultra –retime Use for non-pipelined designs and less aggressive retiming

Clock Gating

• Clock gating not only can save power, it can also help in area savings insert_clock_gating Run before compile_ultra

saves one mux per register, by using only one clock gate per register bank

Outline : Design Analysis

report_design

• Operating conditions• Wire load model and mode• Internal input and outputpin delays• Disabled timing arcs

report_clock

• Clock definition• Clock latency• Clock skew

• Use check_design to check consistency• Consistency means … no unintentionally unconnected ports no unintentionally tied ports no cells without input or output pins no mismatch between a cell and its reference no multiple-driver nets no recursive hierarchy

check_design

check_timing• Unconstrained timing paths

• Clock-gating logic

• Unmapped cells

report_qor

• Timing summary for all path groups• Good overall status of design timing

report_constraint

• Shows difference betweenuser constraints and actualdesign values

report_delay_calculation

• Shows how report_timing calculates delay of a timing arc (cell or net)• Use to understand contributors to Delay calcs

RTL CompilerSynthesis Flow

Optimized netlist

.lib

.lbr

RTLNetlist

.g.SDC

Physical Design

.SDC .g

Encounter RTL

Compiler

Logic Verification

Inputs and Outputs of the Synthesis Tool Inputs

RTL: Verilog, VHDL, directives, pragmas.

Constraints: .sdc or .g Library: .lib or .lbr Physical: LEF (optional)

Outputs Optimized netlist LEC .do file ATPG, ScanDEF, and others Constraints: .sdc or .g

Synthesis Features

Encounter RTL Compiler synthesis provides the following features: Large capacity for top-down synthesis Fast linear runtimes Global optimization finds the best overall structure Well balanced structure for congestion and timing

closure Support for super-threading Support for multisupply voltage (MSV) design

synthesis

Design for Test Features

Design for Testability (DFT) supports the following features:

Multiple clock domains

Multiple scan chains

DFT rule checking

Scan chain configuration and connection

Shadow logic around untestable logic

Scan chain abstraction models

Output ScanDEF and ATPG interface files

Low-Power Synthesis Features Low-power synthesis in the Encounter RTL Compiler

supports the following features: Dynamic power optimization Leakage power Optimization Switching activity information from TCF

and SAIF Hierarchical clock gating Multi-VT leakage

power optimization State- or path-dependent

internal power Cnet

SR TR

Cpin

Instance power Net power

Block FFBlock MUX

clken

Datapath Synthesis Features Datapath synthesis in the Encounter RTL Compiler supports the

following features:

Apply datapath optimization in your flow.

Use the datapath operations.

Verify operator merging and its typical scenarios.

Apply carrysave transformations.

Report the datapath components.

Use ChipWare Developer.

Synthesis Flow

Basic Design FlowSet target library

set_attr library name /

Read HDL filesread_hdl ${FILE_LIST}

Elaborate the designelaborate

Set timing and design constraints

Apply optimization directives

synthesize -to_mapped and synthesize -incremental

Interface to place and route

Place and Route

Yes

Modify optimization directives

Meet constraints? No

synthesize -to_generic

Netlist, SDC

Analyze and Report

Release - 2003.1 55

The Configuration File The .synth_init file contains commands that are executed upon starting

the compiler. These commands do the following: Set the library and HDL search paths. Suppress unwanted warning or information messagesSet globally applicable attributes

The compiler searches for this file in the installation directory, and in the current directory. In the home directory it searches for .cadence/.synth_init. The compiler loads the file unless you start it with the -n option.

include load_etc.tclsource ~/my_file.tclset_attr information_level 9 /set_attr endpoint_slack_opto 1 /suppress_messages { LBR-21 LBR-72 LBR-146 }

Sample .synth_init file

This file includes useful Tcl procedures that perform any extra functions (e.g. remove_buffer_tree)

Navigating the Virtual Directory Structure The compiler uses UNIX-like commands to navigate the design hierarchy in

memory. cd — Sets the current directory in design hierarchy. ls <-l > < -a> — Lists the objects in the current directory. mv — Moves (renames) a design in design hierarchy.

mv test2 test3 Renames a design test2 as test3.

popd — Removes the topmost element of the directory stack, revealing a new top element and changing the directory to the new top element.

pushd — Pushes the specified new target directory onto the directory stack and changes the current directory to that specified directory.

rm — Removes an object (like a clock definition) in design hierarchy. rm /des*/test3/timing/clock_domains/domain_1/clock Removes clock object.

find — Finds an object and passes it to other commands. ls –l –a [find / –wireload *] Reports the wire loads.

Setting Attributes In the compiler, there are predefined attributes associated with

objects in the database. Use the set_attribute or set_attr command to assign values to these attributes.

Syntaxset_attribute <attribute name> <value> <object>

To get information on all the attributes containing the word clock, enter: set_attr –h *clock* *

Examples Root attribute (Notice the fourth argument):set_attribute lp_insert_clock_gating true / Design attribute:set_attr lp_clock_gating_exclude true /des*/top_mod

Querying Attributes To retrieve the value of an attribute, use: Syntax

get_attribute {attribute_name [object]} | {-h object_type [attribute_name]} • Works on a single object.

Or ls –l –a (a = attribute, l = long list)

Examplesget_attr propagated_clocks $pinget_attr load /libraries/slow/INVX1/Als –la /ls –l –a /designs/dtmf_chip

Finding Design Objects

Purpose CommandFinding all flops and latches

find /des* -instance inst*seq*/*

Finding all the input ports find /des* -port ports_in/*

Finding all the output ports find /des* -port ports_out/*

Finding all pins in a hierarchical instance v1

find /des* -pin inst*hier/v1/*find /des* -pin v1/*

Finding all subdesigns. find / -subd *

Finding all hierarchical instances in the design

set inst_list [find / -instance *]echo $inst_list

Finding all clocks in the design

find / -clock *

Finding all available wire-load models in a library

[find [find / -library <LibraryName>] –wireload *]

Setting the Technology Library The library attribute specifies the target technology for synthesis.

To load a single library, enter set_attr library lsi500k.lib /The library attribute is a root attribute.

To load multiple libraries, enterset lib_list1 “ 01_wc3.lib mylib1.lib x1.lib “set_attr library $lib_listSetting the library attribute loads the specified libraries into

the synthesis environment (and populates the /libraries virtual directory).

To append the main library database, enter set_attr library {{a.lib b.lib} c.lib {x.lib y.lib}} /

In this example, the compiler loads a.lib and appends b.lib to a.lib. Next, it loads c.lib. Then, it loads x.lib and appends y.lib to x.lib.

Setting Up Operating Conditions • Use the operating_condition attribute to set the operation condition. • Syntax • set_attr operating_condition <name_of_condition> /

– To find the available operating conditions in the library, use the find command for this. find /libraries –operating_condition *

– Specify the operating condition. set_attr operating_condition “WORST” /

operating_conditions(WORST) { process : 1 ; temperature : 125 ; voltage : 1.35 ; tree_type : balanced_tree ; } operating_conditions(TYPICAL) { process : 1 ; temperature : 70 ; voltage : 1.35 ; tree_type : balanced_tree ; } operating_conditions(BEST) { process : 1 ; temperature : 0 ; voltage : 1.35 ; tree_type : best_case_tree ; }

Section of the .lib file

Setting the Wire-Load Model By default, the compiler selects a

wire-load model automatically, if: Area based wire-load selection

is defined in library. Default wire-load model

attribute is set in the library. Use force_wireload attribute to

override this condition. Example The specified wire-load model on

the design is forced to use the 160K gates wire-load model.

/* wireload.lib file *//*Units: Capacitance - pF, Resistance - Ohm, Length - Micron. */wire_load_table ("suggested_10k") fanout_length( 1, 6.58 ) ; . . . . . fanout_length( 8, 92.11 ) ; fanout_capacitance( 1, 0.0009 ) ;

. . . . . fanout_resistance( 7, 0.37395 ) ; fanout_resistance( 8, 0.43046 ) ; fanout_area( 1, 0.0 ) ; . . . . . fanout_area( 8, 0.0 ) ; } /* End Of Wire Load Model */

wire_load_table ("suggested_160K") fanout_length( 1, 13.5077 ) ; . . . . . . . . . . . . } /* End Of Wire Load Model */

set_attr force_wireload /lib*/mylib/wireload_models/suggested_160K /des*/final

Setting the Wire-Load Mode Using the wireload_mode attribute

Syntax• set_attr wireload_mode <mode> /

Example set_attr wireload_mode top / Wire-load models are one of these

three types: TopEnclosedSegmented

20x20

40x40

60x60

60x60

mode=top

20x20

40x40

60x60

40x40

mode=enclosed

40x40

60x60

20x20 40x40 20x20

mode=segmented

wire_load_selection(predcaps){wire_load_from_area(0, 10000, "10K");wire_load_from_area(10000, 15000, "20K");wire_load_from_area(15000, 40000, "40K");...}default_wire_load_mode : segmented;default_wire_load_selection : predcaps;

Physical Layout Estimator (PLE) PLE is a physical modeling

technique that bypasses wireloads for RTL synthesis optimization. In place of wireloads, the compiler generates an equation to model the wire delay. PLE uses actual design and

physical library information. Dynamically calculates wire

delays for different logic structures in the design.

In most cases, PLE-synthesized designs correlate better with place-and-route tools.

Fanout Load1 0.00112 0.00923 0.01434 0.01995 0.02156 0.02787 0.03158 0.03909 0.045610 0.0577

Fanout Load1 0.00132 0.00993 0.01584 0.02125 0.02676 0.03127 0.03868 0.04679 0.057810 0.0699

Fanout Load1 0.00142 0.01073 0.01864 0.02845 0.03316 0.04017 0.04888 0.05929 0.068510 0.0811

Fanout Load1 0.00162 0.01113 0.02074 0.03035 0.03996 0.04957 0.05908 0.06879 0.078210 0.0879

Block ABlock B

Block C

Block D

LEF/Cap Table

set_attribute lef_library <lef header>

set_attribute cap_table_file <cap table>

set_attribute interconnect_mode ple /

Top

Block E

Preventing the Use of Specific Library Cells Use the avoid attribute to prevent the technology mapper from

using the particular cells.

Syntax set_attr avoid <true(1)/false(0)> <cell name(s)>

Example set_attr avoid 1 { mylib/snl_mux21_prx*}set_attr avoid 1 { /mylib/*nsdel}

The set_dont_use Tcl command in Design Compiler (DC) is supported in Encounter® RTL Compiler (RC), provided that this command appears inside your SDC file.

Reading Designs Use the read_hdl or read_netlist commands to parse the HDL

source. Syntax

read_hdl [-h][-vhdl|-sv][-v1995|-v2001][-netlist] [-define macro=name] file(s)<.gz>

-vhdl By default, the compiler reads VHDL-1993.-sv Read System Verilog files-v1995 (Boolean) force Verilog 1995 mode. -v2001 (Boolean) force Verilog 2001 mode.-define Define Verilog macros

ExamplesTo read the RTL or mixed source (RTL/gate) design:

read_hdl {design1.v subdes1.v subdes2.v}To read the gate-level (structural) netlist:read_netlist design_struc1.v

module TOP ( data_in , data_out , averg_per_sel ) ;

input [data_width1-1:0] data_in ;…

parameter data_width1 = 12;parameter averg_period = 8;parameter data_width2 = 16;

Elaboration of Designs The elaborate Command

– Builds data structures and infers registers in the design. Performs higher level HDL optimization, such as dead code removal. Uses generic gates in elaborated netlist

Elaborate is only required for the top-level design and it automatically elaborates all its references.

elaborate [-h] [-parameter {} ] [<top_module_name>]

Example

elaborate -parameter {12 8 16} TOP

When compiling, these parameters will be modified as follows:

data_width1 = 12 averg_period = 8 data_width2 = 16

parameter data_width1 = 3;parameter averg_period = 2;parameter data_width2 = 4;

Checking for Design Issues Use check_design to check for design problems such as

undriven or multi-driven ports and pins, unloaded sequential elements and ports, unresolved references, constant connected ports and pins, and any assign statements in the design.

Syntaxcheck_design [-undriven] [-unloaded] [-multidriven] [-unresolved] [-constant] [-assigns] [-all] [<design>] [> file]

If you do not specify any options, the check_design command reports a summary in a table format.

Specifying Design Constraints You can specify the design constraints in either of these

two ways:

SDC File (recommended) You can read SDC directly into the compiler after elaborating the top-level design. read_sdc <sdcFileName><.gz>

Encounter RTL Complier Tcl Constraints

Checking for Missing Constraints Use report timing -lint to check for missing constraints. Always run this

command and review the log file before synthesis. Here are some examples of missing constraint warnings:

Missing Constraint SolutionUnclocked primary I/Os Define external_delay for these I/Os.

Unclocked flops Check the fanin cone of these flops using the fanin command.

Multiple clocks propagating to the same sequential clock pin

To see which clocks are being propagated to that pin, use the inverting_clocks or non_inverting_clocks attribute of the pin. Use the timing_case_logic_value attribute to propagate only one clock to that pin (set_case_analysis).

Timing exceptions overwriting other timing exceptions, such as setting a false path and multicycle path starting in the same register.

Check the log file and remove the redundant ones.

Timing exceptions that cannot be satisfied, such as a false path that starts in a flop that was deleted.

Check the log file.

Setting User Priority and Deleting Constraints If a timing path satisfies two conflicting timing exceptions, and you

want to use one and not the other, set a higher priority on the desired exception by using the user_priority attribute.

Exampleset_attr user_priority 5 $my_multi_cycleset_attr user_priority 4 $other_exception

To delete a constraint without exiting the rc shell use the rm command.

Examplerm $my_multi_cycle

Synthesizing the Design The goal of synthesis is to provide the smallest possible implementation

of the design while meeting timing and power constraints. Use the synthesize command to run synthesis.

Syntax• synthesize [–to_generic] [–to_mapped] [-effort

<level>] [-incremental] [design|sub-design] -to_generic — Optimizes the MUX and datapath and stops before

mapping. -to_mapped — Maps the specified design(s) to the cells described

in the supplied technology library and performs logic optimization. -effort <level> — Can be low, medium (default) or high. -incremental/-no_incremental – turn incremental synthesis on/off as

part of single pass -csa_effort <level> - carry-save effort level – addresses equivalency

checking limitations By default, the synthesize –to_mapped command will run generic

optimization, mapping and incremental optimization.

Reporting report area Prints an exhaustive hierarchical area report.

report datapath Prints a datapath resources report.

report design_rules Prints design rule violations.

report gates Reports libcells used, total area and instance count summary.

report hierarchy Prints a hierarchy report.

report instance Prints an instance report.

report memory Prints a memory usage report.

report messages Prints a summary of error messages that have been issued.

report power Prints a power report.

report qor Prints a quality of results report.

report timing Prints a timing report.

report summary Prints an area, timing, and design rules report.

Generating Timing Reports

puts " WNS path/timing among all in2out paths" • report timing -from [all::all_inps] -to [all::all_outs]

puts “WNS path/timing among all in2reg paths"• report timing -from [all::all_inps] -to [all::all_seqs]

puts "WNS path/timing among CLK to outputs in domain $clk "• report timing -from $clk -to [all::all_outs]

puts "WNS path/timing among CLK to D paths in domain $clk"• report timing -from $clk -to [all::all_seqs]

puts "WNS path/timing among paths that cross from $clk to $clk2 domains"• report timing -from $clk -to $clk2

The all:: commands are Tcl procedures that are part of load_etc.tcl, which is part of your installation hierarchy. Please include load_etc.tcl before using these commands. The .synth_init is a good place to do this.

================================================================================Generated by: RTL Compiler (RC) 5.1Generated on: Nov 05 2004 02:33:19 PMModule: timing_exampleTechnology library: cb35os141d_typ 7.1/ 3.3bOperating conditions: NCCOM (balanced_tree)Wireload mode: segmented================================================================================Pin Type Fanout Load Slew Delay Arrival (fF) (ps) (ps) (ps)- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -(clock clk) launch 0 Rstage_y_reg_0/ cp 0 0 Rstage_y_reg_0/ q dfnrq1 1 101 41 +251 251 Rtiming_example/ y[0] <<< out port +0 251 R(ou_del_1) ext delay +0 251 R- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -(clock clk) capture 500 R- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -Timing slack : 249psStart- point : stage_y_reg_0/ cpEnd- point : y[0]

Fanout and Load: STA Using report timing

================================================================================Generated by: RTL Compiler (RC) 5.1Generated on: Nov 05 2004 02:33:19 PMModule: timing_exampleTechnology library: cb35os141d_typ 7.1/ 3.3bOperating conditions: NCCOM (balanced_tree)Wireload mode: segmented================================================================================Pin Type Fanout Load Slew Delay Arrival (fF) (ps) (ps) (ps)- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -(clock clk) launch 0 Rstage_y_reg_0/ cp 0 0 Rstage_y_reg_0/ q dfnrq1 1 1021 3741 +2051 2051 Rtiming_example/ y[0] <<< out port +0 2051 R(ou_del_1) ext delay +0 2051 R- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -(clock clk) capture 500 R- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -Timing slack : - 1551ps (TIMING VIOLATION)Start- point : stage_y_reg_0/ cpEnd- point : y[0]

Load exponentially affects delay.

================================================================================Generated by: RTL Compiler (RC) 5.1Generated on: Nov 05 2004 02:33:19 PMModule: timing_exampleTechnology library: cb35os141d_typ 7.1/ 3.3bOperating conditions: NCCOM (balanced_tree)Wireload mode: segmented================================================================================Pin Type Fanout Load Slew Delay Arrival (fF) (ps) (ps) (ps)- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -(clock clk) launch 0 Rstage_y_reg_0/ cp 0 0 Rstage_y_reg_0/ q dfnrq1 16 1021 3741 +4706 4706 Rtiming_example/ y[0] <<< out port +0 4706 R(ou_del_1) ext delay +0 4706 R- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -(clock clk) capture 500 R- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -Timing slack : - 4206ps (TIMING VIOLATION)Start- point : stage_y_reg_0/ cpEnd- point : y[0] Fanout exponentially affects delay.

Load exponentially affects delay.

STA Using report timing -exceptions================================================================================Generated by: RTL Compiler (RC) 5.1Generated on: Nov 05 2004 02:04:16 PMModule: addTechnology library: tutorial 1.0Operating conditions: typical_case (balanced_tree)Wireload mode: segmented================================================================================Pin Type Fanout Load Slew Delay Arrival (fF) (ps) (ps) (ps)- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -stage_a_reg_0/ CK <<< 0 0 Rstage_a_reg_0/ Q fflopd 2 25.7 17 +148 148 Rg82/ A +0 148g82/ Y nand2 3 45.9 52 +130 278 Fg81/ A +0 278g81/ Y inv1 1 10.5 15 +84 363 Rg66/ B +0 363g66/ Y nand2 1 10.5 45 +121 484 Fg62/ B +0 484g62/ Y nand2 1 15.5 46 +120 604 Rg59/ A +0 604g59/ Y xor2 1 20.5 58 +146 751 Rstage_y_reg_3/ D <<< fflopd +0 751stage_y_reg_3/ CK setup 0 +100 851 R- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - path_delay 100- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -Excepti on : ’path_delays/ del_1’ 100psTiming slack : - 751ps (TIMING VIOLATION)Start- point : stage_a_reg_0/ CKEnd- point : stage_y_reg_3/ D

Exceptions are reported here.

Wire-load mode segmented is not always recommended.

Generating Outputs Commands for Generating Outputs

Use the write_hdl command to generate a gate-level netlist. write_hdl > | >> filename

Use write_script command to generate the constraints file.write_script > | >> design_constraints.g

Use write_sdc command to export RTL Complier constraints in the SDC Tcl format. write_sdc [design] > | >> [filename]

Use the > symbol to redirect the output to a file or >> to append it to the file. write_hdl > <path to the output dir>/design.v

Example Script

set_attr information_level 9 /

set_attr lib_search_path <UNIX Library Search Path> set_attr hdl_search_path <UNIX HDL Search Path>

set_attr library {<library01> <library02> … <libraryNN> }

read_hdl { <design01>.v <design02>.v … <designNN>.v }

elaborate <TopLevel DesignName>

read_sdc constraints.sdc

synthesize -to_mapped

report timing -num_path 10 > timing_10_worst.rpt report area > area.rpt report gates > gates.rpt

write_hdl > <NetlistFileName> write_sdc > < file name>

Set the library and file search path.

Load all the modules of the design.

Elaborate the top level module.

Set the design and timing constraints.

Synthesize and map the design.

Create reports.

Write netlist and constraints to disk.

Load all the libraries for the design.

Set the diagnostic variables.

Command Help

You can get help on all the commands by entering: man command_name

To view man pages from the UNIX shell, set your environment using: setenv MANPATH $CDN_SYNTH_ROOT/share/synth/man

When you are unsure of a command, type the first few letters of the command and press the Tab key to display a list of commands that start with those letters.

Examplepath_ This command returns the following: ambiguous "path_": path_adjust path_delay path_disable path_group

Entering path_* -h does the same as the previous command and provides help for commands.

Thank You