1 Logic design of asynchronous circuits Part II: Logic synthesis from concurrent specifications.

1

Logic design ofasynchronous circuits

Part II:

Logic synthesis fromconcurrent specifications

ASPDAC / VLSI 2002 - Tutorial on Logic Design of Asynchronous Circuits

2

Outline

• Overview of the synthesis flow

• Specification

• State graph and next-state functions

• State encoding

• Implementability conditions

• Speed-independent circuit– Complex gates– C-element architecture


3

Specification(STG)

State Graph

SG withCSC

Next-state functions

Decomposed functions

Gate netlist

Reachability analysis

State encoding

Boolean minimization

Logic decomposition

Technology mapping

Design flow


4

x

y

z

x+

x-

y+

y-

z+

z-

Signal Transition Graph (STG)

xy

z

Specification


5

x

y

z

x+

x-

y+

y-

z+

z-

Token flow


6

x+

x-

y+

y-

z+

z-

xyz000

x+

100y+z+

z+y+

101 110

111

x-

x-

001

011y+

z-

010

y-

State graph


7

x z x y ( )

y z x

z x y z

Next-state functionsxyz000

x+

100y+z+

z+y+

101 110

111

x-

x-

001

011y+

z-

010

y-


8

x

z

y

Gate netlist

x z x y ( )

y z x

z x y z


9

Specification(STG)

State Graph

SG withCSC



Gate netlist


State encoding


Logic decomposition

Technology mapping

Design flow


10

VME bus

DeviceLDS

LDTACK

D

DSr

DSw

DTACK

VME BusController

DataTransceiver

BusDSr

LDS

LDTACK

D

DTACK

Read Cycle


11

STG for the READ cycle

LDS+ LDTACK+ D+ DTACK+ DSr- D-

DTACK-

LDS-LDTACK-

DSr+

LDS

LDTACK

D

DSr

DTACK

VME BusController


12

Choice: Read and Write cycles

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK- DTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

LDS-

LDTACK-DTACK-


13


DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

LDS-

LDTACK-DTACK-


14


DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

LDS-

LDTACK-DTACK-


15


DTACK-

DSr+

LDS+

LDTACK+

D+

DTACK+

DSr-

D-

LDS-

LDTACK-

DSw+

D+

LDS+

LDTACK+

D-

DTACK+

DSw-

LDS-

LDTACK-DTACK-


16

Circuit synthesis

• Goal:– Derive a hazard-free circuit

under a given delay model andmode of operation


17

Speed independence

• Delay model– Unbounded gate / environment delays

– Certain wire delays shorter than certain paths in the circuit

• Conditions for implementability:– Consistency

– Complete State Coding

– Persistency


18

Specification(STG)

State Graph

SG withCSC



Gate netlist


State encoding


Logic decomposition

Technology mapping

Design flow


19

STG for the READ cycle


DTACK-

LDS-LDTACK-

DSr+

LDS

LDTACK

D

DSr

DTACK

VME BusController


20

Binary encoding of signals

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+


21

Binary encoding of signals

DSr+

DSr+

DSr+

DTACK-

DTACK-

DTACK-

LDS-LDS-LDS-

LDTACK- LDTACK- LDTACK-

D-

DSr-DTACK+

D+

LDTACK+

LDS+

10000

10010

10110 01110

01100

0011010110

(DSr , DTACK , LDTACK , LDS , D)


22

QR (LDS+)QR (LDS+)

QR (LDS-)QR (LDS-)

Excitation / Quiescent Regions

ER (LDS+)ER (LDS+)

ER (LDS-)ER (LDS-)

LDS-LDS-

LDS+

LDS-


23

Next-state function

0 1

LDS-LDS-

LDS+

LDS-

1 0

0 0

1 1

1011010110


24

Karnaugh map for LDS

DTACKDSrD

LDTACK 00 01 11 10

00

01

11

10

DTACKDSrD

LDTACK 00 01 11 10

00

01

11

10

LDS = 0 LDS = 1

0 1-0

0 0 0 0 0 0/1?

1

111

-

-

-

---

- - - -

-

- ---

- - -


25

Specification(STG)

State Graph

SG withCSC



Gate netlist


State encoding


Logic decomposition

Technology mapping

Design flow


26

Concurrency reduction

LDS-LDS-

LDS+

LDS-

1011010110

DSr+

DSr+

DSr+


27

Concurrency reduction


DTACK-

LDS-LDTACK-

DSr+


28

State encoding conflicts

LDS-

LDTACK-

LDTACK+

LDS+

10110

10110


29

Signal Insertion

LDS-

LDTACK-

D-

DSr-

LDTACK+

LDS+

CSC-

CSC+

101101

101100


30

Specification(STG)

State Graph

SG withCSC



Gate netlist


State encoding


Logic decomposition

Technology mapping

Design flow


31

Complex-gate implementation

)(csccsc

csc

csc

LDTACKDSr

LDTACKD

DDTACK

DLDS


32

Implementability conditions

• Consistency– Rising and falling transitions of each signal

alternate in any trace

• Complete state coding (CSC)– Next-state functions correctly defined

• Persistency– No event can be disabled by another event

(unless they are both inputs)


33

Implementability conditions

• Consistency + CSC + persistency

• There exists a speed-independent circuit that implements the behavior of the STG

(under the assumption that ay Boolean function can be implemented with one complex gate)


34

Persistency

100 000 001a- c+

b+ b+

a

cb

a

c

b

is this a pulse ?

Speed independence glitch-free output behavior under any delay

a+

b+

c+

d+

a-

b-

d-

a+

c-a-

0000

1000

1100

0100

0110

0111

1111

1011

0011 1001

0001

a+

b+

c+

a-

b-

c-

a+

c-

a-

a-

d-d+

0000

1000

1100

0100

0110

0111

1111

1011

0011 1001

0001

a+

b+

c+

a-

b-

c-

a+

c-

a-

a-

d-d+

abcd 00 01 11 10

00

01

11

10 1

1 1 11

10

0 000

ER(d+)

ER(d-)

abcd 00 01 11 10

00

01

11

10 1

1 1 11

10

0 000

caadd

0000

1000

1100

0100

0110

0111

1111

1011

0011 1001

0001

a+

b+

c+

a-

b-

c-

a+

c-

a-

a-

d-d+

Complex gate


38

Implementation with C elements

CR

S z

• • • S+ z+ S- R+ z- R- • • •

• S (set) and R (reset) must be mutually exclusive

• S must cover ER(z+) and must not intersect ER(z-) QR(z-)

• R must cover ER(z-) and must not intersect ER(z+) QR(z+)

abcd 00 01 11 10

00

01

11

10 1

1 1 11

10

0 000

0000

1000

1100

0100

0110

0111

1111

1011

0011 1001

0001

a+

b+

c+

a-

b-

c-

a+

c-

a-

a-

d-d+

CS

Rdc

ca

0000

1000

1100

0100

0110

0111

1111

1011

0011 1001

0001

a+

b+

c+

a-

b-

c-

a+

c-

a-

a-

d-d+

CS

Rdc

ca

but ...

0000

1000

1100

0100

0110

0111

1111

1011

0011 1001

0001

a+

b+

c+

a-

b-

c-

a+

c-

a-

a-

d-d+

CS

Rdc

ca

Assume that R=ac has an unbounded delay

Starting from state 0000 (R=1 and S=0):

a+ ; R- ; b+ ; a- ; c+ ; S+ ; d+ ;

R+ disabled (potential glitch)

abcd 00 01 11 10

00

01

11

10 1

1 1 11

10

0 000

0000

1000

1100

0100

0110

0111

1111

1011

0011 1001

0001

a+

b+

c+

a-

b-

c-

a+

c-

a-

a-

d-d+

CS

Rdc

cba

Monotonic covers


43

C-based implementations

CS

Rdc

cbaC

d

ab

c

a

b

cd

weak

a

cd

generalized C elements (gC)

weak


44

Speed-independent implementations

• Implementability conditions– Consistency– Complete state coding– Persistency

• Circuit architectures– Complex (hazard-free) gates– C elements with monotonic covers– ...


45

Synthesis exercise

y-

z- w-

y+ x+

z+

x-

w+

1011

0111

0011

1001

1000

1010

0001

0000 0101

0010 0100

0110

y-

y+

x-

x+w+

w-

z+

z-

w-

w-

z-

z-y+

y+

x+

x+

Derive circuits for signals x and z (complex gates and monotonic covers)


46

Synthesis exercise

1011

0111

0011

1001

1000

1010

0001

0000 0101

0010 0100

0110

y-

y+

x-

x+w+

w-

z+

z-

w-

w-

z-

z-y+

y+

x+

x+

wxyz 00 01 11 10

00

01

11

10

-

-

-

-

Signal x

1

0

1

1

1

1

1

0 0

0

0

0


47

Synthesis exercise

1011

0111

0011

1001

1000

1010

0001

0000 0101

0010 0100

0110

y-

y+

x-

x+w+

w-

z+

z-

w-

w-

z-

z-y+

y+

x+

x+

wxyz 00 01 11 10

00

01

11

10

-

-

-

-

Signal z

1

0 0

0

0

11 1

0

0 0

0

1 Logic design of asynchronous circuits Part II: Logic synthesis from concurrent specifications.

Documents

lds ldtack

dtack lds

y slide

y z y

aspdac vlsi

logic synthesis

y state graph

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