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EE290C - Spring 2004Advanced Topics in Circuit DesignHigh-Speed Electrical Interfaces
Lecture #2Channels : Physical Components &
Channel ModelingJared Zerbe1/22/04
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Agenda
ComponentsBasic wiresReal wires & metricsDesign and modeling Channel model verification
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Signaling componentsLarge span of different types of interconnect
Chip to chip on a PCBShort, well controlled, often busses are cheapPackaging usually limits speed
Cables connecting chips on two different PCBsCables are lossy, but relatively clean if coaxConnector transitions usually the bad part
Caveat EmptorThere’s a lot of old junk out thereThere’s even new junk out therePeople are always looking for a way to run fast without spending $$ on expensive components
What’s an S21?An S21 (or S12) is simply a plot of output magnitude normalized to input magnitude as a function of frequency (plotted in –db or linear)Very helpful in forming understanding of channel characteristics
Conductor and Dielectric LossesPCB Loss: DC, skin & dielectric loss
Skin Loss ∝ √fDielectric loss ∝ f : a bigger issue at higher f
Frequency
8 mil wide and 1 m long 50 Ohm strip line
-40.0
-30.0
-20.0
-10.0
0.0
1.E+06 1.E+07 1.E+08 1.E+09 1.E+10
Frequency, Hz
Att
enua
tion
FR4Roger 4350
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Agenda
ComponentsBasic wiresReal wires & metricsDesign and modeling Channel model verification
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The Real Backplane Environment
ConnectorLine card trace
Package
Chip
Backplane trace Backplane via
Package-to-board via
Line card via
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Practical PCB Differential Wires
Differential signaling has nice propertiesMany sources of noise can be made common-modeDifferential impedance raised as f(mutuals) between wiresStrong mutual L, C can improve immunity
t
t
t
W S
-H
H+
SW
εr
t
t
H
+ -
µ - Strip Strip-line
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Differential Wires – O/E Impedance
As space increases between wires they become essentially single-endedRaise impedance of single-trace to make 100Ohm diff
0
10
20
30
40
50
60
70
0 1 2 3 4 5 6
S/W
impedance(Ω)
Zodd
Zeven
Zeven
Zodd
= 2 * common-mode impedance= ½ differential impedance
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Hspice Differential W-element Model
Freq dependent loss terms
Mutual terms
Rdx Ldx
Cdx Gdx
Diagonal terms ofMatrix; only one side
Compute RLGC at anyFrequency and you can computeRs, Gd
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ReflectionsSources of Reflections : Z - Discontinuities
Resonance Due to Via Stub ReflectionsLoss less transmission lines
Stub length = 7.5 mm (300 mil)
Stub delay = 50 ps
Backdrilling
depth: 200 mil
Stub length:
100 mil
Back Plane
Stub Stub
0.0
0.2
0.4
0.6
0.8
1.0
1.0E+08 1.0E+09 1.0E+10
Frequency, Hz
Nor
mal
ized
out
put
Single stub (50 ps, 50 ohms)
Two stubs (50 ps, 50 Ohms)
Single stub (50 ps, 30 ohms)
Single stub (17 ps, 50 ohms)
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SNR Degradation Due to NEXT
X
X
X
X
X
X
X
X
Tx Rx Tx
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0 100 200 300 400 500 600 700 800 900
Time, ps
Volta
ge, V Tx
Rx
XTX
Connector and Via near-end crosstalkStripline near-end crosstalkTx’s full swing couples to attenuated Rx signal
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SNR Improvement With Placement
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
0 100 200 300 400 500 600 700 800 900
Time, ps
Volta
ge, V Tx
RxXTX
X
X
X
X
X
X
X
X
Tx
Rx
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Skew within a Differential Link
Control skew as a percentage of UIA 1% skew for a 30” long link (Tpd of 5 ns) 5% UI at 1Gbps and 50% UI at 10GbpsMatching lengths may not guarantee zero skewCommon-mode signal generation
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Differential Intra-Pair Skew & Slot
Via is not pure transmission line, but 3D structureSkewed pairs look like S.E. pathThru vias in BP look like traces over slotted ground planeNet results is mode conversion, increased crosstalk all from intra-pair skewTight spec on intra-pair skew as a result of budgeting
Single Line with no slotSingle Line Over Slot
~ skew within diff thru via Diff pair with 0-skew over slot
Video source : SiQual/DesignCon’01
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Agenda
ComponentsBasic wiresReal wires & metricsDesign and modeling Channel model verification
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Methodology
TestStructures
2D/3DSimulations
ElementModels
Measured ChannelResponseChannel Model
Active (Si)techniques
SystemModel
SystemSimulations
Budgets SystemMeasurements
Test Chips
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Model Requirements
Component models are criticalPerformance bottlenecksDesign trade-offs Parameter SensitivitySilicon designBudgetingMargining
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12.5 Gbps Test Package Design Example
22 X 22 BGAWire-bonded4-Layer1 mm ball pitch
Source: Kyocera
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Package Modeling
Die to package transition
Package to board transition
Source: Kyocera
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Modeled S-Parameters
Source: KyoceraSource: Kyocera
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Issues in Line Card/Backplane DesignType of transmission lines
Edge coupled vs. broadside coupledTrace width and separation
Inter-pair coupling CrosstalkImplementation of AC coupling on the LC
Impedance discontinuitySkew
SW
T
S
WT
h2
h1
h1
h2
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Issues in Line Card Layout
Connector PackageCap
Connector Package
Connector PackageCap
DC coupled
AC coupled
AC coupled
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Trace Modeling
Parameter Width Spacing Thickness Bot. Height Top HeightW S T h1 h2
Designed 6.0 mil 8.0 mil 0.7 mil 8.0 mil 9.0 milModified by fab 6.7 mil 7.3 mil 0.5 Oz 8.0 mil 9.2 milMeasured 5.9 mil 8.0 mil 0.62 mil 7.7 mil 8.0 mil
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Trace and Via Characterization With Dual Microwave Probes
Source: GGB Industries Inc.
Probes can be placed directly on the differential via pairsTwo probes on one positionerProbe to probe spacing is user adjustable
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Measured and Modeled D-Mode S-Parameters
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Measured and Modeled C-Mode S-Parameters
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Through Hole Via Design ConsiderationsImpedance of the differential via pairInfluence of the anti-padNear-end and far-end crosstalk between differential via pairsCounter-boring considerations
ReliabilityImplementationNumber of counter-boring depthsYield lossCost
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Via Characterization
Differential traces
Various anti-pad sizes
Ground via
Via test structures No trace connections to the Vias
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Measured and Modeled S-Parameters of the Via
Zodd = 24 ohms Zeven = 39 ohms
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Via Modeling
50mil 50mil 50mil
Anti Pad36 mil
Pad26 mil
Drill16 mil
8 mil
Via impedance as a function of anti-pad
50mil Oval anti-pad
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Modeled S-parameters of Via
36mil anti pad 50mil oval anti pad 36mil oval anti pad
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Backplane Connector ConsiderationsImpedance profile, crosstalk and lossFoot print: routability, pin density, via impedanceNot truly differentialSkew Compensation on the line cardHigher cross-talk for outer pairsNEXT > FEXT
NEXT FEXT55 ps (20-80%) 55 ps (20-80%)80ps (10-90%) 80ps (10-90%)
AB 4.4% 3.7%DF 3.3% 2.6%GH 3.3% 2.6%JK 4.3% 3.5%
Source: Teradyne
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Simultaneous Modeling of Trace, Via and Connector With TRL Calibration
Even mode
Odd mode
Coupled Transmissionline model
ConnectorVia ViaTrace Trace
SMAMicrostrip transmission lines
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Measured and Modeled of S12
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Measured and Modeled of S11
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Counter-Boring ExampleNon-Counter-bored Vias
Counter-bored Vias
Middle strip line vias
Top strip
line via
300 mil
Header pin
Bottom strip line via
Bottom strip line via
Middle strip line vias
Top strip
line via
Counter-boring
depth: 200 mil Counter-boring
Depth: 105 mil
for both vias
Diameter: 45 mil
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Differential TDR Measurements of FR4 Backplane Vias
5.50E+01
6.50E+01
7.50E+01
8.50E+01
9.50E+01
1.05E+02
1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0
Time, ns
Diff.
Impe
danc
e, O
hms
tbm1m2tcm2c
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Differential TDR Measurements of Nelco 6000 Backplane Vias