Lecture 5: CMOS Transistor Theory - Piazza

Digital VLSI design

Lecture 5: CMOS Transistor Theory

Surprise QUIZ #1 (Discussion)

Q1. Sketch a transistor level schematic for Y= 𝐴𝐵 + 𝐶 𝐷𝐸.

Q2. Find the function, F, implemented by the following circuit

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Announcements

Labs: Form 2 person Teams by next class and let me know Work will be performed as a team but report and evaluation

will be individual

Term Project (team of 2, evaluation will be individual): Pick a Project by 26/08/2014

Based on something of interest to you Discuss thoughts with me List of suggestions will be available (but working on your own

idea is strongly encouraged) Complete design Evaluate design (for performance, power, etc.) Demonstrate operation Write report Meet intermediate and final deadline

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nMOS I-V Summary

2

cutoff

linear

saturatio

0

2

2n

gs t

dsds gs t ds ds dsat

gs t ds dsat

V V

VI V V V V V

V V V V

Shockley 1st order transistor models

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pMOS I-V

All dopings and voltages are inverted for pMOS Source is the more positive terminal

Mobility mp is determined by holes Typically 2-3x lower than that of electrons mn

Thus pMOS must be wider to provide same current Simple assumption,

mn / mp = 2

-5 -4 -3 -2 -1 0-0.8

-0.6

-0.4

-0.2

0

I ds(m

A)

Vgs

= -5

Vgs

= -4

Vgs

= -3

Vgs

= -2

Vgs

= -1

Vds

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Capacitance

Any two conductors separated by an insulator have capacitance

Gate to channel capacitor is very important Creates channel charge necessary for operation

Source and drain have capacitance to body Across reverse-biased diodes

Called diffusion capacitance because it is associated with source/drain diffusion

Interconnection wires also have (distributed) capacitance

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Gate Capacitance

Approximate channel as connected to source

Cgs = eoxWL/tox = CoxWL = CpermicronW

Cpermicron is typically about 2 fF/mm

n+ n+

p-type body

W

L

tox

SiO2 gate oxide

(good insulator, eox

= 3.9e0)

polysilicon

gate

Device Capacitance

The dynamic response (switching speed) of a CMOS circuit is very dependent on parasitic capacitances associated with the circuit

Use a simple approximation for quick estimates of capacitances; use tools for extraction of more accurate values from actual layouts

Consider the capacitances seen during the different regions of operation

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Pass Transistors

We have assumed source is grounded

What if source > 0? e.g. pass transistor passing VDD

Vg = VDD If Vs > VDD-Vt, Vgs < Vt

Hence transistor would turn itself off

nMOS pass transistors pull no higher than VDD-Vtn Called a degraded “1” Approach degraded value slowly (low Ids)

pMOS pass transistors pull no lower than Vtp

Transmission gates are needed to pass both 0 and 1

VDD

VDD

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Pass Transistor Ckts

VDD

VDDVs = VDD-Vtn

VSS

Vs = |Vtp|

VDD

VDD-Vtn VDD-Vtn

VDD-Vtn

VDD

VDD VDD VDD

VDD

VDD-Vtn

VDD-2Vtn

What would be the voltages on the different nodes?

Example

Assume: initial voltage of 0.5V on all the internal nodes

Vdd=1.0V, Vtn=0.2V and |Vtp|=0.2V

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Results

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Quiz II

Assumption: initial voltage on each node is 2.5 volts

Relevant transistor parameters are, Vdd=5V, Vtn=1V and |Vtp|=0.7V

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