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EECS 303 Lecture 1*Lecture 1Introduction to Digital Logic DesignHai ZhouEECS 303Advanced Digital DesignFall 2011

EECS 303 Lecture 1

EECS 303 Lecture 1*OutlineClass administrationDigital design methodologyRepresentations of Digital DesignIntroduction to Mentor Graphics toolsREADING: Chapter 1Chapter 2

EECS 303 Lecture 1

EECS 303 Lecture 1*Class AdministrationLectures twice a week, Tuesday-Thursday 3:30-4:50PMInstructor: Hai ZhouOffice: L461 TechEMAIL: [email protected]: 491-4155Teaching AssistantPeng KangOffice: M314 TechEMAIL: [email protected] Page: www.eecs.northestern.edu/~haizhou/303/

EECS 303 Lecture 1

EECS 303 Lecture 1*Class PrerequisitesEECS 203: Introduction to Computer EngineeringNeed to have basic understanding of digital systems, logic gates, combinational and sequential logicNeed to have been exposed to UNIX since we will use the Mentor Graphics tools on SUN workstationsClass will form a background for other classes in Computer EngineeringEECS 357: Introduction to VLSI CADEECS 355: ASIC & FPGA DesignEECS 361: Computer ArchitectureEECS 391: Introduction to VLSI Design

EECS 303 Lecture 1

EECS 303 Lecture 1*Class AdministrationRequired Textbooks:Mano and Kime, Logic & Computer Design Fundamentals, Prentice Hall.ClassnotesCopies of lecture transparencies to be made available

EECS 303 Lecture 1

EECS 303 Lecture 1*Class Grades5 Homeworks25% of grade5 Labs25% of gradeMidterm exam20% of gradeFinal exam30% of gradeHomeworks and labs will be due at the beginning of class on the due dateA penalty of 10% per working day will be assigned to late assignments or labs

EECS 303 Lecture 1

EECS 303 Lecture 1*Lab WorkYou will be introduced to the use of a commercial computer aided design tool from Mentor GraphicsWill use the Sun workstations in the Wilkinson Lab (3rd floor M wing of Tech)Lab Hours: OpenThere will be 5 labsLab 1: Tutorial on Mentor Graphics (simple logic)Lab 2: Design of combinational logic (8-bit adder)Lab 3: Design of ALU and shifterLab 4: Design of a simple 8-state finites state machineLab 5: Use of VHDL for combinational and sequential design

EECS 303 Lecture 1

EECS 303 Lecture 1*The Process of DesignDesignInitial concept: what is the function performed by the object?Constraints: How fast? How much area? How much cost?Refine abstract functional blocks into more concrete realizationsImplementationAssemble primitives into more complex building blocksComposition via wiringChoose among alternatives to improve the designDebugFaulty systems: design flaws, composition flaws, component flawsDesign to make debugging easierHypothesis formation and troubleshooting skills

EECS 303 Lecture 1

EECS 303 Lecture 1*Digital SystemsDigital vs. Analog WaveformsAnalog: values vary over a broad range continuouslyDigital: only assumes discrete values

EECS 303 Lecture 1

EECS 303 Lecture 1*Digital Hardware SystemsAlgebra: variables, values, operations

In Boolean algebra, the values are the symbols 0 and 1 If a logic statement is false, it has value 0 If a logic statement is true, it has value 1

Operations: AND, OR, NOTBoolean Algebra and Logical Operators

EECS 303 Lecture 1

EECS 303 Lecture 1*Digital Hardware SystemsCombinational logic no feedback among inputs and outputs outputs are a pure function of the inputs e.g., full adder circuit: (A, B, Carry In) mapped into (Sum, Carry Out)

Network implemented from switching elements or logicgates. The presence of feedback distinguishes between sequentialand combinational networks.Combinational vs. Sequential Logic

EECS 303 Lecture 1

EECS 303 Lecture 1*Digital Hardware SystemsSequential logic

inputs and outputs overlap outputs depend on inputs and the entire history of execution!

network typically has only a limited number of unique configurations these are called states e.g., traffic light controller sequences infinitely through four states

new component in sequential logic networks: storage elements to remember the current state

output and new state is a function of the inputs and the old state i.e., the fed back inputs are the state!Synchronous systemsperiod reference signal, the clock, causes the storage elements to accept new values and to change stateAsynchronous systemsno single indication of when to change state

EECS 303 Lecture 1

Case Study of a Simple Logic Design: Seven Segment DisplayChip to drive digital display

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Case Study (cont.)

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Case Study (cont.)Implement L4:Some gate level implementationof the Boolean function for L4

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EECS 303 Lecture 1*Representations of Digital Design: SwitchesA switch connects two points under control signal.

when the control signal is 0 (false), the switch is open

when it is 1 (true), the switch is closedwhen control is 1 (true), switch is open

when control is 0 (false), switch is closedNormally ClosedNormally Open

EECS 303 Lecture 1

EECS 303 Lecture 1*Switch RepresentationsExamples:routing inputs to outputs through a mazeFloating nodes: what happens if the car is not running? outputs are floating rather than forced to be falseUnder all possible control signal settings (1) all outputs must be connected to some input through a path (2) no output is connected to more than one input through any path

EECS 303 Lecture 1

EECS 303 Lecture 1*Switch RepresentationsImplementation of AND and OR Functions with SwitchesAND functionSeries connection to TRUEOR functionParallel connection to TRUE

EECS 303 Lecture 1

EECS 303 Lecture 1*Representations of a Digital DesignTruth Tablestabulate all possible input combinations and their associated output valuesExample: half adder adds two binary digits to form Sum and CarryExample: full adder adds two binary digits and Carry in to form Sum and Carry OutNOTE: 1 plus 1 is 0 with a carry of 1 in binary

EECS 303 Lecture 1

EECS 303 Lecture 1*Representations of Digital Design: Boolean AlgebraNOT X is written as XX AND Y is written as X & Y, or sometimes X YX OR Y is written as X + Yvalues: 0, 1variables: A, B, C, . . ., X, Y, Zoperations: NOT, AND, OR, . . .A

0011B

0101Sum

0110Carry

0001Sum = A B + A BCarry = A BOR'd together product terms for each truth tablerow where the function is 1

if input variable is 0, it appears in complemented form; if 1, it appears uncomplementedDeriving Boolean equations from truth tables:

EECS 303 Lecture 1

EECS 303 Lecture 1*Representations of a Digital Design: Boolean AlgebraA

00001111B

00110011Cin

01010101Sum

01101001Cout

00010111Another example:Sum = A B Cin + A B Cin + A B Cin + A B CinCout = A B Cin + A B Cin + A B Cin + A B Cin

EECS 303 Lecture 1

EECS 303 Lecture 1*Gate Representations of a Digital Designmost widely used primitive building block in digital system designStandardLogic GateRepresentationHalf Adder SchematicNetlist: tabulation of gate inputs & outputs and the nets they are connected toNet: electrically connected collection of wires

EECS 303 Lecture 1

EECS 303 Lecture 1*Representations of a Digital Design: GatesFull Adder SchematicFan-in: number of inputs to a gateFan-out: number of gate inputs an output is connected to

Technology "Rules of Composition" place limits on fan-in/fan-out

EECS 303 Lecture 1

EECS 303 Lecture 1*Waveform Representationdynamic behavior of a circuitreal circuits have non-zero delaysTiming Diagram of the Half Addersumpropagationdelaycircuit hazard: 1 plus 0 is 1, not 0!sumpropagationdelayOutput changes are delayed from input changes

The propagation delay is sensitive to paths in the circuit

Outputs may temporarily change from the correct value to the wrong value back again to the correct value: this is called a glitch or hazard

EECS 303 Lecture 1

EECS 303 Lecture 1*Block Representation of a Digital Designstructural organization of the design

black boxes with input and output connections

corresponds to well defined functions

concentrates on how the components are composed by wiring Full Adder realized in terms ofcomposition of half adder blocksBlock diagram representationof the Full Adder

EECS 303 Lecture 1

EECS 303 Lecture 1*Introduction to Mentor Graphics ToolsThe Mentor Graphics CAD system has many componentsYou will use a small portion of the tools for this courseFalcon Design FrameworkDesign Architect for entering logic designsQuicksim for simulating the designsQuickHDL for entering and simulating the VHDL designsRead through and execute Lab 1: Mentor Graphics tutorial

EECS 303 Lecture 1

EECS 303 Lecture 1*Introduction to Mentor GraphicsTyping source /vol/ece303/mgc.env on Sun workstation will set up env for 303 labsTyping dmgr for Design Manager will create a window for running several toolsMentor Graphics is not a single tool but a series of design tools that uses object oriented data representation to simplify the design processData created in one tool (e.g. design architect) can be shipped to another tool (e.g. quicksim) for simulationA schematic is merely a pictorial representation of a circuit

EECS 303 Lecture 1

EECS 303 Lecture 1*Viewpoints in Electronic Design ObjectsData created by DESIGN ARCHITECT is saved inComponentViewpointA component is a collection of models used to describe the functional, graphical aspectsComponent data is made of a schematic and a symbolA symbol is a graphical model of the input and output pinsA schematic is a functional model of how outputs are related to input valuesA viewpoint can be thought of as a filter that other applications use to process component dataComponentViewpointElectronic Design ObjectSymbol forXOR

EECS 303 Lecture 1

EECS 303 Lecture 1*Moving Design DataStudents familiar with UNIX, please refrain from using UNIX commands to move directories or filesYou MUST move these objects using the Design ManagerFailure to use Design Manager will result in data corruptionDesign Architect will store the absolute pathname to a designQuicksim will try to use the symbol to look for the design from that pathname

EECS 303 Lecture 1

EECS 303 Lecture 1*SummaryClass administrationDigital design methodologyRepresentations of Digital DesignIntroduction to Mentor Graphics toolsNEXT LECTURE: Memory ElementsREADING: Chapter 4

EECS 303 Lecture 1