1 Digital Integrated Circuit Design Digital Integrated Circuit Design L1 Introduction EE141 1 General Information General Information Instructor : Jinyong Chung [email protected]Room 312, LG Research Building(Tue, Thu) Mailbox @copyroom on 2 nd floor Office: x5016(LG312), x0204(NCNT) Grading Homework - 30% EE141 2 Term Project - 30% Midterm Exam - 20% Final Exam - 20%
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
1
Digital Integrated Circuit DesignDigital Integrated Circuit DesignL1 Introduction
EE141 1
General InformationGeneral Information
Instructor : Jinyong [email protected] 312, LG Research Building(Tue, Thu), g( , )Mailbox @copyroom on 2nd floorOffice: x5016(LG312), x0204(NCNT)
GradingHomework - 30%
EE141 2
Term Project - 30%Midterm Exam- 20%Final Exam - 20%
2
(continued)(continued)
Design Project32bit x 32bit NAND Flash
1.8V operationtransistor model: TBPControl logic (ECC optional) design & simulationcircuit design and simulationReport on target & performance comparison
EE141 3
Report on target & performance comparison /analysisFinal Report by 12/11
(continued)(continued)Baseline textbook디지털집적회로, 대영사, 박홍준Digital Integrated Circuits By J. Rabaey, A. Chandrakasan, B. Nikolicy y, ,Prentice Hall
ReferenceAnalysis and Design of Digital Integrated Circuits
in deep submicron technologyBy D. Hodges, H. Jackson, R. SalehMcGraw Hill
EE141 4
Class Material on webClass schedule
Mid term: 10/21 (Tue)Final on 12/18 (Thu)
3
Class GoalsClass GoalsDigital Integrated Circuits
CMOS gatesPropagation delay, noise margins and power dissipation FOM’sdissipation, FOM sCombinational and sequential circuitsArithmetic, Datapath, Memory, Clock and InterconnectDesign for Testability
What will you learn?U d t di d i i d ti i i di it l
EE141 5
Understanding, designing and optimizing digital circuits with respect to quality metrics: speed, power, cost and reliabilityCircuit Design (design & simulation, layout) on flash memory
Digital Integrated CircuitsDigital Integrated CircuitsIntroduction: Issues in digital designTh CMOS i tThe CMOS inverterCombinational logic structuresSequential logic gatesMemory CircuitDesign for TestabilityInterconnect: R L and C
EE141 6
Interconnect: R, L and CTimingArithmetic building blocksDesign methodologies
4
IntroductionIntroductionWhy is digital IC design different today than it was before?Differences from other disciplinesFuture perspectives
EE141 7
The First Integrated Circuits The First Integrated Circuits
Wires (65nm process)8 layers of Metal (Cu)4 in X, 4 in Y directionVias connect layersWire delay determined by C and R Higher layer – bigger wire - smaller delayWidth can be controlled
EE141 12
Width can be controlled
From Mark Bohr Intel
7
Process scalingProcess scalingHigh Volume High Volume ManufacturingManufacturing
Delay = CV/I scalingDelay = CV/I scaling 0.70.7 ~0.7~0.7 >0.7>0.7 Delay scaling will slow downDelay scaling will slow down
Energy/Logic Op Energy/Logic Op scalingscaling
>0.35>0.35 >0.5>0.5 >0.5>0.5 Energy scaling will slow downEnergy scaling will slow down
Bulk Planar CMOSBulk Planar CMOS High Probability Low ProbabilityHigh Probability Low ProbabilityAlternate, 3G etcAlternate, 3G etc Low Probability High ProbabilityLow Probability High Probability
EE141 13
VariabilityVariability Medium High Very HighMedium High Very HighILD (K)ILD (K) ~3~3 <3<3 Reduce slowly towards 2Reduce slowly towards 2--2.52.5RC DelayRC Delay 11 11 11 11 11 11 11 11Metal LayersMetal Layers 66--77 77--88 88--99 0.5 to 1 layer per generation0.5 to 1 layer per generation
From Pat Gelsinger Intel
Moore’s Law and its costs Moore’s Law and its costs
1.E+01
1.E+02
1.E+03
1.E+04
MIP
s
$ per MIPS$ per MIPS
$100
$1,000
$10,000
st ($
M)
FAB CostFAB Cost
1.E-02
1.E-01
1.E+00
1960 1970 1980 1990 2000 2010
$/M
1 E 03
1.E-02
1.E-01
stor
$ per Transistor$ per Transistor
1.E+01
1.E+02
1.E+03
l ($)
Per ChipTest CapitalTest Capital
$1
$10
$100
1960 1970 1980 1990 2000 2010
Fab
Cos
www.icknowledge.com
EE141 14
1.E-06
1.E-05
1.E-04
1.E-03
1960 1970 1980 1990 2000 2010
$/Tr
ansi
s
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1980 1990 2000 2010
Test
Cap
ital
Based on SIA roadmap
Intel
8
Moore’s LawMoore’s LawIn 1965, Gordon Moore noted that the
number of transistors on a chip doublednumber of transistors on a chip doubled every 18 to 24 months.
He made a prediction that semiconductor technology will double its effectiveness every 18 months
Why Scaling?Why Scaling?Technology shrinks by 0.7/generationWith every generation can integrate 2x more functions per chip; chip cost does not increase significantlyCost of a function decreases by 2xBut …
How to design chips with more and more functions?Design engineering population does not double every
EE141 25
Design engineering population does not double every two years…
Hence, a need for more efficient design methodsExploit different levels of abstraction
Noise BudgetNoise BudgetAllocates gross noise margin to expected sources of noiseSources: supply noise, cross talk, interference, offsetDifferentiate between fixed and
SummarySummaryDigital integrated circuits have come a long way and still have quite some potential left for th i d dthe coming decadesSome interesting challenges ahead
Getting a clear perspective on the challenges and potential solutions is the purpose of this book
Understanding the design metrics that govern digital design is crucial
EE141 50
digital design is crucialCost, reliability, speed, power and energy dissipation