10VGA.ppt [호환 모드] - chungbuk.ac.kr

VGAVGA

충북대학교 전자정보대학 김영석

2 1 92010.9

1

Outline1. AGC System

I t d ti– Introduction– System Analysis

2. VGA – Control Block– Gain Cell

3. RSSI– Limiting Amplifier– Rectifier

2전자정보대학 김영석

AGC in GPS ReceiverRF Freq = 1.575GHzIF F 4 092MHIF Freq = 4.092MHzIF Bandwidth = 2MHzBPF selects GPS signal, but rejects the Image

3Torrre07,GloNav


AGC in GPS Receiver• AGC Input: Below Thermal Noise • AGC Output: ADC Full ScaleAGC Output: ADC Full Scale• AGC 40dB Variable Gain Range• MOSFET M1,2 in Triode ,

=> Variable Gain• Removes DC Offset • AGC Loop

4 4전자정보대학 김영석

AGC TheoryAGC(Automatic Gain Control): Automatically Controlling Gain, High Enough to Operate ADC

y

Originally Used to Remove Radio FadingAmplifying Vin => Peak Detection => Low pass Filtering Compare with VREF => Loop Filter => VGA Gain ControlCompare with VREF => Loop Filter => VGA Gain Control

V O U T

PeakD etector

VG AV IN

LPF

V C

LoopFilter V R EF

+-


AGC with Several VGA StagesLarge Gain in the 1st Stage Reduce the Noise FigureBut When Signal Large Enough

g

g g gNoise Figure Not CriticalGain of 1st Stage May Be Low

LPF LPFVG A VG A LPF Buffer

R F Front-End

X1

BasebandD em odulator

R SSI

Analog Baseband AG C


AGC Transfer CharacteristicsVi < V1 (Low Input)

AGC InoperativeLinear

V1< Vi <V2AGC OperativeAGC OperativeOutput Constant

Vi > V2 (High Input)AGC InoperativeLinearPrevent System InstabilityPrevent System Instability Problems

7

Modern Communication Circuits, Smith


AGC: Linear in Decibels

Linear in DecibelsGain in decibels (dB) vary linearly with VCGain in decibels (dB) vary linearly with VCIf Input has Step Increase in 3dB, Output has Step Increase of 3dB and Decay Exponentially after Settling Time

, : 1 PVVeKPAmpGainVariable ioaVc ==

))((:)ln(:

:

2

122

1

VVsFVVoltageControlVKVAmpcLogarithmi

VVDetectorEnvelope o

−==≈

)log(20 ),log(20 )(ln)](1[ln ,

))((: 2

VeVeletVsaFVsaFVSolving

VVsFVVoltageControl

iioo

rio

rc

==+=+

)(1)(7.8

)(1 saFVsaF

saFe

e rio +

++

=∴

8Modern Communication Circuits, Smith



F(s) usually LPF Loop Bandwidth < Modulating Frequency(AM)Loop Bandwidth < Modulating Frequency(AM)

Steady State Output Change = SmallL G i LLoop Gain = Large

Fe

ChangeStateSteady o 0)0(1

1: ≈+

=ΔΔ

S t DC O t t i D ib l P ti l t V

FilterofGainDCFwhereaFei

)0( )0(1

=+Δ

System DC Output in Decibels Proportional to Vr

)( =KsFlet

)1( 655.81655.8

1:

/1)(

>>≈+

++

=

+=

aKVaKaKV

aKe

eOutputDC

BssFlet

rri

o



Closed-Loop Transfer FunctionaK > 0 => LHP Pole => /1

)( Bs

KsFlet+

=aK 0 LHP Pole Inherently StableAGC = High Pass Filter

1

1

1

/1

sBs

aKe

e

Bs

io

+

+

+Δ

=Δ

+

Low Freq: Output Change = Small (AGC Operation)High Freq: Output Pass =>

)1(1

aKB ++

High Freq: Output Pass AGC NonOperation (Ex: Pass AM Signal)wL =B(1+aK) < wM(AmplitudewL =B(1+aK) < wM(Amplitude Modulation Freq)



Filter = Integrator (Infinite DC Gain)C

ri aCVssese

sCsF

655.8)()(

)(

+=

=

rot

o

VteOutputStateSteadyaCsaCs

se

655.8)(lim:

)(

0=

++

+

→

Ex: Time Response to a Step Change in InputTime Constant of Exponential Decay = AGC Bandwidth = aC

i

i

sesse

DecibelChangeStepUnits

se

Δ=Δ

=Δ

)()(

), (1)(

aCtoo

o

eteaCs

se

aCsse

−=Δ+

=Δ∴

+Δ

)( ,1)(

)(


AGC: Pseudo-Linear• No Logarithmic Amp => NonLinear System

V

oo

orc

ioaV

PVdVS l i

VVsFVVoltageControlPVVeKPAmpGainVariable c

/))((:

,: 1

−===

• Loop Transmission ci

ii

oo

dVdPVsFVdV

Solving)(1/

,+

=

– Nonlinear, Function of Input Signal– BW = Pole = 1/Speed =Input Signal Dependent


AGC: Psuedo-Linear

Ex: No Log Amp, P=Vc(linear), F(s)=K/sVdV /

ci

ci

ii

oo

sKV

P

dVdPVsF

PVdVVdV

+=

+=

1)(1//

i

i

i

cc

sΔ

sVΔV

InputinChangeStepSmall =)( :

tKVi

o

o

i

i

o

o ieΔtVΔV

KVsΔ

sVΔV −=

+=∴ )( ,)(

Time Constant (Speed) of AGC is Dependent on Input Signal Amplitude Vi


AGC System Componentsy pExponential Amp (VGA)

LT

cLm

o RVI

RgVV

V

21 −=−=

−

cTc

aVL

T

VVs eKRVeI

1

/ =−=

Logarithmic Amp

/C

VVs

s

i

V

eIRV

I To==

)ln(ss

iTo IR

VVV =


AGC Settling TimePreamble Duration > Settling (Acquisition) Time of AGC Loop

g

Nonlinear AGC System => Settling Time is Input Signal Dependent. Long Preamble 2

1)( VkGC ekVG CG= ⋅Long Preamble

Addition of Logarithmic Function => Linear in Decibels

212

2)(

vGM

GC

kkGC

ekVG

=

=

τ

Analysis:VGA Must Have Exponential Function

21)( Vk

GC

CekVG CG= ⋅

Constant AGC Time ConstantWithout Log Amp, AGC Operates OK But Nonlinear AGC Time

212 vGM kkGC

=τ

OK. But Nonlinear AGC Time Constant. Inversely Proportional to VREF=VIN

REFGM VkGC

12=τ

15

Khoury98


AGC Settling TimeAGC ABM(Analog Behavioral Model) SimulationAGC1: VGA with Exponential Gain Control

g

AGC2: VGA with Linear Gain Control=> Input Decrease => Longer Time Constant

ss

VGeG CVC

μτμτ

503TimeSettling 163.0

331, 2535.1

1

≈≈=>=

+==

sμτ 5.03TimeSettling ≈≈=>

16Khoury98


VGA Theory• VGA(Variable Gain Amplifier: 자동 이득 조절기): Voltage Gain (dB) is Linear to

Control Signal

y

• Voltage Gain is dB => VGA Gain has dB-Linear Char.• VGA = Exp Amp (cf: RSSI = Log Amp)

G i C t l b Di it l Si l 2NR• Gain Control by Digital Signal 2 R

2R

R

• Gain Control by Analog Signal

V IN

V O UT

-

+

VIN +

2II Δ

+2II Δ

−II Δ+

VIN -

TriodeTransistor


VGA Exponential Function ApproximationVGA Has Exponential Function of Control Signal

p pp

Control SignalExponetial Function Approximations

Pseudo Exponential (Harjani95)p ( j )

Taylor Series (Chang01)

Pseudo Exp + Taylor (Dong05)Pseudo Exp + Taylor (Dong05)


VGA Exponential Function ApproximationPseudo Exponential Appro.[Harjani95]-0.7<x<0.7, 30dB Gain Variability=>

p pp

Require 2 Stages for 60dBDifferential Pairs Q1,Q2 + Load Q3,Q4 Voff: Current Mirror in SaturationVoff: Current Mirror in Saturation Region3rd Stage: Large Diff Gain, CMFB

11)( 2

ax

axax

axax

eeexf

−+

≈==−

)/1()/1(

Required Stages 2/1/1

1

111

1

1

3

1

3

1

bbb

bbbD

b

b

m

m

IIIIIIIIIIIIIIII

gg

Gain

axe

−=−=+=+=

=>−+

==ββ

)/1( 113 bbbD IIIIII ==


VGA Exponential Function ApproximationPseudo-exponential[Motamed98]Exp(Control Current IC) => I1/I2

p pp

cnxn Ixwheree

xx

IIxf α==

−+

== )11()( )2(

2

1

I1/I2 => Vds

2

113

2453

33

1

II*IRV

*IRV

)-V*(VKI

-triodeNds

/NPG

THG∝==

=

Vds => Multiplier

2

p


VGA Exponential Function Approximation

Pseudo-exponential[Huang98] 5.0)

11(

)()(

/ xKIIII

II

ggGain controlbiasiiiloadminputm

+=

+===

ββ

ββ

p pp

exponential[Huang98]Diff Pairs M1/M2, Diode Connected

,, )1

()( xIII

ggcontrolbiaslll

loadminputm −−ββ

Diode Connected Loads M3/M4

Cascading Two Cells => Exp(x)=> Exp(x)


VGA Control Block• Control Block : x=Vc

22

Duong06


VGA Gain CellGain Cell + CMFB

23

Duong06


VGA2 VGA StagesTechnology: 0.18umVDD=0.18V, I=3.6mABandwidth: 40MHz – 1GHzGain Variation: 48dB 26dBGain Variation: -48dB – 26dB

24

Duong06


DC Offset CancellationDC Output Feedback to Input Through LPF. HF Signal Does not Pass.Adding this DC Output (-) to DC Input => Remove DC Offset DC Offset is Removed in First Stage before It Becomes Too LargeResidual Offset is removed in Last Stage

25

Ta05


VGA ExampleVGA Control Block

p

0674

)1()1()(

25

262

22

=

=−+++

≈==−

aSimulationFromVx

II

axkaxk

eeexf

C

D

Dax

axax

067.4, =aSimulationFrom


VGA ExampleGain Block with CMFB

p


VGA ExampleVGA Output: AC, Transient

p


VGA ExampleCMFB

p


AGC ExampleAGC Block Diagram2 VGAs


AGC Example

3 VGAs


AGC Example

Error Amp + Full Wave Rectifier(FWR)


RSSIRSSI(Received Signal Strength Indicator): Represent the Received Signal Strength Used to Adjust Gains of Baseband Processor. Power Off when No SignalMagnitude of Received Signal [dBm], RSSI Transfer Char. V vs dBm. g g [ ]RSSI is Log Amplifier. (cf. VGA is Exponential Amp)Ref: Huang00


Log Amplifier

)log( xy =

• Char.

g p

)log( xy =

• Input Sine Wave modulated by• Input Sine Wave modulated by Triangular Signal => Log Output of Triangular Signal

• ASK Amplitude => Log of Amplitude Pulse


Log AmplifierLog Amp

Limiting Amp + FWR(Full Wave Rectifier)

g p

Summation + LPFGain and Bandwidth of Unit Limiting Amp

(N # f St At T t l V lt G i )(N = # of Stages, At=Total Voltage Gain)


Log Amplifier• Clipping by 1st Stage:

g p

• Clipping by 2nd Stage:

V IN

4V L

5V L

V]

T rue Logarithm ic R esponse

L ith i E

A vV IN

∑

V IN

V 1

V 2

V 3

V n

V O UT

A v A v A v V log

LPF

3V L

2V L

V

V OU

T [VLogarithm ic Error

Logarithm ic O utput

V L

5V

L

AV

4V

L

AV

3V

L

AV

2V

L

AV

V

L

AV

0-100

6V

Lt A

VV ≈

10-5 1

36

V IN [dB m , V]


Limiting AmplifierConventional NMOS Load: Low Voltage Operation is Difficult due to Body Effect =>

g p

Operation is Difficult due to Body Effect => Folded Load

M 3 M 4

V (+) V ( )

V out(-) V out(+)

M 1 M 2 V (+) V ( )

V out(-) V out(+)

M 1 M 2

M 3 M 4

V B2

ID 3 ID 1

V in(+) V in(-)

V B

M 1 M 2 V in(+) V in(-)

V B1

M 1 M 2


Limiting Amplifier(1) An NMOS differential pair with NMOS loads [Khorram95]

g p

3

1m

gg

Gain =3mg

(a) (b)


Limiting Amplifier(2) Source-coupled pair with Folded diode load [Huang00] =>Low Voltage operation

g p

load [Huang00] =>Low Voltage operation1m

gg

Gain =3mg


Limiting Amplifier(3) Current mirror type [Kim01]:

Khorram95: Load has Body Effect

g py

Eliminate Body Effect. Low Voltage Operation. But High Current Consumption

3

1

m

m

gg

Gain =


RectifierFWR(Full Wave Rectifier)Tie 2 Current Mirrors =>Tie 2 Current Mirrors => FWR-out ResistorVin(+) > Vin(-): ID1 > IBVin(+) > Vin(-): ID1 > IB, Current Mirror 1 On => Current to FWR-out Vin(+) < Vin(-): ID2 < IB, Current Mirror 2 On =>Current to FWR-out => Full Wave Rectification


Rectifier(1) Unbalanced Source-Coupled Pairs [Kimura93]Linearity Improvements by Unbalanced Source-Coupled Pair(M1-M4)y p y p ( )Vin+ > Vin- : ID3, ID6, ID8 Increase => Output HighVin+ < Vin- : ID2, ID6, ID8 Increase => Output High => FWR


Rectifier(2) Source degenerated differential pairs and two current mirrors [Kim01]Source degenerated differential pairs => Improve LinearityVin+ > Vin- : ID1, ID3, ID5 Increase => Output HighVin+ < Vin : ID2 ID4 ID6 Increase => Output High => FWRVin+ < Vin- : ID2, ID4, ID6 Increase => Output High => FWR


Rectifier(3) Multiplier based on Gilbert cells [Khorram95]Four-Quadrant MOS MultiplierQ p


Rectifier(4) Open-loop Current-mode rectification [Huang00]Depending on Iin Direction =>Mrn/MrpON/OFF (Half Wave Rec.)Two Parallel Circuits => Full Wave RecTwo Parallel Circuits => Full Wave Rec.Instead of Mrp, NMOS Didoe Mr1 is usedMg1-Mg4: Convert V => Ig g


DC Offset CancellationDC offset cancellations(1) feedback type [Huang00]( ) yp [ g ]


RSSI ExampleLimiting AmplifierGain =gm21/gm23= 10dB

pg g


RSSI ExampleFull Wave Rectifier

p


RSSI ExampleFWR DC Transfer Curve/Transient Char.

p


RSSI ExampleRSSI

p


RSSI ExampleRSSI Output

1.0V

p

0.5V

0V

Time

50us 100us 150us 200usV(vi+) V(fwr1:fwr_out)


ConclusionAGC System

Linear in Decibels AGCLinear in Decibels AGC Pseudo-Linear AGC

VGAControl BlockGain BlockExample

RSSILimiting AmplifierRectifierE lExample


평가 문제1. Linear in Decibels AGC System의 블록 다이어그램을 그려라.2. Linear in Decibels AGC System과 비교하여 Pseudo-Linear AGC

평가 문제

System의 문제점은 무엇인가?3. Linear in Decibels AGC System에서 사용되는 VGA는 출력 전압이 제어전

압에 대해서 어떤 특성(함수)을 가지나?압에 대해서 어떤 특성(함수)을 가지나?4. RSSI의 출력은 입력 전압에 대해서 어떤 함수를 가지나?


참고 문헌[Chang01] C.-C. Chang et al., “CMOS Current-Mode Exponential-Control Variable-Gain Amplifier”, Electronics Circuits, vol. 37, pp. 868-869, 2001.[Duong05] Q-H. Duong et al., “An All CMOS 84dB-Linear Low-Poer Variable Gain Amplifier”, Symposium on VLSI

참고 문헌

Circuits, pp. 114-117, 2005.[Harjani95] R. Harjani, “A Low-Poer CMOS VGA for 50 Mb/s Disk Drive Read Channels”, IEEE Trans. Circuits Syst. II, vol. 42, pp. 370-376, 1995.[Huang98] P.-C. Huang et al., “A 3.3-V CMOS Wideband Exponential Control Variable-Gain-Amplifier”, ISCAS, pp. 285 288 1998285-288, 1998.[Huang00] P-C. Huang, “A 2-V 10.7-MHz CMOS Limiting Amplifier/RS냐”, IEEE J. of Solid-State Circuits, vol. 35, pp. 1474-1480, 2000.[Kim01] H.-S. Kim et al., “CMOS Limiters with RSSI for Bluetooth Receivers”, MWSCAS, pp. 812-815, 2001.[Kimura93] K Kimura “A CMOS Logarithmic IF Amplifier with Unbalanced Source Coupled Pairs” IEEE J of[Kimura93] K. Kimura, A CMOS Logarithmic IF Amplifier with Unbalanced Source-Coupled Pairs , IEEE J. of Solid-State Circuits, vol. 28. pp. 78-83, 1993.[Khorram95] S. Khorram et al., “A CMOS Limiting Amplifier and Signal-Strength Indicator”, Symp. on VLSI Circuits, pp. 95-96, 1995.[Khoury98] J. M. Khoury, “On the Design of Constant Settling Time AGC Circuits”, IEEE Trans. Circuits Syst. II, [ y ] y, g g , y ,vol. 45, pp. 283-294, 1998.[Motamed98] A. Motamed et al., “A Low-Voltage Low-Power Wide-Range CMOS Variable Gain Amplifier”, IEEE Trans. Circuits Syst. II, vol. 45, pp. 800-811, 1998.[Smith98] Modern Communication Circuits, 2nd Edition, J. R. Smith[Ta05] C. M. Ta et al., “A 2.7mW, 0.064mm2 Linear-in-dB VGA with 60dB Tuning Range, 100MHz Bandwidth, and two DC Offset Cancellation Loops”, RFIT2005, pp. 74-77, 2005.[Torre07] V. D. Torre, “A 20 mW 3.24 mm2 Fully Integrated GPS Radio for Location Based Services”, IEEE J. of Solid-State Circuits, vol. 42, pp. 602-612, 2007.


10VGA.ppt [호환 모드] - chungbuk.ac.kr

Documents