Kyle Campbell ECE 518 Memory Circuit Design Boise State University …cmosedu.com/jbaker/courses/ece5418/s10/proj1.pdf · 1 Kyle Campbell ECE 518 Memory Circuit Design Boise State

1

Kyle CampbellECE 518 Memory Circuit Design

Boise State University04/28/2010

2

DLL use in SDRAMCharge Pump DLL DescriptionExample Circuits from literature that address problemsDrawbacks and Benefits

3

High speeds require internal and external clocks to be synchronized.Starting with DDR SDRAM, Joint Electron Device Engineering Council (JEDEC), committee JC42 has included a DLL as part of the specification.

*JEDEC DOUBLE DATA RATE (DDR) SDRAM SPECIFICATION JESD79F

4

Charge pump phase detectors are used with a loop filter to generate an analog bias voltage for an analog delay lineData is delayed to bring φout close to φclock

[1]

5

PD generated “Up” pulse adds charge to CLF, increasing VCtrlPD generated “Down” pulse removes charge from CLF, reducing VCtrlBelow are two charge pump examples from the DRAM Circuit Design text.

[2]

6

Solution 1 - Jitter and Lock Speed [3]Solution 2 - Trigger timing, jitter caused by metastability of PD. [4] Solution 3 - Bandwidth and Standby Power [5]Discussion on noise rejection

7

“Fast-Lock Dual Charge Pump Analog DLL using Improved Phase Frequency Detector” [3]◦ Conventional analog DLLs have an ideally linear transfer

function.◦ A “fast lock” DLL incorporates a Coarse Charge Pump and a

Fine Charge Pump

8

Fine CP is always activated by Up, DownLock Control Circuit decides when to activate Coarse CP.By using only Fine CP when close to lock, jitter is less than using coarse alone.

9

PFD uses a NOR gate on the output of the pre-charged PFD. This reduces the pulse width of UP/DOWN when the loop is locked(using Reset). Output jitter could be reduced.

10

Lock control circuit uses a variable delay element to set the phase error before Coarse CP activates.

11

Result waveform shows that Coarse CP is used at the start, resulting in faster lockingNote the slight overshoot

12

“A 0.03mm2/ 9mW Wide-Range Duty-Cycle Correcting False-Lock-Free DLL with Fully Balanced Charge-Pump for DDR Interface” [4]Problems Addressed◦ Trigger timing controlled by phase shifting of 90° and

270° is not always the best when the clock duty cycle degrades for a single-ended signal transmission.

◦ Metastability of PD inherently causes a two-cycle pattern on the control voltage of VCD which then causes pattern jitter.

Sub-DLL structures generate rising edges at the center of the bitVCDL controls only the falling edge.PD scheme with one cycle pattern (not two)

13

Two complementary DLLs allow clock to lock the center of the bit

14

‘Fully Balanced’ Charge pump causes Vc to trend up to the same voltage until a DN pulse in a stable state. (No pattern jitter)

15

Delay element only delays the falling edge using M6 and M8

16

Discussion of False Lock (one claim in the title)◦ Total VCDL delay equals a multiple of clock cycles◦ Need to be able to prevent or detect this condition◦ Initializing VCDL with minimum delay can prevent

this. [2]

17

CLKi (input) has a duty cycle error. CLKc does not have a duty cycle error and hits the center of the bit

18

“A Low jitter, Fast recoverable, Fully analog DLL using Tracking ADC For High Speed and Low Stand-by power DDR I/O interface” [4]Putting the DLL into standby for reduced power adds a latency cost of at least 200 cycles before returning to active modeVcontrol information is digitized by a tracking ADC. When entering standby, the ADC circuit forces the previous voltage on the delay line.

19

DLL architecture.◦ Two loops used – Reference and Fine Loop◦ Reference loop sends phases to Phase Mux.◦ FSM controls phase MUX, sending matched phase to phase

mixer.◦ Any remaining phase error is corrected in the Fine Loop

20

During operation, the counter digitizes the control voltageOn Power Down, the previous voltage is sent to the loop filter

21

Results show less jitter than the conventional optionArea, active current, standby current and re-lock cycle are not improved (the fast recoverable and low standby power parts of the title were not true)

22

ADLLs can have good supply/ground noise rejection properties, depending on design.The VCDL delay elements play a big role in noise rejection.MPC should retain constant current under VDD noiseGround noise should feed through equally to the differential outputs and be rejected by later differential amplification

[1]

23

Jitter◦ Use dual loops incorporating coarse and fine CPDuty Cycle Errors◦ Duty corrector circuit can be usedCharge pump pull up, pull down imbalances◦ Use a differential CP or ‘Fully Balanced’ CP.Possible charge sharing issues depending on CP designPhase state is not retained in standby unless ADC/DAC circuits are added.Longer lock time compared to DDLLsDead Zone possible if resolution is not highFalse Lock

24

Delay increment can be varied infinitelyNo quantization induced jitter unless ADC/DAC scheme is employedLarge lock rangeSmall layout compared to DDLLsGood supply noise rejectionAbility to include duty-cycle correctionMultiple phases can be generated

25

26

1) CMOS Circuit Design, Layout, and Simulation. Revised Second EditionR. Jacob Baker, John Wiley and Sons, 2008.

2) DRAM Circuit Design. Fundamental and High-Speed TopicsKeeth, Baker, Johnson, Lin. John Wiley and Sons, 2008

3) Fast-Lock Dual Charge Pump Analog DLL using Improved Phase Frequency Detector

Soh Lip-Kai; Sulaiman, M.-S.; Yusoff, Z.; VLSI Design, Automation and Test, 2007. VLSI-DAT 2007. International Symposium on Digital Object Identifier: 10.1109/VDAT.2007.372761Publication Year: 2007 , Page(s): 1 - 5

4) A 0.03mm2/ 9mW Wide-Range Duty-CycleCorrecting False-Lock-Free DLL with Fully Balanced Charge-Pump for DDR Interface

Tokunaga, Y.; Sakiyama, S.; Dosho, S.; Doi, Y.; Hattori, M.; Solid-State Circuits Conference, 2006. ISSCC 2006. Digest of Technical Papers. IEEE International Digital Object Identifier: 10.1109/ISSCC.2006.1696176Publication Year: 2006 , Page(s): 1286 - 1295

5) A low jitter, fast recoverable, fully analog DLL using tracking ADC for high speed and low stand-by power DDR I/O interface

Se Jun Kim; Sang Hoon Hong; Jae-Kyung Wee; JIn Hong Ahn; Jin Young Chung; VLSI Circuits, 2003. Digest of Technical Papers. 2003 Symposium on Publication Year: 2003 , Page(s): 285 - 286

27