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Page 1ITRS Perspective on the Compact Model Developments
The International Technology Roadmap for Semiconductors is sponsored by the five leading chip manufacturing regions in the world: Europe, Japan, Korea, Taiwan, and the United States. The sponsoring organizations are:
European Semiconductor Industry Association (ESIA)
Japan Electronics and Information Technology Industries Association (JEITA)
Korean Semiconductor Industry Association (KSIA)
Taiwan Semiconductor Industry Association (TSIA)
United States Semiconductor Industry Association (SIA)
Page 4ITRS Perspective on the Compact Model Developments
The objective of the ITRS is to ensure cost-effective advancements in the performance of the integrated circuit and the products that employ such devices, thereby continuing the health and success of the semiconductor industry
Set benchmark/guidelines for R&D: SRA, Work Programs of subsidy frameworks
• US event originally (NTRS), since 1998 world wide effort
Sponsored by 5 Semiconductor Industry Associations (Korea, Taiwan, Japan, Europe, US)
System DriversDesignTest & Test EquipmentProcess Integration, Devices, & StructuresRF & A/MS Technologies Emerging Research DevicesEmerging Research MaterialsFront End ProcessesLithography
The working groups, known as TWGs, focus on technologies that are crucial to the design, materials, and manufacture of semiconductors, as well as the factory sciences, process control, metrology, and environmental aspects. The working group members include subject matter experts that represent all sectors of the industry-chip manufacturers, equipment suppliers, and R&D experts.
Page 7ITRS Perspective on the Compact Model Developments
Technology Modeling and Simulation covers the region of the semiconductor modeling world called extended TCAD, and it is one of the few enabling methodologies that can reduce development cycle times and costs. Extended TCAD, within the scope of this document, covers the following topical areas:
1.Front end process modeling, simulation of the physical effects of manufacturing steps used to build transistors up to metallization, but excluding lithography
2.Lithography modeling-modeling of the imaging of the mask by the lithography equipment, the photoresist characteristics and processing
3.Device modeling-hierarchy of physically based models for the operational description of active devices
4.Interconnect and integrated passives modeling-the operational response (mechanical, electromagnetic, and thermal properties) of back-end architectures;
5.Circuit element modeling-compact models for active, passive, and parasitic circuit components, and new circuit elements based on new device structures;
6.Package simulation-electrical, mechanical, and thermal modeling of chip packages
7.Materials modeling-simulation tools that predict the physical properties of materials and, in some cases, the subsequent electrical properties
8.Equipment/feature scale modeling-hierarchy of models that allows the simulation of the local influence of the equipment (except lithography) on each point of the wafer, starting from the equipment geometry and settings
9.TCAD for design, manufacturing and yield-the development of additional models and software to enable the use of TCAD to study the impact of inevitable process variations and dopant fluctuations on IC performance and in turn design parameters, manufacturability and the percentage of ICs that are within specifications
10.Numerical methods-all algorithms needed to implement the models developed in any of the other sections, including grid generators, surface-advancement techniques, (parallel) solvers for systems of (partial) differential equations, and optimization routines
Page 8ITRS Perspective on the Compact Model Developments
Some essentials on ITRS process Industrial perspective: ITRS governed by semiconductor industry;
contributions from suppliers and research Top-level specifications by IRC and ORTC – e.g. on scaling speed 17 ITWGs derive challenges and requirements for focus and cross-cut
areas – Modeling and Simulation on crosscut ITWG New roadmap each odd year – even years only update of tables Limited publication in July, full publication in December
(Winter meeting and internet)
Modeling and Simulation ITWG Currently 35 members – 17 industry, 8 suppliers, 10 research Discussion starts from analysis of requirements of other ITWGs w.r.t
M&S cross-cut texts Challenges, requiremens and chapter texts derived State-of-the-art vs. requirements labelled in colour codes
ITRS Process Essentials
Page 11ITRS Perspective on the Compact Model Developments
Each Chapter also contains tables Difficult challenges Near term and long term requirements Accuracy tables for most relevenant FOMs Color coding system to indicate issues
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Integrated modeling of equipment, materials, feature scale processes and influences on device and circuit performance and reliability, including random and systematic variability• Deposition, etching, CMP, ECP, wafer
polishing/thinning
Nanoscale device simulation capability: Methods, models and algorithms• Models and software• Novel device architectures, channel and
gate stack materials• Fluctuations/variations; reliability• Efficient and robust QM-based simulation
2011 ITRS draft, Jul/Aug 2011
Page 14ITRS Perspective on the Compact Model Developments
Electro-thermal-mechanical modeling for interconnects and packaging• Co-simulation electro-thermal-mechanical• Feature scale to 3D ICs and packages• Novel materials• Interfaces and thin layers• Variability, reliability
Circuit element and system modeling for high frequency (up to 300 GHz) applications• From device/interconnect to dies and