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1
ITRS 2008 Update – April, Konigswinter, Germany
International Technology Roadmap for Semiconductors
– Unchanged 2-year cycle* through 2008/45nm, then 3-year cycle* (2014/22.5; 2020/11.25); ;– Unchanged: Cell Design Factor; Array Efficiency; Bits/Chip– PIDS Flash Survey Team to report status of survey data update and proposals in April meetings.
• Inui-san report:– No Change to number; Floating Gate to Charge from 2010 to 2011; 3D structure from 2013 to 2018– NAND 2 MLC to 4MLC 2010; possible 3 bits/cell – need inputs from additional companies– Recommend Litho Overlay 33%; LWR 12% of CD (Half-Pitch based) [no change to Litho drivers]
• DRAM Model stagger-contacted M1 half-pitch updated to the MPU 2.5-year cycle* through 2010/45nm, then
• DRAM function size, function density, and chip size models have been updated to latest Product 2.5-year cycle scaling rate;
– Only 2007-2009 years affected in 2008 Table Update. – Unchanged 2010-2022
• MPU Model M1 stagger-contact half-pitch unchanged from 2007– 2.5-year cycle* through 2010/45nm, then 3-year cycle* (2016/22.5; 2022/11.25).
• MPU/ASIC Printed Gate Length Updated – Unchanged 3-year cycle through 2018, – then 3.8-year cycle* 2019-2022.
• MPU/ASIC High-Performance Physical Gate Length – 3.8-year cycle* beginning 2007. – Declining printed/etch ratio – need FEP and Litho TWGs to agree on new annual ratios– Slower unchanged On-Chip Frequency trend (8% trend) was set by Design TWG in 2007 ITRS ORTC) -
need updated transistor and design model alignment by PIDS, FEP, and Design.– New drivers will be Ion/W, CV/I – possibly add to ORTC – need PIDS and FEP 2008 Update and
provide ORTC line items.* ITRS Cycle definition = time to .5x linear scaling every two cycle periods]
– Two-year delay 2007 from High Performance; one-year delay 2008-2012; and no delay 2013-2022.
• MPU/ASIC Low Standby Power Physical Gate Length [add to ORTC 1a,b]– No Change 2007, 2008; two-year delay 2009-2011 from High Performance; one-year delay in
2012; and no delay 2013-2022.• Also, one decimal place rounding was added to all ORTC 1a,b from 2016-2022
• New 2008 “Moore’s Law and More” Working Groups and Definitions Work : – “More Moore” (“Moore’s Law;” typically digital computing) Functional and Performance scaling is
enabled by both “Geometrical” and also “Equivalent” scaling technologies; Design “Equivalent Scaling” to be added in 2008
– More than Moore “Functional diversification” text will be impacted (typically non-digital sensing, interacting) system board-level migration/miniaturization is enabled by system-in-package and system-on-chip
– “Beyond CMOS” definition and timing range will be added, focused on the Logic Switch transition at “Ultimately Scaled CMOS”
• The average of the industry product “Moore’s Law” (2x functions/chip per 2 years) rate forecast to continue throughout the latest 2007-2022 ITRS timeframe
• Total MOS Capacity (SICAS) growing at ~16% CAGR (SICAS); new “<80nm” data split out; and 300mm Capacity Demand has ramped to 33% of Total MOS
• Industry Technology Capacity Demand (SICAS) – [3Q,4Q07 published status] continues on a on 2-year cycle* rate at the leading edge.
– Unchanged 2-year cycle* through 2008/45nm, then 3-year cycle* (2014/22.5; 2020/11.25); ;– Unchanged: Cell Design Factor; Array Efficiency; Bits/Chip– PIDS Flash Survey Team to report status of survey data update and proposals in April meetings.
• Inui-san report:– No Change to number; Floating Gate to Charge from 2010 to 2011; 3D structure from 2013 to 2018– NAND 2 MLC to 4MLC 2010; possible 3 bits/cell – need inputs from additional companies– Recommend Litho Overlay 33%; LWR 12% of CD (Half-Pitch based) [no change to Litho drivers]
• DRAM Model stagger-contacted M1 half-pitch updated to the MPU 2.5-year cycle* through 2010/45nm, then
• DRAM function size, function density, and chip size models have been updated to latest Product 2.5-year cycle scaling rate;
– Only 2007-2009 years affected in 2008 Table Update. – Unchanged 2010-2022
• MPU Model M1 stagger-contact half-pitch unchanged from 2007– 2.5-year cycle* through 2010/45nm, then 3-year cycle* (2016/22.5; 2022/11.25).
• MPU/ASIC Printed Gate Length Updated – Unchanged 3-year cycle through 2018, – then 3.8-year cycle* 2019-2022.
• MPU/ASIC High-Performance Physical Gate Length – 3.8-year cycle* beginning 2007. – Declining printed/etch ratio – need FEP and Litho TWGs to agree on new annual ratios– Slower unchanged On-Chip Frequency trend (8% trend) was set by Design TWG in 2007 ITRS ORTC) -
need updated transistor and design model alignment by PIDS, FEP, and Design.– New drivers will be Ion/W, CV/I – possibly add to ORTC – need PIDS and FEP 2008 Update and
provide ORTC line items.* ITRS Cycle definition = time to .5x linear scaling every two cycle periods]
– Two-year delay 2007 from High Performance; one-year delay 2008-2012; and no delay 2013-2022.
• MPU/ASIC Low Standby Power Physical Gate Length [add to ORTC 1a,b]– No Change 2007, 2008; two-year delay 2009-2011 from High Performance; one-year delay in
2012; and no delay 2013-2022.• Also, one decimal place rounding was added to all ORTC 1a,b from 2016-2022
• New 2008 “Moore’s Law and More” Working Groups and Definitions Work : – “More Moore” (“Moore’s Law;” typically digital computing) Functional and Performance scaling is
enabled by both “Geometrical” and also “Equivalent” scaling technologies; Design “Equivalent Scaling” to be added in 2008
– More than Moore “Functional diversification” text will be impacted (typically non-digital sensing, interacting) system board-level migration/miniaturization is enabled by system-in-package and system-on-chip
– “Beyond CMOS” definition and timing range will be added, focused on the Logic Switch transition at “Ultimately Scaled CMOS”
• The average of the industry product “Moore’s Law” (2x functions/chip per 2 years) rate forecast to continue throughout the latest 2007-2022 ITRS timeframe
• Total MOS Capacity (SICAS) growing at ~16% CAGR (SICAS); new “<80nm” data split out; and 300mm Capacity Demand has ramped to 33% of Total MOS
• Industry Technology Capacity Demand (SICAS) – [3Q,4Q07 published status] continues on a on 2-year cycle* rate at the leading edge.
13
ITRS 2008 Update – April, Konigswinter, Germany
ORTC Pre-Summary – 2008 Update (cont.)• More than Moore [discussion leader – Mart Graef also see
Backup for additional MtM presentation information]– Objective:
Define and quantify value-adding parameters for functional diversification
• Identify/elaborate Technical Parameters• Added Value to the target application• Usual ITRS goals: Grand Challenges, Potential Solutions, narrowing
over time• Pitfall(Design TWG comment): line item doesn’t “fit”• May need to “tweak” to “fit” the MtM taxonomy• Key parameters for MtM examples in marketplace
– Involve IRC/ITWGs• A&P, Design, RF/AMS, Test, Interconnect, but open to other TWGs• Key Categories to address: Sensors, Actuators (MEMS, Optical)
– Key Issue differentiating “MtM”: Integration– Next Meeting will be called by Mart Graef
• TWGs notify Mart of their participant at the April ITRS meeting
More than Moore Study Group 4/3/08
14
ITRS 2008 Update – April, Konigswinter, Germany
Design TWG Proposed “More Moore” and “MtM” Text, 3 apr 2008 Plenary v2a[discussion leader – Andrew Kahng]• 1 = More Moore
– 1a = geometric scaling– 1b = equivalent scaling– 1c = Design equivalent scaling– NEED: quantifiable, specific Design Technologies that deal with More Moore
– “Design equivalent scaling occurs in conjunction with Equivalent Scaling and continued Geometric Scaling, and refers to design technologies that enable high performance, low power, high reliability, low cost, and high design productivity.”
– “Examples (not exhaustive) are: Design for variability; low power design (sleep modes, hibernation, clock gating, multi-VDD, ...); and homogeneous and heterogeneous multicore SOC architectures.”
• 2 = More than Moore– NEED: Design technologies to enable functional diversification
– “Design technologies enable new functionality that takes advantage of More than Moore technologies.”
– “Examples (not exhaustive) are: Heterogeneous system partitioning and simulation; software; analog and mixed signal design technologies for sensors and actuators; and new methods and tools for co-design and co-simulation of SIP, MEMS, and biotechnology.”
– 3.8-year cycle* beginning 2007. – Declining printed/etch ratio – need FEP and Litho TWGs to agree on new annual ratios– Slower unchanged On-Chip Frequency trend (8% trend) was set by Design TWG in 2007 ITRS
ORTC) - need updated transistor and design model alignment by PIDS, FEP, and Design.– New drivers will be Ion/W, CV/I – possibly add to ORTC – need PIDS and FEP 2008 Update
and provide ORTC line items.– Thomas Scotnicki review of Paper and VLSI presentation (see Scotnicki files)
• Discrepancy between measured vs ITRS model• Andrew Kahng review – what interconnect capacitance assumed (~zero in ring oscillators)• Proposal for 3 changes to
– 17% not needed, 8% is enough (due to increased 1 core to 2 core architecture performance)– Variability not taken into account (no manufacturing flexibility) PIDS recommendation
» MASTAR Random Generator– Variability vs Device Structure– Not a model problem/limitation – need decision
» Not supporting 1/Ion; Want CV/I
– Paolo Gargini Review of “Equivalent Scaling Knobs” for Performance/Power tradeoffs• Smaller changes on 5 “knobs” (including Strain, Hik/MetGate, etc) vs historical 2 knobs (Oxide Thickness,
Gate Length)• More complex modeling options using Mobility, Dielectric Constant, Voltage “indicators”
– “equivalent channel length” possible approach• Andrew Kahng – please advise how to share the investment in manufacturing solutions (“knobs”)?
• Beyond CMOS [discussion leader – Jim Hutchby]• “new switch” (asterick “information processing” including interconnect and memory);• Logic switch -> SIA/NRI “invent the new switch”• Graphics need a new color• ERD/ERM (Jim Hutchby, Mike Garner); PIDS (Kwok Ng, Thomas Skotnicki); Design (Andrew Kahng; Juan-
Antonio Carballo)
More Moore Study Group 4/3/08
Beyond CMOS Study Group 4/3/08
16
ITRS 2008 Update – April, Konigswinter, Germany
Backup
- On-chip Frequency Update- Bohr “Tutorial” URL- More than Moore Study Group Kickoff presentation- SICAS 3Q/4Q07 Update
Moore’s Law & MoreMore than Moore: Diversification
Mo
re M
oo
re:
Min
iatu
riza
tio
nM
ore
Mo
ore
: M
inia
turi
zati
on
Combining SoC and SiP: Higher Value SystemsBas
eli
ne
CM
OS
: C
PU
, M
emo
ry,
Lo
gic
BiochipsSensors
ActuatorsHV
PowerAnalog/RF Passives
130nm
90nm
65nm
45nm
32nm
22nm...V
130nm
90nm
65nm
45nm
32nm
22nm...V
Information Processing
Digital contentSystem-on-chip
(SoC)
Interacting with people and environment
Non-digital contentSystem-in-package
(SiP)
Beyond CMOS
Sca
lin
g (
Mo
re M
oo
re)
Functional Diversification (More than Moore)
Continuing SoC and SIP: Higher Value Systems
MtM StudyGroup 4/3/08
21
ITRS 2008 Update – April, Konigswinter, Germany
2007 ITRS “Moore’s Law and More” Definition Graphic Proposal
Computing &Data Storage
Heterogeneous IntegrationSystem on Chip (SOC) and System In Package (SIP)
Sense, interact, Empower
BaselineCMOS Memory RF HV
PowerPassives Sensors,
ActuatorsBio-chips,Fluidics
“More Moore”
“More than Moore”
Source: ITRS, European Nanoelectronics Initiative Advisory Council (ENIAC)
MtM StudyGroup 4/3/08
22
ITRS 2008 Update – April, Konigswinter, Germany
• “More Moore”: ScalingContinued shrinking of physical feature sizes of the digital functionalities (logic and memory storage) in order to improve density (cost per function reduction) and performance (speed, power).
• “More than Moore”: Functional DiversificationIncorporation into devices of functionalities that do not necessarily scale according to "Moore's Law“, but provide additional value in different ways. The "More-than-Moore" approach allows for the non-digital functionalities to migrate from the system board-level into the package (SiP) or onto the chip (SoC).
• The Challenge: Integration of MM with MtMCreation of intelligent compact systems.
“More Moore” and “More than Moore”MtM Study
Group 4/3/08
23
ITRS 2008 Update – April, Konigswinter, Germany
Following Moore’s Law is one approach:
Monolithic CMOS logic System-on-Chip
PowerSensor
Actuator
Storage
Processor
Radio
Advantage:-Smallest footprint
Disadvantage:-Limited functionality
More Moore
MtM Study Group 4/3/08
24
ITRS 2008 Update – April, Konigswinter, Germany
Adding More-than-Moore is another:System-on-Chip and System-in-Package
PowerSensor
Actuator
Storage
Processor
Radio
Advantage:-Full functionality
Disadvantage:-Complex supply chain
More than Moore
More Moore
MtM Study Group 4/3/08
25
ITRS 2008 Update – April, Konigswinter, Germany
Proposal for MtM Study Group• Objective:
Define and quantify value-adding parameters for functional diversification– Identify/elaborate Technical Parameters– Added Value to the target application– Usual ITRS goals: Grand Challenges, Potential Solutions,
narrowing over time– Pitfall(Design): line item doesn’t “fit”
• May need to “tweak” to “fit” the MtM taxonomy– Key parameters for MtM examples in marketplace
• Involve IRC/ITWGs– A&P, Design, RF/AMS, Test, Interconnect, but open to other TWGs– Key Categories to address: Sensors, Actuators (MEMS, Optical)
• Key Issue differentiating “MtM”: Integration• Next Meeting will be called by Mart Graef
– TWGs notify Mart of their participant at the April ITRS meeting
MtM Study Group 4/3/08
26
ITRS 2008 Update – April, Konigswinter, Germany
Design TWG Proposed MTM Text, 3 apr 2008 Plenary v2a• 1 = More Moore
– 1a = geometric scaling– 1b = equivalent scaling– 1c = Design equivalent scaling– NEED: quantifiable, specific Design Technologies that deal with More Moore
– “Design equivalent scaling occurs in conjunction with Equivalent Scaling and continued Geometric Scaling, and refers to design technologies that enable high performance, low power, high reliability, low cost, and high design productivity.”
– “Examples (not exhaustive) are: Design for variability; low power design (sleep modes, hibernation, clock gating, multi-VDD, ...); and homogeneous and heterogeneous multicore SOC architectures.”
• 2 = More than Moore– NEED: Design technologies to enable functional diversification
– “Design technologies enable new functionality that takes advantage of More than Moore technologies.”
– “Examples (not exhaustive) are: Heterogeneous system partitioning and simulation; software; analog and mixed signal design technologies for sensors and actuators; and new methods and tools for co-design and co-simulation of SIP, MEMS, and biotechnology.”
More Moore Study Group 4/3/08
27
ITRS 2008 Update – April, Konigswinter, Germany
SICAS Update (www.sia-online.org )MOS Capacity by Technology
0.0
200.0
400.0
600.0
800.0
1000.0
1200.0
1400.0
1600.0
1800.0
2000.0
1Q05
2Q05
3Q05
4Q05
1Q06
2Q06
3Q06
4Q06
1Q07
2Q07
3Q07
4Q07
Year
(000
's w
spw
)
0.7µm
<0.7µm to 0.4µm
<0.4µm to 0.3µm
<0.3µm to 0.2µm
<0.2µm to 0.16µm
<0.16µm to 0.12µm
<0.12µm
<0.12µm to 0.08µm
<0.08µm
15.5% CAGR
59.7% CAGR
Source: SICAS www.sia-online.org, ca
28
ITRS 2008 Update – April, Konigswinter, Germany
SICAS Update (www.sia-online.org )MOS Capacity by Dimensions
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
1Q05
2Q05
3Q05
4Q05
1Q06
2Q06
3Q06
4Q06
1Q07
2Q07
3Q07
4Q07
WS
pW
x 1
000
0.7µm
<0.7µm to0.4µm
<0.4µm to0.3µm
<0.3µm to0.2µm
<0.2µm to0.16µm
<0.16µm to0.12µm
<0.12µm
<0.12µm to0.08µm
<0.08µm
["65nm" ITRS Technology CycleIntro Year: 2007]
[2-yr SICAS Data Technology CycleIntro Year: 2006]