Introduction to Low Power Rf-ic Design Rfdr.

INTRODUCTION TO LOW INTRODUCTION TO LOW POWER RFPOWER RF--IC DESIGNIC DESIGN

Dr. T K BhattacharyyaDr. T K Bhattacharyya

E & ECE Dept.Advanced VLSI Design Lab.

IIT Kharagpur..

PART – IBasics of RF Design

WHAT IS RF?Frequency spectrum:

• Why Lumped parameters models failed ……………….

• Kirchoff's to Maxwell’s…….

• Failure of two port circuit parameter (Z, Y,ABCD) ……..

• Scattering parameter( S-parameter) on the basis of Maxwell equation comes in …

Application area of the RFApplication area of the RF--IC designerIC designerWireless communication

Radar

Navigation

Remote sensing

RF identification

Automobile and Highways

Sensors:

Medical

Radio- astronomy and space exploration

Beauty of RF_IC Design: Link between Microwave Engineer and Design Engineer

Maxwell equation’s are

kirchoff’s law Total voltage around a loop is zero( KVL)

No net current build up at any node(KCL)

•If ε & μ =0, (c α ) i.e infinitely fast wave propagation of wave gives KVL and KCL

•As the physical dimension of circuit element & sub-circuit in a IC chip is very less (even less than 1/10th of λ [ 30 cm in air at 1 GHz] ) , so finiteness of the speed of light is not noticeable inside chip, so a full transmission line ( Microwave) for on-chip design and analysis is generally unnecessary. Kirchoff’s law is well suited for on-chip design•But for interfacing the RF signals in / out of the chip, we need connectors, boards, cables etc. Where transmission-line effects cannot be ignored

( Analog [Low frequency<100MHz] ) ( RF/MW[ High frequency>100MHz] )

Conductor

Capacitor

Resistor

Inductor

Simple wire

Microstrip line

Comparison of Analog and RF/MW

Ceramic

1. On Discrete PCB component

Carbon Thin Film SMD comp.

Thin Film SMD comp.

Wire Wound

Thin Film SMD comp.

( Analog [Low frequency<100MHz] ) ( RF/MW [High frequency>100MHz] )

Comparison of Analog and RF/MW1. On Performance Based

A. Small signal AC equivalent circuit analysis

B. Linearity

C. Stability

D. Noise (on few cases)

A. Small signal AC equivalent circuit analysis with parasitic i.e. Good circuit Modeling

B. Matching

E. Linearity

D. Stability

C. Noise

F. Sensitivity

G. Dynamic range

Comparison of MMIC/RFIC

Parameter MMIC( Discrete) RFIC( integrated)Development Cost Moderate Very high

Modifications Relatively easy & inexpensive Expensive ,generally one or more new mask

BOM cost Low Depends on volume , die sized and process used

Mixing Technologies Optimum device technology can be used through out ( combined GaAs, BJT, MOS)

Limited scope

Parts Count High Low to very low

Size Small to medium Smallest

Weight Light Lightest

Cost of Using Additional transistor

Moderate Low

Matched transistor Difficult to implement Very good , used extensively

Basic of RFIC design

• Analog/RF design octagon

• Disciplines required in RF design

1. Phase shift of the signal is significant over the extent of the component because it’s size is comparable with the wavelength.

2. The reactance of the circuit must be accounted for, particularly those associated with the parasitic of the active devices.

3. Circuit losses causes degradation of Q, reduction of frequency selectivity and noise performance.

4. Noise especially arising from the circuit can be significant and it’s effect needs to be modeled.

5. Electromagnetic radiation capacitive coupling and substrate coupling significantly alter the performance of the circuit.

6. Reflection issues, because circuit size is of the order of a wavelength.

7. Circuit design should take care to ensure reflections do not cause any loss of gain, power, or failure of components.

8. Nonlinearity which causes distortion and unwanted frequency components is undesirable, but it may become essential part of the circuit operation, as in mixing or local oscillators.

RF CIRCUITS AND SYSTEMS RF CIRCUITS AND SYSTEMS -- DESIGN ISSUESDESIGN ISSUES

Noise Noise

• Thermal Noise-Brownian motion of thermally agitated charge carriers - generated in every physical resistor

- pure reactive components generate no thermal noise

Thermal Noise in MOSFETTh most significant source of noise Channel Noise:

In2 = 4kTγgm

• γ ~1 at a zero VDS for long channel device, 2/3 at saturation, 2-3 for short channel transistor

Significance :The significance of noise performance of a circuit is the limitation it places on thesmallest input signals(MDS) the circuit can handle before the noise degrades the quality of output signal. • this noise is negligible at low frequency, but can dominate at RF

• δ ~ 4/3 in long device

- both drain and gate noise share a common origin and they are correlated

Shot Noise-Gaussian white process associated with the transfer of charge across an energy barrier

- due to DC current through p-n junction, gate channel

Flicker noise in MOSFET-random trapping of charge at oxide interface- modeled as a voltage source in series with gate

Gate induced noise

Thermal agitation of channel charge cause fluctuation of channel potential. This couples capacitively with gate terminal, leading to gate noise

Noise figureNoise figure

Noise figure (F) specifies the noise performance of a circuit or device

• Limitation : Noise figure is definable only when input source is resistive ------important parameter on communication system as the source impedance in this system is often resistive

Noise factor (NF) = Noise Figure (F)= 10log10 NF-Noise figure measures the SNR degradation as a signal pass through a system• if a system has no noise the NF=1, F = 0dB

• if input signal contains no noise then SNRin =αand NF = α ( even though the system has finite noise ) : is it really possible!!

•Definition :

•In most cases condition for power optimum and noise optimum resistance do not coincide ( challenge !!!)

Examples :

- NF is minimized by maximizing Rp

- Maximum power transform possible when Rs =Rp

• So condition for minimum noise figure does not coincide with maximum power transfer

Noise figureNoise figure (cont..)

Noise figureNoise figure (cont..)Noise figure of cascaded stages ..

For two stage case it can be shown

For m- stages

• NF of each stages is calculated with respect to the output impedance of previous stages

• The noise is contributed by each stage decreases as the gain preceding the stages increase

•That’s why the first stage of any system should have higher gain with low noise figure ( PRIME CRITERION FOR LOW NOISE AMPLIFIER (LNA) DESIGN OF A RECEIVER)

Noise figure of Lossy circuit ..•Passive circuits attenuates signal, contribute noise

=>Noise factor= LossCascade passive Filter &LNA

Noise figureNoise figure (cont..)

s2

nR sV 4kTR f= Δ2

n1 d0i 4kT g f= γ Δ

D2

n R

D

4 k Ti fR

= Δ

Output noise current due to source resistance2 2 2

nsm m sg V g .4kTR f= = Δ

Total Output noise current2

m s d0D

4kTg .4kTR f 4kT g f fR

= Δ + γ Δ + Δ

d02 2

m s m s D

g 1NF 1g R g R Rγ

= + +

gs nss

2 2d0

2 2m s m s D

sLV VR sL

{(R / L) 1} g 1 (R / L)NF 1g R g R R

=+

ω + γ + ω= + +

Examples LINEARITY ISSUES

Linearity Issues Cont… Linearity Issues Cont…

Linearity Issues Cont… Method for Estimating Linearity Parameter from Device Parameter

Already we get for a nonlinear system

MOSFET current :1 dB compression point

IIP3 value

g(Vo), g(V+), g(V-) are the Transconductance value, Where V0 is the dc-bias voltage, V+ is slightly higher and V- is slightly lower

Stability Analysis

Basic criteria:For good stable has no positive feedback loop, in general the all pole must in right half s-plane.

•As real circuit are complex, proper analysis of transfer function is required and compensation technique is used to obtain good stability (such as OPAMP)

m 0o u t

in

sg r (1 )V (s ) zsV (s ) 1p

− −=

+ 0 gd

1pr C

= m

gd

gzC

=,,

Cgd gives pole in right half plane, if Cgd 0 , then get good stability

CS -stage

CG -stageCds gives positive feed back, so stability reduce

• The backward-transmission(S12) is required to be small for good stability

Sensitivity

Dynamic RangeHigh Frequency Device modeling

Silicon Technologies

BiCMOS MOSBipolar

Junction Isolated

BJTs

DielectricIsolated

PMOS NMOS

CMOS

Standard Digital CMOS is hardly the ideal medium for RF ICs, because of :Lossy Silicon substrateLarge source/drain parasiticsHigh device noise and

poor 1/f noise performanceSeries gate resistance

But,Device scaling …faster CMOS fT (and fmax) ….range of 60GHz

doubles roughly every 3 years.CMOS is cost effectiveBoth digital & analog block can be

designed on same substrateHigh linearity; Low distortionLow power consumptionOn-chip realization of passive inductors

and capacitors

CMOS BJT

Symmetric behavior.Better linearity

(Higher signal swing).Higher fT at sub-

micron feature size.Better scaling

properties.Low power (no gate

DC current).

Higher gm for same bias.

High fT.

Low thermal and 1/f noise, but input current noise.

Lower DC offset .No body effect.Lower overdrive

(Low VCE sat).

WHY CMOS FOR RF-IC High Frequency Device modeling (contd.)Visualization of Process Flow

Protective Overcoat

CVD Oxide

p-epi

p-substrate

n+ n+

Gate oxidepolyFOX

contact

Metal-1

via

Metal-2

R

RRpoly Cgs Cgd Cds

Csub

•To calculate magnetic coupling between two adjacent metal line, interlayer capacitance , EMI between subcircuits & on-chip passive component (such as inductor and MIM capacitor) , the Maxwell EM equation is required ( Challenging issue !!!)

RF CMOS MODELLINGRF CMOS MODELLING

Maximum unit power gain Maximum unit power gain frequencyfrequency

Maximum CutMaximum Cut--off frequencyoff frequency

““Standard” (digital oriented) MOS models do not allow for RFStandard” (digital oriented) MOS models do not allow for RF

In RF, Cgs ( whose effect negligible in low frequency analog) affects the matching with successive blocks . Frequency dependence of Transconductance(gm )

c.f Lee P-68,70 gc oxC C= cb siC C=sbo

jsb1/ 2sb

0

CC V(1 )=

+ψ

d b oj d B

1 / 2d b

0

CC V(1 )=

+ψ

Long channel effect

n ox gs t21

Id 2WC (V V )L

= μ −

g s t3 nf T 22 2 L

( V V )μ=

π−

Sort channel effectn

d

c

V1

μ ε=

ε+ε

d vd y

ε =

d I dI Q WV (y)=,

d I nc

1 dv dvI (1 . ) W Q ( y)dy dy

+ = με

n o xd g s t

g s t

c

2C WI ( V V )V V L2 ( 1 )L

μ= −

−+

εn o x

g s tg s t

2C W ( V V )2[1 ( V V )] L

μ= −

+ θ −

g s t

cm o x s c l

g s t

c

2 ( V V )1 1

Lg W C V

2 ( V V )1

L

−+ −

ε=

−+

ε

scl n cV = μ ε

,

• fT independent of overdrive voltagegs t(V V )−

• fT inversely proportional to L

RF CMOS MODELLINGRF CMOS MODELLINGOn-Chip inductor realization

At RF frequencies, matching network consists of number of inductors. Therefore on-chip realization of inductors is important for RF IC design.

Three kind of inductors :ACTIVE INDUCTORACTIVE INDUCTOR →→ More noisy, highly non-linear, High Q with large L

value possible , frequency dependent, higher power consumption.

BOND WIRE INDUCTORBOND WIRE INDUCTOR → → Depends on curvature, High Q(~60), Typical value : 1nH/mm, series resistance : 0.2 Ω/mm(1mm φ).

ONON-- CHIP SPIRAL INDUCTORCHIP SPIRAL INDUCTOR →→ Less Q (3-6), In CMOS process maximum 10nH value possible with reasonable Q values, very small DC power consumption….At very low (<0.5nH) L value → interconnect parasitics dominate… At high (>10nH) L values → Large area, Higher losses.

ONON-- CHIP PASSIVE COMPONENTCHIP PASSIVE COMPONENT

ICs.ICs.Key Issues :Key Issues :

Z(s) = Z(s) =

Z(s) = s L +RZ(s) = s L +R

Concerned propertiesConcerned propertiesBandwidth, Quality Factor (Q) and Noise Factor. Bandwidth, Quality Factor (Q) and Noise Factor.

Advantages over Spiral Inductors : Advantages over Spiral Inductors :

Much Less Chip AreaMuch Less Chip AreaHigh Q factor( about 5 times)High Q factor( about 5 times)Less parasitic effectLess parasitic effectBetter modeling and characterizationBetter modeling and characterization ..

Disadvantage: Disadvantage: Bandwidth is Low , Higher Noise.Bandwidth is Low , Higher Noise.

Active Inductor DesignActive Inductor Design

==

Coplanar Spiral InductorsCoplanar Spiral Inductors

Most Popular structure → Coplanar Spiral InductorShapes Used → Rectangular, Circular, PolygonDisadvantages :Lossy → Metallic ohmic loss, Substrate losses, Eddy current lossPoor Quality factor (Typically 3-6)Takes large areaNoisy → Thermal noise of various resistors (Metal, Eddy current, Substrate)

Coplanar Spiral Inductor DesignCoplanar Spiral Inductor Design

Edge to Edge distance d (Typically 100-200 um)Metal strip width w (Typically 10-15 um)No of turns (Typically 3-5)Strip Separation t (Typically 1-3 um)

Design Parameters:

Technology Constraints:No of Metal Layers (Typically 3-5)

Metal Layer Thickness (or Metal Sheet Resistance)

Substrate Resistivity

Design Guide-Lines:

Hallow structure gives better Q

Top metal layer used (Small substrate Cap, Low Metal Resistivity)

Pattern Ground Shield (reduces Eddy Current Loss)

Self Resonance Frequency ( ω02 α [n*w*(d-w-t(n-1)]-1)> 5 *

Operating Frequency

Multi Layer InductorsMulti Layer Inductors2 or more layers combined in seriesMore electromagnetic coupling between two layers → higher L-valueAsymmetrical structureModeling difficult (3-D effects)

Large Dia → High surface area → Low Resistivity → Large Q.No Conductive Surface beneath → No Substrate/Eddy current losses.Typical Inductance : 1nH/mm.No standard technology for Fab.Difficult Modeling.Coupled Bond Wires give higher L value.

Bond Wire InductorsBond Wire Inductors

Pad & Bond WirePad & Bond Wire

Typical Bond Pad capacitance is of the order of 300 – 600 fF.

Shielding reduces the effect of loss( due to Rsub).

PART – IITransceiver Design

Basic Transceiver ArchitectureBasic Transceiver Architecture

T/R Switch

LNADownConverter

Up Converter

PA

Frequency Synthesizer

IF or baseband

IF or baseband

Simplified Diagram

Complete Block Diagram

Performance Measures

• Sensitivity• Selectivity• Noise• Dynamic Range• Linearity• Power consumption

Transmitter Receiver

• Power efficiency• Modulation accuracy• Carrier leakage• Power consumption

Standards

GSM Bluetooth ZigbeeTransmission

schemeTDMA & FDD FHSS(Frequency

Hopping Spread Sprectrum)

DSSS(Direct Sequence Spread Spectrum)

Frequency Band Tx : 890 – 915 MHzRx : 935 – 960 MHz

2.4 GHz 2.4 GHz, 915 MHz, 868 MHz

Modulation scheme GMSK(GaussianMinimum Shift Keying)

GFSK(GaussianFrequency Shift Keying)

QPSK(Quadrature Phase Shift Keying) or BPSK

depends on the freq band

Sensitivity -102 dBm -70 dBm for 0.1% BER -85 dBm (2.4GHz) or -92 dBm (915/868 MHz) for packet error rate < 0.1%

Transmitted power 0.8 – 20 W Maximum 100 mW, 2.5mW or 1 mW

depending on class

Minimum capability 0.5mW, Maximum as

allowed by local regulations

Data Rate 270 KBPS 1 MBPS 250 KBPS, 40 KBPS or 20 KBPS ( depending on

frequency band)

Transmitter Architecture

Direct Conversion Transmitter

LO Pulling by PA

Modulation and upconversionare done in the same circuit

Simplicity lends it to high degree of integration

Important drawback: Output of the PA tends to shift the LO output as its spectrum lies around LO frequency.

Transmitter Architecture (contd.)

Direct Conversion Tx with offset LO

Two step Transmitter

LO pulling is avoided by having the PA output spectrum sufficiently away from that of LO

Quadrature modulation of I and Q signals are done at a lower frequency and thereafter the upconversion occur at higher frequency.

PA spectrum is away from both the LO frequencies

Wide-band Transmitter Architecture

Ultra Wide-band( UWB) Transmitter

Single Band

Another option for multi-band implementation is to use LNA tuned at two different frequencies

Multi-Band

Receiver Architecture on Application Basis

UWB

Architecture classification based on principle of downconversion

Heterodyne Architecture

Heterodyne architecture has been the dominant choice for many years.

The received signal is first downconverted to an Intermediate Frequency (IF).

Received signal is bandpass filtered and downconverted at progressively lower frequencies to achieve high selectivity.

Stringent requirements on the filters force the use of large passive components and make it difficult to integrate on a chip.

Problem of Image

Problem of Image

Use of image reject filter

Images can be several times larger than the wanted signal mandating an Image Rejection Ratio (IRR) of at least -70 dB.

Very high Q requirement is usually placed on the Image Reject Filter

High IF High IRR or Facilitates Image Rejection

Low IF Facilitates Channel Selection

Optimum Value of IF needs to be chosen

Homodyne Receiver

Simple Homodyne or Direct Conversion Receiver

Quadrature Downconversion in DCR

Simplicity lends it to efficient on-chip implementation

Problem of image is not there.

To be more precise “images” in this case comes from the same channel and hence are of comparable magnitude as of the desired signal. Hence IRR of around -40 dB is typically sufficient.

LO Leakage from LO to RF port and subsequent self mixing produces DC Offset

Offset voltages near DC corrupts the signal and more importantly may saturate the following stages

LO Leakage also generates spurious radiations

Flicker Noise becomes more prominent at low frequencies.

Even-order distortion

Demerits of DCR

LO Leakage to input

Even order Distortion

Image Reject Architectures

Image Rejection using Single Sideband Mixing

Weaver Architecture

Special Image Reject architectures were developed to relax the required performance of the filters

Image Rejection depends on the matching between the mixers and the LO I and Q signals.

For typical mismatch IRR is limited to -40 dB.

Low IF architecture

Combines the advantages of the heterodyne and homodyne architectures.

Image rejection is deferred till the IF stage and is done by a filter with asymmetric frequency response.

Signal and the image are downconverted at positive and negative frequencies respectively or vice versa.

The image is filtered out by the polyphase filter.

Low IF Architecture

Image Rejection using Polyphase Filter

Initial Guess

Block Level Specs

System Level Specs

Requirement Satisfied?

Required System Level Specs

no

yes

Final Block Level Specs

Modify

From system level to component level specifications

From System level to Component level specifications (contd.)

Sensitivity of the Receiver

Block Diagram of the Receiver System

Noise Figure of the Front-end

Given

•SNRout Required = 14 dB

•Sensitivity Required( Pin,min) = -90 dBm

•Bandwidth = 2 MHz

The required Noise Figure of the receiver front-end is calculated from the sensitivity eqn.

-90 = -174+ 10 log10(2x103) + NF + 14

NF = 7 dB

Gain, NF and IIP3 of cascaded stages

Total Noise Factor

Total IIP3

p1 p2 pkA A AAp = × × ×L

32 k1

p1 p1 p2 p1 p2 p(k-1)

NF 1NF 1 NF 1NF=NF .....A A A A A ...A

−− −+ + + +

p1 p1 p2 p1 p2 p(k-1)

3 3,1 3,2 3,3 3,k

A A A A A ...A1 1= .....IIP IIP IIP IIP IIP

+ + + +

Total Gain

Where NFi, Api and IIP3,i are respectively Noise Factor , Available Power Gain and input 3rd order intercept point of the i-th stage

Example- Gain and NF calculation

ON-CHIP GHz CMOS LOW NOISE AMPLIFIER

WHY ON-CHIP ?

4 P-words :Price : Mass volume production reduces pricePackage : Integration reduces No of total pin countPerformance : Improves except few cases Power : On-chip components dissipate lesser power

Challenges :Poor quality of passive components (inductor etc.)Device modeling at RF frequenciesRealizing good analog circuits in digital technologyMeeting stringent performance requirements in digital environment. Substrate noise coupling is more critical in mixed signal

LOW NOISE AMPLIFIERS

Characteristics :First gain stage in receiver

Received signal very weak (~μV)

Gains usually moderate (10-20 dB typical)

Noise Figure (NF) should be as low as possible (<3 dB typical)

Linearity is also an issue

Reverse Isolation should be high

Noise Figure: 2~3dB

Gain: 15~20dB

IIP3: ~ -10dBm

Input/output Impedance: 50 Ohm

Input/output Return Loss: -15dB

Reverse Isolation: >30dB

Stability Factor >1

Design consideration :

Different structure of CMOS LNA

All structures are narrow-band

Common source LNACommon source LNA ac equivalent modelac equivalent model

Capacitive input impedance.Lg cancels Capacitive term.A parallel RS (50 Ω) is added to match input source R50.

To reduce the effect of Zout (img)on tuning circuit, C value should be large compared to Zout

Corresponding circuit

Disadvantage of this circuit :

Due to Rextra , the power divide by 2.

NF ~1+ (γ/α) * Rextra/R50 , γ & α (=gm/gdo) are device parameter. NF~3-4 dB.

Due to Cgd reverse isolation(S11) Bad.

Cgd affects stability due to presence of zero in transfer function (Vout/Vin)

Most popular LNA topologyRemedy ………

“ Cascode source degeneration common source”Equation for choosing Input matching network ComponentEquation for choosing Input matching network Component

Choosing of device (W/L) & Vgs : determine gm & Cgs value , then Ls and Lg can be found.Effect of channel resistance & gate resistance : modify above equation (Fingering is done in layout to reduce this value ).The parasitic of inductor must be considered for calculating practical component values.

Equation for choosing output matching network componentEquation for choosing output matching network componentGate of M2 is ac ground, so Gate of M2 is ac ground, so output cap due to Zout is Coutput cap due to Zout is Cgd2gd2onlyonly….…. C value lesser.C value lesser.As impedance looking to source As impedance looking to source of M2 is 1/gof M2 is 1/gm2 m2 as a result Miller as a result Miller capcap effect gets reduced.effect gets reduced.

Good L, Q is 2 Good L, Q is 2 ––3, then get Rd, 3, then get Rd, From Rd findFrom Rd find--out equivalent Ld out equivalent Ld

by by ASITIC with maximum ASITIC with maximum possible Q.possible Q. then calculate C then calculate C from from ωω00, check whether C is , check whether C is much larger(~10 times of much larger(~10 times of CgdCgd))

Bias &Device sizeNoise and power are two important parameter to characterize device size and bias. Two-port noise model

Noise-freeTwo-Port

I2

V2

vn

inYSiS

Where Gs, Gc, Bc, Rn →→ noise parameters

The channel noise & gate induced noise id2 & ig2 are main noise source in MOS

For optimum noise figureFor optimum noise figure::

Noise figure( cont’d)

Minimum noise figure (Neglecting the gate resistance and inductor losses & without any power constraints):

Gopt= 20m mho( Gs) Cgs can be calculated from above Eq. Choose smallest possible length[ to make ωT(~1/L2) high].Then find out W, from the relation Cgs= 2/3 Cox. W*L.(in saturation)This calculation gives a very high W value , which makes large power consumption, ………therefore noise minima condition is not preferable for choosing device geometry.

…….. .. Analysis based on Analysis based on power constraint noise figure calculationpower constraint noise figure calculation ::

More complex form( considering all losses)

Noise (cont’d)

Simplified form

Power constraint Noise minimum

Without Power constraint Noise minimum

The FminP differ from Fmin about 0.5dB to 0.7 dB more(∞ <1)But the FminP are more reliable one from practical circuit design point of view.

It is difficult to achieve maximum gain, minimum power consumption , minimum noise figure & good input match at a single value of Wopt & bias ( Vgs)……we are now working to develop efficient algorithm for setting global optimum for different constraints.

γ, δ, α→ device geometry and scaling dependent constants

Other LNA StructuresThis is a common gate topology. the impedance

looking from source end is 1/(gm+gm-bulk). This should be made 50ohm for matching (active matching).

The Ls cancels the Cgs value.

The noise figure is poor.

Good linearity.

Common gate LNA structure This is an inverting amplifier topology.

Large gain {~(gm1+gm2)}.

Bias current reusable.

Relatively small Bias current for identical gain.

The noise figure is poor. Complementary LNA structure

Differential LNA

The single ended LNA (especially for source degeneration topology), the ground parasitic inductor is a crucial since degeneration inductor value is small → parasitic dominates in operationThe ground inductor can be tuned by putting extra cap across ground line inductor, but any cap in source line produces a negative resistance in input. This causes stability problem.

Remedy → Differential structure

INTER-STAGE MATCHING LNA

Provides better gain Relatively low noise FigureProvides 50 Ohm input/output impedanceMinimum power dissipation

• Provides a negative resistance & extra inductance at I/P

• Matching condition changed

1 V Low Noise Amplifier

Performance Parameters

Values in the typical corner

Supply Voltage 1 VoltBandwidth 825 - 975 MHz

Voltage Gain 16.53 dBPower Consumption 4.06 mW

Noise Figure 2.327 dB

Native MOSes used to facilitate low voltage operation

The input N/W consisting of LG and CGS is tuned to 900 MHz.

The LC load is also tuned to 900 MHz.Gate induced noise is included in simulation by

an equivalent resistor.

Schematic

ON-CHIP GHz OSCILLATORS

Voltage Controlled Oscillators

Used for channel selection.Frequency depends on Input Control Voltage.Frequency change is made by tuning passive elements (e.g. varactors in LC oscillators) or by changing current/voltage supply (e.g. in ring oscillator).Governing Equation is:

Here; Kvco ≡ VCO Gain (Hz/volt).Vcontrol ≡ Input Control Voltage (volts).

Fout = Kvco * Vcontrol

VCO Specifications

Center Frequency; ωo (GHz)Tuning Range (MHz)Tuning Sensitivity; KVCO (Hz/volt)Spectral Purity or Phase Noise (dBc/Hz @ Hz offset)Power Consumption (mW)Output Power (mW)Harmonic Suppression (dBc)Load Pulling : Frequency changes with Load changesSupply Pulling : Frequency change with VDD (Hz/volt)

TYPES of OSCILLATORS

Oscillators are autonomous circuits that produce periodic output without any periodic input.Three main topologies and their Comparison:

TYPE Principle On-chip? GHz ? PN Ring Cascaded inverters YES YES POOR

Relaxation Cap is charged and discharged

YES YES POOR

LC-Tuned LC resonance YES (difficult)

YES GOOD

QVCO Architecture

Injection Locked Divider

900 MHz

Cross Coupled D Latch

LC VCO

1.8 GHz

Frequency Divider

I

Q

+

+

-

-

+

+

-

-

+

+

-

-

+

+

-

-

Ring Oscillator

LC VCO

900 MHz

LC VCO

I

Q

Cross-coupled QVCO

Worse Phase Noise as compared to LC oscillator

Requires more inductors

Inductors become bulky at lower frequency

Higher Q at this relatively higher frequency

Lower power consumption

Lower Phase Noise

Low area overhead

Capacitive Cross-coupling of PMOS pair

Native MOSBinary weighted switched

capacitors

Common Mode Feedback

Cross-coupled PMOS

Varactor

Cross-coupled NMOS

-2/gm

-2/gm -2/gm

The Complementary structure is chosen as it provides more energy to the tank as compared to the NMOS only structure for same current bias

VDS

VGS

VGS = VDS

VDS

VGS

VGS ≠ VDS

VCO Core: LC negative Resistance Oscillator

1V1V

Vth~ 80 mVHelps to combat Voltage

headroom problem

Increases the tuning range while keeping KVCO low.

Tuning becomes more linear

0.18 μm technology

1 V Supply Voltage

Threshold Voltage ~ 0.5 V.

VCO Core : Salient Features

• Voltage headroom solution– NMOS pair is replaced by Native MOS – PMOS pair is capacitively cross-coupled

• Common mode feedback is required to keep the output DC levels fixed.– The supply sensitivity of frequency decreases as the dc bias across the

varactor does not change with supply.

• Bank of switched capacitors is used for discrete tuning– Increases tuning range (150 MHz) keeping KVCO (~50 MHz/V) low.– Improves linearity of the frequency change with control voltage.

• Consumes only 2.5 mW of power.

Frequency Divider

Frequency Divider

Clk-Clk+

D-

Q+Q-

D+

D Flip-flop

Provides quadrature signals at 900 MHz for input signal (clk) of 1.8 GHz.

Self oscillation frequency of the Divider is designed to be 900 MHz

Condition for self-oscillation:

Tail current source for the Flip-flops were removed to accommodate 1 V supply

Consumes 1 mW power.

1>× Rg m

gm

R

Simulation results: Plots

Variation of frequency and KVDD(Δf/ΔVDD) with supply voltage

Tuning curves

Output waveform of VCO and QVCOPhase noise

Comparison with other results

Parameters [1] [2] [3] Our work

Technology 0.25 μm 0.18 μm 0.18 μm 0.18μmSupply (Volt) 2.5 1.8 1.5 1Tuning Range(GHz) 1.71–1.99 1.05–1.39 0.667-

1.1560.825–0.975

KVCO(MHz/V) -- -- -- 50

Phase Noise -143@ 3 MHz

-137@ 3 MHz

-124@600KHz

-136@ 3 MHz

KVDD(MHz/V) -- -- -- 6Power (mW) 20 5.4 30 3.5FOM (dBc/Hz) -185.5 -180.96 -- -180.1

2

0

/S S B V C OfF O M S P m W

f⎛ ⎞Δ

= ⎜ ⎟⎝ ⎠

System simulation results

Noise Figure IF output for 1 mV RF input

Measurement Results (VCO)(contd.)

PMOS Gate Bias(mV)

Output Power (dBm)

0.329 -21.9

0.362 -23

0.411 -24

0.452 -27

0.519 -36

0.526 -60

Output Power variation with bias Output spectrum and phase noise measurement

MIXERS

MIXER

Ideal Mixer → Ideal Mixer → Multiply signals.Multiply signals.Mixer is a Frequency translator circuit.Mixer is a Frequency translator circuit.

Acos(w1t) * Bcos(w2 t) = (AB/2)* [ cos(w1+w2)t + cos(w1-w2)t ]

up-conversion down-conversion

Block diagram representation of Mixer Basic Mixer operation and its MOS equivalent

Special considerations for Mixer Design

Provides efficient frequency translation.Low noise figure (10-13 dB).A moderate conversion gain (8-15 dB).Low LO coupling to RF Port (10-20 dB).High linearity (-6 – 15 dBm, IIP3).Suppression of LO feed-through to the IF port.Provides good image rejection ( some times require to add image rejection filter).IF matching. Low distortion.Power consumption (3-5 mW) and Area consideration.

Classification

On the basis of operating mechanism :a) Switching type – switch the RF signal path ON & OFF at

LO frequency. b) Non linear type – use the non linear characteristic of

device.

On the basis of gain of a mixer : a) Passive mixer – switch type, conversion gain less than one,

less noise. b) Active Mixer – nonlinear type, conversion gain greater

than one, more noise.

Different topologies of CMOS Active Mixer1. Square law MOSFET Mixer

RF signal drives the gate while LO drives the source.For long channel devices :

id = β/2*(Vgs –VT)2

=β/2*{VBIAS+[vRFcos(wRFt)-vLOcos(wLOt)]-VT}2

The useful term is the product of cos(wRFt) and cos(wLOt). All other terms are removed by filtering.The output contains a dc part, RF and LO feed-through, and number of harmonics.Conversion gain = β/2*(VLO).For low IF down-conversion, LC tuned output network is replaced by RC network.

Drawbacks : High chances of LO to IF feed-through, poor port isolation between RF, LO & IF.For short channel device : id α (VGS –VT). So it can not be used .

Different topologies (continued)…2. Single balanced mixer

Output is balanced to RF signal.Exhibits superior performance.Ideally generates inter-modulation terms.The inputs are entered at separate ports – gives high degree of isolation among RF, LO & IF.Converts the RF voltage into a current through trans-conductance.Performs multiplication in current domain.Approximate expression of output current :

iout(t) = sgn [cos(wLOt)] * [ IDC + IRFcos(wRF)t ] sgn(x) = 4/π[ sin(x) + (1/3)sin3(x) + (1/5) sin5(x) + …..]

Actual current equation can be established on the basis of Actual current equation can be established on the basis of single stage differential amplifier with time varying large LO isingle stage differential amplifier with time varying large LO in n differential part and small ac RF signal in tail current part.differential part and small ac RF signal in tail current part.

Conversion gain Conversion gain αα (2/(2/ππ ))2 2

ADV:ADV: Differential output gives higher gain and more immunityDifferential output gives higher gain and more immunityfor RF to IF feedfor RF to IF feed--throughthrough

DISDIS--ADV:ADV: High LO to IF feedHigh LO to IF feed--through, Large power through, Large power consumption compared to previous topology, noise figure increasconsumption compared to previous topology, noise figure increases.es.

Different topologies (continued)…3. Double balanced Mixer

Output is balanced to both RF and LO.Has high degree of LO-IF isolation.The LO drive should be large enough, so that the differential pair behaves as switch.Two signals in double balanced mixer are connected in anti-parallel for LO signal but in parallel for RF signal – LO terms sum to zero at output and RF is doubled.

iout(t)= 2IRF * sgn * [cos(wLOt)] * [cos(wRF)t ]• Actual current equation can be established on basis of single stage differential

amplifier, with time varying large LO in upper part of differential pair and smallac RF signal in lower part of differential part .

Conversion gain Conversion gain αα (4/(4/ππ ))22..ADV:ADV: Gives higher port isolation among RF, LO &Gives higher port isolation among RF, LO &

IF. Gives higher conversion gain.IF. Gives higher conversion gain.DIS ADV:DIS ADV: large power consumption, large noiselarge power consumption, large noise

figure.figure.

Two Important MixerGilbert Type Mixer

Conversion gain = gmRL2/π

Design issuesThe gain and IIP3 are determined by tail current( Iss). The increase of tail current improves the performance, however the voltage drop across load resistance drives the RF transistor out of saturation. As a result conversion gain and IIP3 suffers. Increasing load resistance increases gain, but cannot be increased indefinitely as the RF transistors come out of saturation.

Even Harmonic MixerEven Harmonic Mixer

The circuit is a "three level multiplier", composed of two stages, a double-balanced switching cell and a differential transconductance stage.

DOUBLED BALANCED EVEN-HARMONIC MIXER

Low IF Receiver Architecture

PCB matching components

PCB 50 ohm Transmission line

850 – 950 MHz

+

- +

-

850 – 950 MHz

+

- +

-

850 – 950 MHz

1.7-1.9 GHz+

-+-

+

-+-

0180

90270

I

LO (VCO+Div2+Buffer)

Q

1 MHz

1 MHz

LNACurrent reuse gain stage

Gilbert Cell

Layout of the complete RF Front-End (KGPLPRX)

Total Die size ~2mmX2mm

System Die size ~ 1mmX1mm

System

System QVCO

LNA &Mixer

LNA

FREQEUNCYSYNTHESIZERS

Building blocks of frequency Synthesizer

PLL based frequency synthesizer is a negative feedback system that locks both phase & frequency Basic building blocks of PLL based frequency synthesizer are

Phase Frequency Detector (PFD) Sequential tri-state dual DFF PFDCharge Pump Constant UP/DOWN Current sources with Switches on DrainLoop filter Passive 3rd order low pass filterVoltage Control Oscillator (VCO) Low KVCO, low KVDD, low phase noise LC VCO with on-chip inductorProgrammable Integer N Frequency Divider Divide by 2/3 pre-scalar structure with both Current Mode Logic (CML) structure for high frequency division and digital logic structure for low frequency division

Frequency Synthesizer

Motivation-All frequencies in the band of interest from the reference frequencyHigh degree of purity due to the ever decreasing channel spacingLow power consumptionLow costHigh integrationExplosive growth in demand for wireless communication services

Direct Analog/Digital Synthesis-Fine frequency resolutions and fast switching timesNot suitable for high frequency and low phase noise synthesis

Indirect PLL based Synthesis-Fine frequency resolutions and fast switching timesSuitable for high frequency stability and accuracy, low phase noise and high frequency (even in giga-hertz frequency range) synthesisAmenable to full integration on a standard CMOS technology

Block Diagram of frequency Synthesizer

PFD CHARGEPUMP

LOOPFILTER

VCO

FREQUENCYDIVIDER

REFERENCEFREQUENCY OUTPUT

FREQUENCY

Channel Control (8 bit)

VCO Cap Control (5 bit)

Linear PLL Model

Phase → Independent variable.For phase variable → VCO is perfect integrator.Different blocks modeled as:

PFD PFD → Difference Block→ Difference BlockCharge PumpCharge Pump → Constant gain, (→ Constant gain, (KcpKcp))Loop FilterLoop Filter → generic Transfer → generic Transfer function F(s)function F(s)VCOVCO → Integrator with constant gain, → Integrator with constant gain, (Kvco/s)(Kvco/s)Frequency DividerFrequency Divider → Divider ratio → Divider ratio (N)(N)

PLL Large Signal Behavior

> FREF; Down Exact PLL locking is nonlinear phenomena.If FVCO/N output of PFD will turn enable more often than Up.Loop filter control voltage → goes down → FVCOgoes down.Typically; ts = 25/FREF.ts : settling time.

Locking Behavior of PLLLocking Behavior of PLL

Phase Frequency Detector

Gives difference between Reference and output phases.Usually implemented digitally.Most widely used topology → Sequential tri-state dual DFF PFD.

Operation of Sequential PFDOperation of Sequential PFD

Charge PumpGives infinite DC gain with passive filters → Needed for zero phase error.Consists of two or more Current sources, switched ON/OFF by PFD outputs.Mismatches & Leakage in charge pump → Spurious component in PLL output.Three main topologies:

Switch on Source → Fastest, Lowest mismatches, Minimum overshoots,easily scaleable.

Switch at DrainSwitch at Drain

Switch at SourceSwitch at Source

Switch at GateSwitch at Gate

Loop Filter

Usually a Low pass filter.Provides a stabilizing zero for the loop (C2, R2).Determines loop’s transient behavior.Active or passive implementation possible.Passive filter → No active device noise, easy on-chip implementation.Filter order → decides spurioussuppression (typically 2-3).Filter Design parameters:

Loop Bandwidth Loop Bandwidth →→ Decided by Decided by settling time requirementssettling time requirements

Phase margin → Decided by Phase margin → Decided by maximum permissible overshoot maximum permissible overshoot Third order passive Loop Filter

VCO

VCO parameters, most relevant to Frequency Synthesizers:

Details of VCO design has been discussed in previous chapter………

1.1. KKVCOVCO requirements → Should be linear requirements → Should be linear

2.2. Phase Noise → Should meet the specificationsPhase Noise → Should meet the specifications

3.3. Settling time → Should be much higher than PLL loop Settling time → Should be much higher than PLL loop band widthband width

4.4. VCO isolation → Buffers should be added at the outputVCO isolation → Buffers should be added at the output

5.5. Power consumption → Should conform the system Power consumption → Should conform the system requirements.requirements.

Programmable DividerOnly block (except VCO) that operates at RF frequency.Implementation is critical → Power hungry, high speed.Most popular Architecture → based on Pre-scalar.Only pre-scalar operates at highest frequency.Output Frequency = P*N + APre-scalar → Current Mode Logic (CML)CML → Constant current, No power line spikes, Low power at GHz frequencies. A CML DFF-AND gate

(Divider cont’d)Prescalar architecture → Not modular → Complex LayoutArchitecture based on 2/3 divider cells:

Programmable 2/3 divider cells are Programmable 2/3 divider cells are cascaded.cascaded.

For N cells, Division range : 2For N cells, Division range : 2NN ––(2(2N+1N+1 -- 1).1).

Highly regular structure.Highly regular structure.2/3 Divider cell schematic

2 cascaded 2-3 cells in divide by 7 mode

Simulation & Silicon Tested Results

Parameter Simulation Result Results Tested on fabricated chip

Frequency range of operation 2.4 GHz – 2.4835 GHz 2.3964 GHz - 2.4788 GHz

No of channels 16 16

Channel spacing 5MHz 5MHz

VCO gain 60 MHz / V --VCO current 2.5 mA --

Charge pump current 50uA --

Division ratio 480 – 495 480 – 495

Open loop unity gain frequency (PLL -3dB BW)

100 kHz --

Phase margin 50 degree --Total power consumption 9 mW 9mW

Layout of Frequency Synthesizer And Test Setup of the chip

Die area: 1812.4um x 1965.04um Snapshot of the PCB

Silicon Testing : PLL locking check (Fref=5MHz).

Divider output Divider output when no input is when no input is given; Unlocked given; Unlocked conditioncondition

Divider output Divider output when 5MHz input when 5MHz input is given; locked is given; locked conditioncondition

Channel selection by Divider control in locked condition

There are 8 control bit is used to select a channel among the 16 channel over the frequency range 2.40-2.48GHz .The divider ratio is changed with change of control bits .Only 4 LSB bits are used for 16 channel selection, extra 4 MSB bits are added to select out of band frequency. The test results are shown in the following table

4MSB+ 4 LSB divider control bits(8)

VCO freq measured GHz

Ideal output as 5MHz reference

1110,1000 (488) 2.4426 2.44

1110,0000 (480) 2.3964 2.4

1110,1111 (495) 2.4788 2.475

1110,1100 (492) 2.4664 2.46

1110,0100 (484) 2.4194 2.42

For first phase of testing, we taken the reference frequency from a signal generator, which gives frequency variation from 4.992M-5.008MHz instead of fixed 5MHz, that’s why the comparison table are slightly mismatched

Channel selection by Divider control inlocked condition

Divider ratio:Divider ratio:1110,1111 (495)1110,1111 (495)

Divider ratio:Divider ratio:1110,0000 (480)1110,0000 (480)

VCO centre frequency tuning

• There are 5 control bit is used to compensate the VCO center frequency variation of due to process. These are shown in the following table

Cap_cntl bits(5) VCO freq measured GHz

Divider o/pfrequency MHz

00000 2.6044 5.336

00110 2.4404 5

00111 2.4148 4.448

11111 1.9704 4.032

Comparison of performance• The frequency synthesizer consumes very less power which is lowest

reported till now for Integer-N frequency synthesizer in 2.45GHz Zigbee application

• This structure gives low KVCO and KVDD• The reference signal are given through a signal generator rather than from a

crystal oscillator , thus we expect better phase noise performance of the frequency synthesizer by using crystal.

• Setting time measurement of FRS is on process

Conditions VDD Supply Current I(VDD)

Maximum Supply voltage checked

2.5V 8.2mA

Minimum supply voltage for which the chip is functional

1.40V 3.4mA

Normal Operating Condition 1.8V 5mA

Supply Voltage Variation and Operating CurrentSupply Voltage Variation and Operating Current

Comparison of performance (cont ..)

Operating frequency

VCO phase noise

Power consumption

This work 2.4 -2.4835GHz

-104 dBc/Hz @ 3MHz offset

9mW

4) 2.4-2.5GHz -112 dBc/Hz @ 1MHz offset

20mW

6) 2.4-2.5GHz -116 dBc/Hz @ 2MHz offset

Total current of 66mA from 2.7-3.3V supply for

full system

5) 2.4GHz band -104 dBc/Hz @ 1MHz offset

17mW

7) 2.45GHz (center freq.)

-126 dBc/Hz @ 2MHz offset

-

• VCO Phase noise is taken from Simulation Result

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