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MOS Transistor Modeling for RF Integrated Circuit Design
INTRODUCTIONINTRODUCTIONStrong demand for low-cost, small form-factor and low-power transceiversDeep submicron CMOS well suited for wireless
High ft and good RF noise performanceHigh integration capabilities
Design of RF ICs remains a challengeCrucial to accurately predict performance of RF ICsRequires accurate MOST models valid for all bias from dc to RF and for a large range of geometries
MOS Transistor Modeling for RF Integrated Circuit Design
TYPICAL RF MULTIFINGER DEVICETYPICAL RF MULTIFINGER DEVICERF MOS Transistors are usually large devicesImplemented as multi-finger devices due to limited width
G
S
D
S
D
S
Wf
Lf
Nf : # of fingers
Wf : width of a single finger
Lf : length of a single finger
Weff=Nf·Wf : total width
Minimum # of drain diffusions
MOS Transistor Modeling for RF Integrated Circuit Design
TRANSIT FREQUENCY EVOLUTIONTRANSIT FREQUENCY EVOLUTION
H. Iwai and H. S. Momose, “Technology Towards Low-Power / Low-voltage and Scaling of MOSFETs,” Microelectronic Engineering, vol. 39, No. 1-4, pp. 7-30, Dec. 1997.
SMALLSMALL--SIGNAL MOST MODELING AT RFSIGNAL MOST MODELING AT RFEquivalent circuit at RFApproximate Y-parameters analysisSubstrate couplingNQS versus QS
MOS Transistor Modeling for RF Integrated Circuit Design
The different RC time constants due to Rs and Rd do not depend on Weff but only on the gate length Lf and overlap length LovThe poles due to Rs and Rd are at a much higher frequency than typically the transit frequency ft and can therefore be neglected when calculating the Y-parameters
ffeff WNW ⋅≡
MOS Transistor Modeling for RF Integrated Circuit Design
EFFECT OF VELOCITY SATURATIONEFFECT OF VELOCITY SATURATION
For short-channel devices in SI and saturation ⇒ lateral electrical field larger than critical field ⇒ carrier velocity saturationCarrier velocity limited ⇒ additional charge builds up close to the drain ⇒ additional thermal noise without increase of gm ⇒increase of γsat compared to the long-channel value 2/3
HOT CARRIERS AND EFFECTIVE TEMP.HOT CARRIERS AND EFFECTIVE TEMP.High lateral electric field ⇒ carrier not in thermal equilibrium with lattice ⇒ higher carrier temperature ⇒ higher thermal noise
31
1
K=
+⋅=
mEETT
m
t
xeff
P. Klein, EDL, Aug. 1999.
MOS Transistor Modeling for RF Integrated Circuit Design
EXCESS NOISE FACTOR MODEL (1/2)EXCESS NOISE FACTOR MODEL (1/2)In SI and in saturation, these effects can be included in a modified noise excess factor according
112 −+⋅−⋅=
⋅−≡
effc
SP
effc
SDsatLEVV
LEVVz
)1()1( 21
32 +⋅⋅⋅++⋅= zz
EEzt
csatγ
velocity saturation hot carriers
where
VDsat corresponds to the drain voltage at which the output conductance becomes zero
Fmin, Rv, Gopt and Bopt (or Γopt) are the four noise parameters extracted from noise measurementsF=Fmin for Gs=Gopt AND Bs=Bopt (noise matching)The circuit parameters Gi, Gc and Bc are given by
( )optc
optc
optoptopti
BBRGRF
G
RBGRYG
−=−−
=
⋅+=⋅=
v
v
vv
212min
222
MOS Transistor Modeling for RF Integrated Circuit Design
MODERATE INV. FOR RF CIRCUITSMODERATE INV. FOR RF CIRCUITSMoving operating points from strong to moderate or even weak inversion offers the following advantages:
Higher current efficiency (higher gm/ID)Lower electrical fields within device
No velocity saturation (1/L2 scaling instead of 1/L)No hot electrons (lower noise excess factor)
Low-voltage operation compatible with the supply voltages required by deep-submicron processes
Higher nonlinearity due to exp I-V lawModerate inversion seems to be a good trade-off
MOS Transistor Modeling for RF Integrated Circuit Design
CONCLUSIONCONCLUSIONSimple scalable RF MOS model implemented in Spice as a subCKT has been presentedGate resistance, intra-device substrate coupling, NQS effects, thermal noise, induced gate noiseValidated up to 10 GHz, from moderate to strong inversion and for several geometriesFor deep submicron processes, operating points can be moved from strong to moderate inversion
Better current efficiency, no high electrical field effectsGood trade-off for low-voltage
MOS Transistor Modeling for RF Integrated Circuit Design
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