1 Introduction to CMOS VLSI Design Logical Effort Part A Lecture by Jay Brockman University of Notre Dame Fall 2008 Modified by Peter Kogge Fall 2010,2011,2015, 2018 Based on lecture slides by David Harris, Harvey Mudd College http://www.cmosvlsi.com/coursematerials.html Slide 1 Logical Effort A CMOS VLSI Design Logical Effort A Slide 2 Slide 2 Introduction Chip designers face a bewildering array of choices – What is the best circuit topology? – What gives least delay? – How wide should the transistors be? Logical effort: a method to make these decisions – Simple model of delay – “Back-of-the-envelope” – Rapid comparisons between alternatives – Emphasizes remarkable symmetries ? ? ?
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1
Introduction toCMOS VLSI
Design
Logical Effort Part A
Lecture by Jay BrockmanUniversity of Notre Dame Fall 2008
Modified by Peter Kogge Fall 2010,2011,2015, 2018Based on lecture slides by David Harris, Harvey Mudd College
http://www.cmosvlsi.com/coursematerials.html
Slide 1Logical Effort A
CMOS VLSI DesignLogical Effort A Slide 2Slide 2
Introduction Chip designers face a bewildering array of choices
– What is the best circuit topology?
– What gives least delay?
– How wide should the transistors be?
Logical effort: a method to make these decisions
– Simple model of delay
– “Back-of-the-envelope”
– Rapid comparisons between alternatives
– Emphasizes remarkable symmetries
? ? ?
2
CMOS VLSI DesignLogical Effort A Slide 3Slide 3
Motivating Example Ben Bitdiddle is the memory designer for the Motoroil 68W86,
an embedded automotive processor. Help Ben design the decoder for a 16x32 register file.
Decoder specifications:– 16 word register file– Each word is 32 bits wide– Each file bit presents load of 3 unit-sized transistors– Both true & complementary address inputs A[3:0] available– Each address input may drive 10 unit-sized transistors
Ben needs to decide:– How many stages to use in decoder driver output buffers?– How large should each gate be?– How fast can decoder operate?
A[3:0] A[3:0]
16
32 bits
16
wo
rds
4:16 Decoder
Register File
CMOS VLSI DesignLogical Effort A Slide 4
Some Review k: transistor’s width is k times unit width
On resistance is 1/k times unit transistor
Cg is capacitance of gate to body
– Unit transistor’s Cg is “1 unit”
– Cg-k is k times Cg-unit of unit transistor
Cdiff is capacitance to body from a contacted source or drain
– Approximately = Cg
Diffusion capacitance of uncontactedsource or drain is less (approx ½)
– For simplicity assume the same
k
Cg
Cdiff
Slide 4
3
CMOS VLSI Design
N vs P Widths To make rise ≈ fall time, want ~ equality between
– On resistance of N side of circuit
– On resistance of P side of circuit
Remember
– Unit width PMOS ≈ 2X unit width NMOS
– Resistors in series add
– Resistors in parallel = 1/sum(reciprocal of Rs)
When multiple paths are possible
– Reflecting multiple possible input conditions
– Choose one with max resistance
Logical Effort A Slide 5
CMOS VLSI DesignLogical Effort A Slide 6
Elmore Delay Model
Delay = ∑Rn-iCi ~ ∑Ci∑Rji i=1
N
j=1
i
Slide 6
Vout
4
CMOS VLSI DesignLogical Effort A Slide 7
What If Output Not At End?
Delay = R1*∑Ci
Slide 7
Vout
Ignore R2 thru Rn, & just sum C’s
In reality, C2, … CN “shielded” by R’s (don’t have to charge all way to voltage at Y)
Thus a “conservative” estimate
CMOS VLSI Design
Resistance Examples
Logical Effort A Slide 8
1R
(2R)/2
½ R + ½ Rwhen both on
(2R)/2when either on
Why?
Why?
5
CMOS VLSI DesignLogical Effort A Slide 9
What’s Cin: the Input Capacitance?
Assuming:• gate size is indicated as # in each transistor• gate capacitance of unit transistor 1 Cg = C
for both A & B for both A & B
CMOS VLSI Design
General Input Capacitance:Minimum Transistors
Logical Effort A Slide 10
# of Inputs NAND NOR
1 3C:Inverter
2 4C 5C
3 ? ?
4 ? ?
N ? ?
How About for K inputs: (K+2)C (2K+1)C
6
CMOS VLSI DesignLogical Effort A Slide 11
Sample Circuit Extraction
Assuming all diffusion nodes contacted
Real worldSlightlysmaller
CMOS VLSI Design
Key Definitions Parasitic Delay: gate delay when no load attached
– Count only diffusion capacitances
Contamination Delay: Minimum (fastest) time from some input changes until any output starts to change
– Look for input pattern that minimizes delay
Logical Effort of some gate: ratio of its input capacitance to input capacitance of inverter that can deliver same output current
– I.e. has same pullup/pulldown resistance
Ideal Delay: ideal inverter (with no parasitic diffusion capacitance) driving an identical inverter
Effort Delay: Delay imposed by external load
Logical Effort A Slide 12
7
CMOS VLSI DesignLogical Effort A Slide 13Slide 13
Approximate Parasitic Delay of Gates
Parasitic Delay (Normalized)
Gate type
Number of inputs
1 2 3 4 n
Inverter 1
NAND 2 3 4 n
NOR 2 3 4 n
Tristate / mux 2 4 6 8 2n
XOR, XNOR 4 6 8
Parasitic delay = delay when it drives zero load
Normalized to multiples of pinv = 3RC
CMOS VLSI DesignLogical Effort A Slide 14
Real Life Parasitic Delay
Applying Elmore model when all but lowest=1 & lowest:0→1:
tpd = (n2/2 + 5n/2)RC
Note the square term!!!!Big gates are sloooowwwwweeeeerrrrrr
8
CMOS VLSI Design
Contamination Delay Minimum time from some input
change until any output starts to change for any input pattern
– A function of load capacitance
E.g. 3NAND: On fall, best if both bottom NMOS Ts on
– Diffusion cap already drained
– Only R effective left
– Delay = ?
On rise, best when ALL 3 PMOS turn on
– Resistances in parallel
– Delay = ?
Delay B Slide 15
CMOS VLSI DesignLogical Effort A Slide 16
3 Input NAND
Slide 16
When all inputs high
When oneinput low
What is circuit forall inputs
low?
9
CMOS VLSI DesignLogical Effort A Slide 17Slide 17
Logical Effort Logical effort g: ratio of input capacitance of a gate
to the input capacitance of an inverter delivering the same output current (same pullup/down resistance).
Measure from delay vs. fanout plots
Or estimate by counting transistor widths
AND divide by 3 to “normalize”
A YA
B
YA
BY
1
2
1 1
2 2
2
2
4
4
Cin = 3g = 3/3
Cin = 4g = 4/3
Cin = 5g = 5/3
CMOS VLSI DesignLogical Effort A Slide 18Slide 18
Logical Effort of Gates
Logical Effort (Normalized)
Gate type
Number of inputs
1 2 3 4 n
Inverter 1
NAND 4/3 5/3 6/3 (n+2)/3
NOR 5/3 7/3 9/3 (2n+1)/3
Tristate / mux 2 2 2 2 2
XOR, XNOR 4, 4 6, 12, 6 8, 16, 16, 8 ?
All inputs are not the same!
10
CMOS VLSI DesignLogical Effort A Slide 19Slide 19
Now Consider Loaded Gates Estimate worst-case rising and falling delay of 2-
input NAND driving h identical 2in NAND gates.
h copies
2
2
22
B
Ax
Y
CMOS VLSI DesignLogical Effort A Slide 20
Summary Delay Estimation
Assume driving h identical 2in NANDSOnly 1 pmos on for slowest case
Rise delay Fall delay
Assume internal node x charged(i.e. A=1, B: 0→1)
Elmore delays:Worst Case Rise = R(6+4h)C = (6+4h)RCWorst Case Fall = (R/2)(2C) + R*(6+4h)C = (7+4h)RC
11
CMOS VLSI DesignLogical Effort A Slide 21
What If All Transistors k Wider?
Elmore delays if driving h copies of scaled gates:Worst Case Rise = (6+4h)RCWorst Case Fall = (7+4h)RC
• What happens to capacitances? Resistance? • Assume output load = 4h’C
• h’=h if driving small gates; = kh if larger gates
The same as before: WHY?
CMOS VLSI DesignLogical Effort A Slide 22
Ideal Gate Delay Imagine ideal inverter (with no parasitic diffusion