1 Introduction to CMOS VLSI Design Lecture 1: Circuits & Layout David Harris Harvey Mudd College Spring 2004 1: Circuits & Layout Slide 2 CMOS VLSI Design Outline A Brief History CMOS Gate Design Pass Transistors CMOS Latches & Flip-Flops Standard Cell Layouts Stick Diagrams
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Introduction to CMOS VLSI Design · 1: Circuits & Layout Slide 7CMOS VLSI Design 1970’s processes usually had only nMOS transistors – Inexpensive, but consume power while idle
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Invention of the TransistorVacuum tubes ruled in first half of 20th century Large, expensive, power-hungry, unreliable1947: first point contact transistor– John Bardeen and Walter Brattain at Bell Labs– Read Crystal Fire
by Riordan, Hoddeson
1: Circuits & Layout Slide 6CMOS VLSI Design
Transistor TypesBipolar transistors– npn or pnp silicon structure– Small current into very thin base layer controls
large currents between emitter and collector– Base currents limit integration density
Metal Oxide Semiconductor Field Effect Transistors– nMOS and pMOS MOSFETS– Voltage applied to insulated gate controls current
between source and drain– Low power allows very high integration
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1: Circuits & Layout Slide 7CMOS VLSI Design
1970’s processes usually had only nMOS transistors– Inexpensive, but consume power while idle
1980s-present: CMOS processes for low idle power
MOS Integrated Circuits
Intel 1101 256-bit SRAM Intel 4004 4-bit µProc
1: Circuits & Layout Slide 8CMOS VLSI Design
Moore’s Law1965: Gordon Moore plotted transistor on each chip– Fit straight line on semilog scale– Transistor counts have doubled every 26 months
Series and ParallelnMOS: 1 = ONpMOS: 0 = ONSeries: both must be ONParallel: either can be ON
(a)
a
b
a
b
g1
g2
0
0
a
b
0
1
a
b
1
0
a
b
1
1
OFF OFF OFF ON
(b)
a
b
a
b
g1
g2
0
0
a
b
0
1
a
b
1
0
a
b
1
1
ON OFF OFF OFF
(c)
a
b
a
b
g1 g2 0 0
OFF ON ON ON
(d) ON ON ON OFF
a
b
0
a
b
1
a
b
11 0 1
a
b
0 0
a
b
0
a
b
1
a
b
11 0 1
a
b
g1 g2
1: Circuits & Layout Slide 14CMOS VLSI Design
Conduction ComplementComplementary CMOS gates always produce 0 or 1Ex: NAND gate– Series nMOS: Y=0 when both inputs are 1– Thus Y=1 when either input is 0– Requires parallel pMOS
Rule of Conduction Complements– Pull-up network is dual of pull-down– Parallel -> series, series -> parallel
A
B
Y
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1: Circuits & Layout Slide 15CMOS VLSI Design
Compound GatesCompound gates can do any inverting functionEx: (AND-AND-OR-INVERT, AOI22)Y A B C D= +
A
B
C
D
A
B
C
D
A B C DA B
C D
B
D
YA
CA
C
A
B
C
D
B
D
Y
(a)
(c)
(e)
(b)
(d)
(f)
1: Circuits & Layout Slide 16CMOS VLSI Design
Example: O3AI( )Y A B C D= + +
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1: Circuits & Layout Slide 17CMOS VLSI Design
Example: O3AI ( )Y A B C D= + +
A B
Y
C
D
DC
B
A
1: Circuits & Layout Slide 18CMOS VLSI Design
Signal StrengthStrength of signal– How close it approximates ideal voltage source
VDD and GND rails are strongest 1 and 0nMOS pass strong 0– But degraded or weak 1
pMOS pass strong 1– But degraded or weak 0
Thus nMOS are best for pull-down network
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1: Circuits & Layout Slide 19CMOS VLSI Design
Pass TransistorsTransistors can be used as switches
g
s d
g
s d
1: Circuits & Layout Slide 20CMOS VLSI Design
Pass TransistorsTransistors can be used as switches
g
s d
g = 0s d
g = 1s d
0 strong 0Input Output
1 degraded 1
g
s d
g = 0s d
g = 1s d
0 degraded 0Input Output
strong 1
g = 1
g = 1
g = 0
g = 0
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1: Circuits & Layout Slide 21CMOS VLSI Design
Transmission GatesPass transistors produce degraded outputsTransmission gates pass both 0 and 1 well
1: Circuits & Layout Slide 22CMOS VLSI Design
Transmission GatesPass transistors produce degraded outputsTransmission gates pass both 0 and 1 well
g = 0, gb = 1a b
g = 1, gb = 0a b
0 strong 0
Input Output
1 strong 1
g
gb
a b
a bg
gb
a bg
gb
a bg
gb
g = 1, gb = 0
g = 1, gb = 0
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1: Circuits & Layout Slide 23CMOS VLSI Design
TristatesTristate buffer produces Z when not enabled
11011000
YAEN
A Y
EN
A Y
EN
EN
1: Circuits & Layout Slide 24CMOS VLSI Design
TristatesTristate buffer produces Z when not enabled
111001Z10Z00YAEN
A Y
EN
A Y
EN
EN
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1: Circuits & Layout Slide 25CMOS VLSI Design
Nonrestoring TristateTransmission gate acts as tristate buffer– Only two transistors– But nonrestoring
• Noise on A is passed on to Y
A Y
EN
EN
1: Circuits & Layout Slide 26CMOS VLSI Design
Tristate InverterTristate inverter produces restored output– Violates conduction complement rule– Because we want a Z output
A
YEN
EN
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1: Circuits & Layout Slide 27CMOS VLSI Design
Tristate InverterTristate inverter produces restored output– Violates conduction complement rule– Because we want a Z output
A
YEN
A
Y
EN = 0Y = 'Z'
Y
EN = 1Y = A
A
EN
1: Circuits & Layout Slide 28CMOS VLSI Design
Multiplexers2:1 multiplexer chooses between two inputs
X11
X01
1X0
0X0
YD0D1S
0
1
S
D0
D1Y
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1: Circuits & Layout Slide 29CMOS VLSI Design
Multiplexers2:1 multiplexer chooses between two inputs
1X11
0X01
11X0
00X0
YD0D1S
0
1
S
D0
D1Y
1: Circuits & Layout Slide 30CMOS VLSI Design
Gate-Level Mux Design
How many transistors are needed?1 0 (too many transistors)Y SD SD= +
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1: Circuits & Layout Slide 31CMOS VLSI Design
Gate-Level Mux Design
How many transistors are needed? 1 0 (too many transistors)Y SD SD= +
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D1
D0S Y
4
2
22 Y
2
D1
D0S
1: Circuits & Layout Slide 32CMOS VLSI Design
Gate-Level Mux Design
How many transistors are needed? 201 0 (too many transistors)Y SD SD= +
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D1
D0S Y
4
2
22 Y
2
D1
D0S
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1: Circuits & Layout Slide 33CMOS VLSI Design
Transmission Gate MuxNonrestoring mux uses two transmission gates
1: Circuits & Layout Slide 34CMOS VLSI Design
Transmission Gate MuxNonrestoring mux uses two transmission gates– Only 4 transistors
S
S
D0
D1YS
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1: Circuits & Layout Slide 35CMOS VLSI Design
Inverting MuxInverting multiplexer– Use compound AOI22– Or pair of tristate inverters– Essentially the same thing
Noninverting multiplexer adds an inverter
S
D0 D1
Y
S
D0
D1Y
0
1S
Y
D0
D1
S
S
S
S
S
S
1: Circuits & Layout Slide 36CMOS VLSI Design
4:1 Multiplexer4:1 mux chooses one of 4 inputs using two selects
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1: Circuits & Layout Slide 37CMOS VLSI Design
4:1 Multiplexer4:1 mux chooses one of 4 inputs using two selects– Two levels of 2:1 muxes– Or four tristates
S0
D0
D1
0
1
0
1
0
1Y
S1
D2
D3
D0
D1
D2
D3
Y
S1S0 S1S0 S1S0 S1S0
1: Circuits & Layout Slide 38CMOS VLSI Design
D LatchWhen CLK = 1, latch is transparent– D flows through to Q like a buffer
When CLK = 0, the latch is opaque– Q holds its old value independent of D
a.k.a. transparent latch or level-sensitive latch
CLK
D Q
Latc
h D
CLK
Q
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1: Circuits & Layout Slide 39CMOS VLSI Design
D Latch DesignMultiplexer chooses D or old Q
1
0
D
CLK
QCLK
CLKCLK
CLK
DQ Q
Q
1: Circuits & Layout Slide 40CMOS VLSI Design
D Latch Operation
CLK = 1
D Q
Q
CLK = 0
D Q
Q
D
CLK
Q
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1: Circuits & Layout Slide 41CMOS VLSI Design
D Flip-flopWhen CLK rises, D is copied to QAt all other times, Q holds its valuea.k.a. positive edge-triggered flip-flop, master-slave flip-flop
Flop
CLK
D Q
D
CLK
Q
1: Circuits & Layout Slide 42CMOS VLSI Design
D Flip-flop DesignBuilt from master and slave D latches
QMCLK
CLKCLK
CLK
Q
CLK
CLK
CLK
CLK
D
Latc
h
Latc
h
D QQM
CLK
CLK
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1: Circuits & Layout Slide 43CMOS VLSI Design
D Flip-flop Operation
CLK = 1
D
CLK = 0
Q
D
QM
QMQ
D
CLK
Q
1: Circuits & Layout Slide 44CMOS VLSI Design
Race ConditionBack-to-back flops can malfunction from clock skew– Second flip-flop fires late– Sees first flip-flop change and captures its result– Called hold-time failure or race condition
CLK1
D Q1
Flop
Flop
CLK2
Q2
CLK1
CLK2
Q1
Q2
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1: Circuits & Layout Slide 45CMOS VLSI Design
Nonoverlapping ClocksNonoverlapping clocks can prevent races– As long as nonoverlap exceeds clock skew
You can use them if you like for safe design– Industry manages skew more carefully instead