International Journal of Heat and Mass Transferkaviany/researchtopics/gshwang08MTE.pdfthe thermal isolation from the surroundings. Thus, for the optimal design, thermal isolation through

International Journal of Heat and Mass Transfer xxx (2008) xxx–xxx

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Contents lists available at ScienceDirect

International Journal of Heat and Mass Transfer

journal homepage: www.elsevier .com/locate/ i jhmt

Micro thermoelectric cooler: Planar multistage

G.S. Hwang a, A.J. Gross b, H. Kim b, S.W. Lee b, N. Ghafouri b, B.L. Huang a, C. Lawrence c, C. Uher c, K. Najafi b,M. Kaviany a,*

a Department of Mechanical Engineering, University of Michigan, Ann Arbor, MI 48109, USAb Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI 48109, USAc Department of Physics, University of Michigan, Ann Arbor, MI 48109, USA

a r t i c l e i n f o

Article history:Received 10 April 2008Available online xxxx

Keywords:Micro thermoelectric (TE) coolerPlanar multistageOptimal designBi2Te3

Sb2Te3

Substrate conductionRadiationThermal isolationThermal network model

0017-9310/$ - see front matter � 2008 Elsevier Ltd. Adoi:10.1016/j.ijheatmasstransfer.2008.10.014

* Corresponding author. Tel.: +1 734 936 0402; faxE-mail address: [email protected] (M. Kaviany).

Please cite this article in press as: G.S. Hwdoi:10.1016/j.ijheatmasstransfer.2008.10.0

a b s t r a c t

A suspended, planar multistage micro thermoelectric (TE) cooler is designed using thermal networkmodel to cool MEMS devices. Though the planar (two-dimensional) design is compatible with MEMS fab-rication, its cooling performance is reduced compared to that of a pyramid (three-dimensional) design,due to a mechanically indispensable thin dielectric substrate (SiO2) and technical limit on TE film thick-ness. We optimize the planar, six-stage TE cooler for maximum cooling, and predict DTmax = 51 K withpower consumption of 68 mW using undoped, patterned 4–10 lm thick co-evaporated Bi2Te3 and Sb2Te3

films. Improvement steps of the planar design for achieving cooling performance of the ideal pyramiddesign are discussed. The predicted performance of a fabricated prototype is compared with experimen-tal results with good agreements.

� 2008 Elsevier Ltd. All rights reserved.

1. Introduction

A pyramid (three-dimensional), multistage thermoelectric (TE)cooler, as shown in Fig. 1(a), has been studied as a vertically cas-caded design for cooling to low temperatures from an ambient,achieving DT = 50–100 K [1–3]. Using bulk n-type Bi2Te3 andp-type Sb2Te3 TE materials [3], commercialized, six-stage pyramiddesigns produce DT = 130–140 K in a vacuum without an activecooling rate. Previous studies have also proposed planar (two-dimensional) designs to overcome technical challenges of the pyr-amid (three-dimensional) design for MEMS fabrication processes[2,4–9]. For the planar design, columnar TE couples in the pyramidstructure are concentrated at the edges of the dielectric plates ofeach stage as shown in Fig. 1(b), and collapsed down to build thesuspended, planar, concentric thermally isolated structure asshown in Fig. 1(c).

Amongst the past micro TE coolers, a single-stage, pyramid de-sign produced DTmax = 1.3 K using n-type Bi2Te3 and p-type Sb2Te3

films [4], and DTmax = 10.9 K using n-type Bi2Te3 and p-type(Bi,Sb)2Te3 films [10], while in [11,12], DTmax = 4.5 K was achievedusing variations of Si and Ge superlattices. For a single-stage, pla-nar design [8], DTmax = 0.76 K was achieved using InGaAs/InGaAsPsuperlattices integrated single-stage planar micro cooler, while

ll rights reserved.

: +1 734 647 3170.

ang et al., Micro thermoele14

DTmax = 15.5 K was measured using a single-stage planar designwith n-type Bi2Te3 and p-type Sb2Te3 films [13].

However, micro, planar designs carry inherent disadvantages inachieving low temperatures, such as lower thermal isolationcaused by additional conduction through dielectric substrate andpoor film quality, while pyramid design presents technical chal-lenges for MEMS fabrication processes. Here we design a planar,rectangular, six-stage micro TE cooler using n-type Bi2Te3 andp-type Sb2Te3 co-evaporated TE films. A thin, dielectric substrate(SiO2 film) bridging between thermally isolated islands (Si wafer)is unavoidably included to support TE film couples. Due to theirsmall size (in the order of a few hundred microns) and high ther-mal conductivity (Si, 150 W/m K), these islands are assumed tobe isothermal (i.e., isothermal island). A serpentine tether (glass)is also added to hold the thermal isolation structure. The numberof TE couples is the smallest in the last stage (innermost stage),and largest in the first stage (outermost stage) to transport theaccumulated heat from the center outward.

In comparison with the pyramid design, there are four signifi-cant considerations, namely, thermal isolation, thermal isolation/electrical resistance of the TE film (i.e., optimal TE film dimensionaspect ratio including conduction through the substrate andtether), TE film quality, and electrical resistance of inter-connect-ing electrical wires.

The planar design inherently results in extra thermal conduc-tion paths through the substrate and tether, which in turn decrease

ctric cooler: Planar multistage, Int. J. Heat Mass Transfer (2008),

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Nomenclature

ll Ak cross-sectional area of the thermoelectricelement (m2)

Je electrical current (A)k thermal conductivity (W/m K)L length (m)N number of thermoelectric couplesPe electrical power (W)Q heat flow rate (W)Re electrical resistance (X)Rk conduction resistance (K/W)_S energy conversion rate (W)T temperature (K)wte width of thermoelectric element (m)Ze figure of merit (1/K)

Greek symbolsaS Seebeck coefficient (V/K)d thickness (m)rSB Stefan–Boltzmann constantqe electrical resistivity (X-m)

Superscriptsamb ambientb boundaryc cold, contact

e electrical, electronext extrinsich hoti stage, nodeint intrinsicJ Joulek conductionMEMS MEMS devicen n-type thermoelectric element, number of stageopt optimump p-type thermoelectric element or phononP Peltierr radiations stagesub substratete thermoelectric elementtether glass serpentine tetherwire inter-connecting electrical wire

2 G.S. Hwang et al. / International Journal of Heat and Mass Transfer xxx (2008) xxx–xxx

ARTICLE IN PRESS

the thermal isolation from the surroundings. Thus, for the optimaldesign, thermal isolation through those structures should be maxi-mized. In addition, direct exposure of the cooler structure to sur-roundings allows for an increase in radiation, especially for largetemperature difference between the cold stage and the surround-ings. Also, the substrate thickness controls the optimal ratio of ther-mal conduction resistance to electrical resistance. While the optimaldimension aspect ratio of TE couples changes with the substratethickness, it remains constant without the substrate because it isdetermined only by TE film material properties [2]. For co-evapo-rated n-type Bi2Te3 and p-type Sb2Te3 TE films, lower Seebeck coef-ficient and higher electrical resistivity are measured than those ofbulk TE materials [6,14,15]. The thermal conductivity of thin-film,in general, is lower than the bulk value, since large grain boundaryscattering of thin-film hinders phonon transport [16]. For a conser-vative estimate, we use the same thermal conductivity for TE filmsas that of bulk TE materials [6,13]. Thus, the TE figure of merit ofTE films is expected to be lower than that of bulk TE elements, whichin turn decreases cooling performances. Micro sized inter-connect-ing electrical wires also lower cooling capability by increasing Jouleheating and by providing additional thermal paths. A comparisonbetween the planar and pyramid designs is given in Table 1.

In Section 2, we discuss intrinsic (only material) and extrinsic(material and geometry) TE figures of merit for a multistage cooler,and in Section 3, we develop a thermal network model that in-cludes interfacial phenomena. In Section 4, we compare predic-tions with on-going experimental results, and discusses theoptimal planar six-stage design and improvements to reach cool-ing performances of an ideal pyramid design.

Details of MEMS fabrication processes for the planar, multistagemicro cooler are found in [17], and discussions of TE film deposi-tion are also given in [14,15].

2. Thermoelectric figure of merit

The intrinsic (material only) thermoelectric figure of meritincluding both n- and p-type TE materials is defined as [18]

Please cite this article in press as: G.S. Hwang et al., Micro thermoeledoi:10.1016/j.ijheatmasstransfer.2008.10.014

Ze;int �a2

S

ðkqeÞ1=2p þ ðkqeÞ

1=2n

h i2 ; ð1Þ

where aS is the junction Seebeck coefficient (i.e., aS = aS,p � aS,n), k isthe total thermal conductivity which is a sum of phonon kp andelectronic ke thermal conductivity (i.e., k = kp + ke), and qe is theelectrical resistivity.

Including the geometries of the TE couples, dielectric sub-strate, glass tether, and inter-connecting electrical wires, we de-fine the extrinsic (material and geometry) thermoelectric figureof merit as

Ze;ext ¼a2

S

Re=Rk; ð2Þ

where the thermal resistance Rk, and the electrical resistance Re.These are

Rk ¼XNs

i¼1

Rk;i

Re ¼XNs

i¼1

ðRe;te;i þ Re;wire;iÞ

1Rk;i¼ 1

Rk;te;iþ 1

Rk;sub;iþ 1

Rk;tether;i

1Rk;te;i

¼ Ni1

ðRk;teÞpþ 1ðRk;teÞn

" #¼ Ni

Ak;tekLte

� �pþ Ak;tek

Lte

� �n

" #

Re;te;i ¼ NiqeLte

Ak;te

� �p

þ qeLte

Ak;te

� �n

" #: ð3Þ

In Eq. (3), Ns is the number of the stage, Ni is the number of TEcouples in the ith stage, Rk,te,i is the thermal resistance of the TEmaterial at the ith stage, Rk,sub,i the thermal resistance of substrateat the ith stage, Rk,tether,i is the thermal resistance of glass tether atthe ith stage, Re,te,i is the electrical resistance of TE material at theith stage, and Re,wire,i is the electrical resistance of inter-connecting


Stage 1(Hot Stage)

(Electrical Current)

(-)

Stage 1(Hot Stage)

2

34

56 (Cold Stage)

(+)

(-)

(-)

2

23

23

45

3

4

56 (Cold Stage)

eJ

(+) eJ

...

ElectricalConductor

ElectricalConductor

Multistage TE Coolers

Bulk TE Columns

Bulk TE Columns

Vapor DepositedTE Films

Dielectric Film (SiO )

Glass TetheredStructure (SiO )

2

2

High Thermal ConductivityDielectric Material(Ceramic Plate)

High Thermal ConductivityMaterial (Si)

High Thermal ConductivityDielectric Material(Ceramic Plate)

hT

hT

hT

rQ

hT

hT

rQ

rQ

Conduction Through Substrate

Conduction ThroughTE Film

Parasitic Heat Load by Tether Structure

cQ−

cQ−

Joule Heating

Conduction ThroughTE Columns

Radiation FromSurrounding

Peltier Cooling

2 3-type(Sb Te )p

2 3-type(Bi Te )n

2 3-type(Sb Te )p2 3-type(Bi Te )n

2 3-type(Sb Te )p2 3-type(Bi Te )n

Stage 1(Hot Stage)

6 (Cold Stage)

,k tetherQ

,5 ,6c hQ Q− =

,1 ,2c hQ Q− =

,k subQ

,k teQ

...

,5 ,6c hQ Q− =

,1 ,2c hQ Q− =

...

Q Q− =,5 ,6

c,6 c

c hQ Q− =

,1 ,2c hQ Q− =

,k teQ

cT

cQ−

cT

(+)eJ

,k teQ

Q Q− =c,6 c

Q Q− =c,6 c

a

b

c

Fig. 1. Schematics of six-stage TE coolers. (a) Pyramid (three-dimensional) design using bulk TE couples spaced the dielectric stages, (b) pyramid (three-dimensional) designusing bulk TE couples arranged on the periphery, and (c) planar (two-dimensional) design using TE films including a thin substrate and a serpentine glass tether. Thermalconduction and radiation, heat sources/sinks, n- and p-type TE elements, inter-connecting electrical wires, hot, and cold stage temperatures are also shown.

Table 1Comparison between multistage planar and pyramid designs.

Planar Pyramid

Thermal isolation Radiation for the inner stages is not isolated fromsurroundings

Each stage is fully isolated by thin plates, thus preventing radiationfrom penetration

Conduction through TE films and their substrates Conduction only through TE couplesTE couple structure Thin TE films supported by dielectric substrate connecting

stagesSpaced columnar couples filling the space between stages

Material properties and substrate thickness dependentoptimal TE aspect ratio

Only material properties dependent optimal TE aspect ratio

TE element Vapor deposited n-type Bi2Te3, p-type Sb2Te3 [14,15] Bulk n-type Bi2Te3, p-type Sb2 Te3 [3]Resistance of inter- connecting

electrical wiresSignificant Negligible

G.S. Hwang et al. / International Journal of Heat and Mass Transfer xxx (2008) xxx–xxx 3

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Please cite this article in press as: G.S. Hwang et al., Micro thermoelectric cooler: Planar multistage, Int. J. Heat Mass Transfer (2008),doi:10.1016/j.ijheatmasstransfer.2008.10.014

Cold Stage(Cooled MEMS)

Temperature AmbientTemperature

Conduction ThroughTE Film

Substrate

Radiation

Conduction ThroughTether

Isothermal (Stage) Node

Conduction ThroughWire

Conduction ThroughSubstrate

Resistance toheat sink

ContactResistance

Isothermal (Stage)Island

ActiveCooling RateCold Node Hot Node

,k tetherQ

,k subQ

,k tetherR

,k hR

hT

rQ

cQ−

cT,k wireQ

, ,k wire nR

,k cR

, ,k te nR Resistance toheat sink ,k cR

,J( )e wireS

,P ,J( )e e cS S+ ,P ,J( )e e hS S+

Tamb

teL

iL iT

, 1h iT +,c iT

,sub iw

tew

wirew

teδwireδMEMSw

subδ

,r iR

, ,k sub iR

, ,k te iQ

Fig. 2. Thermal circuit diagram for planar multistage micro cooler. It includes Peltier cooling/heaing, Joule heating, thermal conduction, thermal radiation, and interfacialthermal/electrical resistances. Three temperature nodes are marked at the isothermal (stage) node Ti, cold Tc,i and hot Th,i + 1 junctions of TE couples. The cold stagetemperature Tc (cooled MEMS) and ambient (surrounding) temperature Tamb are also shown.


ARTICLE IN PRESS

wires at the ith stage. These resistances are shown in Fig. 2. For anideal pyramid design, no substrate and no tether are allowed, soRk,sub,i ?1, and Rk,tether,i ?1. Also, Re,wire,i ? 0, because the electri-cal resistances of inter-connecting wires are negligibly small.

The thermoelectric figure of merit signifies the efficiency of TEdevices. The active cooling rate Qc at the optimal current Je,opt is gi-ven as [18]

�Q c ¼1Rk

Ze;extT2c

2� ðTh � TcÞ

" #; Je;opt ¼

aSTc

Re: ð4Þ

The maximum temperature difference DTmax, between the hotstage temperature Th and cold stage temperature Tc, for Qc = 0 is[18]

DTmax � ðTh � TcÞmax ¼Ze;extT

2c

2: ð5Þ

To maximize DTmax, large extrinsic thermoelectric figure ofmerit Ze,ext is needed, which is achieved by increasing film qualityZe,int and by optimizing the structure. Discussions on improvingZe,int are found in [14,15,19], and we will optimize the design byimproving the thermal isolation and reducing the electricalresistance.

3. Thermal network model

To elucidate and analyze the multistage TE micro cooler, a ther-mal network model is developed considering the Peltier cooling/heating, Joule heating, thermal conduction, thermal radiation,and temperature dependent TE material properties, as shown inFig. 2. The hot stage temperature Th, [leftmost temperature junc-tion, or outermost temperature junction in Fig. 1(c)] which is ex-posed to the ambient temperature Tamb, is thermally andelectrically connected by TE couples (including the substrate) withthe next-stage temperature junction Ti. This continues for the sec-ond stage, etc. up to the cold stage temperature Tc [cooled MEMSsite (rightmost), or the innermost stage in Fig. 1(c)].

Peltier cooling/heating, ð _Se;PÞc , ð _Se;PÞh are considered at cold/hotjunctions of each set of TE couple. Thermal conduction resistance,


Rk includes TE couples, thin substrate, tether, inter-connectingelectrical wires as well as thermal boundary/contact resistances.Thermal radiation resistance, Rr consists of radiation exchanges be-tween the surroundings and each stage. Joule heating results fromTE couples, inter-connecting electrical wires, and electrical con-tacts. Detailed discussions concerning the thermal/electricalboundary/contact resistances as an interfacial transport are foundin [20]. Convection is neglected due to ancipated vacuum packag-ing [17].

Under steady-state condition, the energy equation for thermalnode i, as shown in Fig. 2, is [21]

Q jAi¼X

j

_Sj; ð6Þ

where Q jAiis the net heat transfer through the surface Ai, and _Sj is

the nodal energy conversion, which comprises Peltier cooling/heating, or Joule heating. For the temperature node Ti, Eq. (6)becomes

Qc;i � Q h;iþ1 þX

j

Q k;sub;j þX

j

Qk;wire;j þX

j

Q k;tether;j þX

j

Q r;j

¼ ð _Se;JÞwire;i at temperature node Ti; ð7Þ

where Qc,i is the heat transfer at the cold junction of the TE couplesin the ith stage, Qh,i+1 is the heat transfer at the hot junction of theTE couples in the (i + 1)th stage, Qk,sub is the conduction through thesubstrate, Qk,wire is the conduction through the inter-connectingelectrical wires, Qk,tether is the conduction through the tether, Qr isthe radiation exchange with the surroundings, ð _Se;JÞwire;i is the Jouleheating by the inter-connecting electrical wires.

For the hot and cold temperature nodes of TE couples at eachstage Tc,i, Th,i+1, respectively, the energy equations are

�Q c;iþQ k;te;i¼ð _Se;Pþ _Se;JÞc;i at cold node of TE couplesTc;i ð8ÞQh;iþ1þQ k;te;iþ1¼ð _Se;Pþ _Se;JÞh;iþ1 at hot node of TE couplesTh;iþ1; ð9Þ

where Qk,te,i is conduction through the TE couples, _Se;P is the Peltiercooling/heating, and ð _Se;JÞc=h is the Joule heating either at the cold orhot junction of the TE couples. These are



ARTICLE IN PRESS

Qk;te;i ¼ ðTh;i � Tc;iÞRk;te;i

; Q k;sub;i ¼ðTi � Ti�1Þ

Rk;sub;i;

Qk;wire;i ¼ðTi � Ti�1Þ

Rk;wire;i; Qr;i ¼

rSBðT4amb � T4

i ÞRr;i

;

_Se;J ¼12

Re;te;iJ2e;i; ð _Se;PÞc ¼ �aSJe;i; ð _Se;PÞh ¼ aSJe;iþ1;

where Th,i and Tc,i are the temperatures at the hot/cold junctions atthe ith stage, Rk,te,i is the thermal resistance of the TE couples, Rk,sub,i

is the thermal resistance of the substrate, Rk,wire,i is the thermalresistance of the inter-connecting electrical wires, rSB is the Ste-fan–Boltzmann constant, Re,i is the electrical resistance, and Je,i isthe electrical input current in the ith stage.

For the outermost and innermost temperature nodes, the en-ergy equations become

Q h;1 ¼Th � Tamb

Rk;hð10Þ

� Qc;n ¼Tc � Tn

Rk;c¼ �Q c þ

Xj

Q r;n;j � Q k;tether;n; ð11Þ

where Rk,h and Rk,c are the thermal resistances at the hot-end andcold-end heat sinks respectively, and �Qc is the active cooling ratefor MEMS device. The ambient temperature Tamb is set to 300 K, andTh is predicted nearly the same as Tamb.

4. Results and discussions

4.1. Predictions and experimental data

The predictions using the thermal network model are comparedwith the on-going experimental results of a planar, five-stage pro-totype [17] as shown in Fig. 3. The cold stage temperatures andpower consumptions are measured, while varying the electricalcurrent. With a temperature measurement uncertainty of ±5%[17], this cooler produces maximum cooling of D Tmax = 9 K, withthe electrical power consumption of Pe = 12 mW. The predictedelectrical power consumptions and optimal electrical currentwhere the minimum cooling temperature occurs, agree with theexperimental data within the range of uncertainty. Considering ameasurement uncertainty of the substrate thickness and a lack ofmeasurements of k, two estimated values for a substrate thickness

0 1 2 3 4 5 6 7288

289

290

291

292

293

294

295

296

297

298

299

300

Ze,intT@300 K = 0.62, δsub = 1.4 μm,

k = 1.0 W/m-K, ksub = 0.7 W/m-K

Ze,intT@300 K = 0.41, δsub = 1.7 μm,

k = 1.5 W/m-K, ksub = 1.0 W/m-K

Measured Tc Predicted Tc

T c, K

Je , mA

Five-Stage, δte = 1.9 μm, wte = 80 μm,

k = kp + ke,

ke = 0.48 @ 300 K by Wiedemann-Franz Law

0

4

8

12

16

20

24

28

32

36

40

Measured Pe Predicted Pe

Pe,

mW

Fig. 3. Comparison between the predicted and the measured cold stage temper-atures, and power consumptions of a planar five-stage prototype [17]. Thepredictions are for two values of TE film thermal conductivity. The prototypespecifications are also shown.


and a cross-plane thermal conductivity k of TE film are used. With-in a substrate thickness measurement uncertainty, the value of kfitted to Ze,intT (T = 300 K) = 0.62, is k = 1.0 W/m K. The predictedcold stage temperatures Tc show good agreement with the mea-surements. Based on this, in the following analysis, we use themeasured TE film values for aS and qe, along with k fitted to Ze,intT(T = 300 K) = 0.62.

4.2. Optimal design

To achieve the maximum cooling, the extrinsic TE figure of mer-it in Eq. (2) should be maximized. The optimization parametersare:

(a) TE couple dimension aspect ratio (i.e., width of TE elementwte for given length Lte and thickness dte),

(b) electrical current Je,i, and its stage ratio Je,i/Je,i+1, and(c) number of TE couples in the last stage, N6, and ratio of num-

ber of TE couples in adjacent stages, Ni/Ni+1.

For TE couples, the ratio of the cross-section area Ak,te to thelength Lte [Eq. (3)] determines the thermal and electrical resistanceof TE elements. A long element with a small cross-section areaallows for high thermal isolation, while a short element with alarge cross-section area provides a low electrical resistance. Sincethe TE film thickness is limited by co-evaporated depositiontechnique, dte,max 6 10 lm, only its length and width are opti-mized. A similar approach was used in [20]. Here, we use dte = 4 lmwith MEMS cooler device size of wsub = 5500 lm, and optimize TEfilm width wte (given Je,6, Je,i/Je,i+1, N6, and Ni/Ni+1). Fig. 4 showsvariation of Tc with respect to wte for subject to geometric con-straint dimension (packing limit at first stage, N1) for given devicesize (wte,max = 120 lm for wsub = 5500 lm). Tc decreases as wte in-creases, since the larger cross-section area Ate reduces the Jouleheating. The minimum Tc is predicted at wte = 120 lm. Here, weset wte = 120 lm as geometric constraint.

A moderate electrical current favors the Peltier cooling, whileexcessive current results in Joule heating. Note that the optimalelectrical current Je,opt is given in Eq. (4). The electrical current sup-ply can be in series or in parallel for each stage. Even though theparallel arrangement has an advantage in supplying optimal elec-trical currents for each stage, it adds multiple (parallel) thermal

90 100 110 120 130240

260

280

300

320

Geometrical Constraint(Element Packing

Limit for Stage 1, N )1

Optimal Planar Six-Stage, Ze,intT@300K = 0.62δte = 4 μm, Lte = 30 μmN6 = 2, Ni /Ni+1 = 2

T c, K

wte, μm

Tc = 249 K

Fig. 4. Variation of the predicted cold stage temperature of the optimal planar six-stage micro TE cooler, as a function of TE element width wte, using TE film withZe,intT = 0.62. The detailed specifications are found in Tables 2 and 3. Thegeometrical constraint is also marked.



ARTICLE IN PRESS

paths which in turn compromise the thermal isolation. Based onthe thermal network model predictions using such complex elec-trical current supply, the parallel arrangement produces only smallenhancement in the cold stage temperature. A similar prediction isalso found in [1]. Thus, only the serial arrangement is consideredhere (Ji/Ji+1 = 1). Table 2 lists the range of geometric parametersused in the optimization, and Table 3 lists the thermal conductiv-ities, electrical resistances, and surface emissivities used. The tem-perature-dependent TE film properties (fitted) are also given(measured values are reported in [15]).

The number of TE couples of the innermost stage N6, is impor-tant, since it contributes the most to the thermal isolation betweenthe cold stage and surroundings, and Joule heating by the inner-most stage results in heat loads for the lower stages. While using

Table 2Geometrical parameters for the optimal planar six-stage design.

Parameter Description Magnitude

Isothermalislands(Bulk Si)

wMEMS One edge length of MEMS die 1500 lm

Li Width of isothermal island (j = 1, . . . ,6) 250–750 lmdi Thickness of isothermal island

(j = 1, . . . ,6)300 lm

TE films Lte Length of TE couples 30 lmwte,i Width of TE couples in ith 120 lmdte Film thickness of TE couples 4 lm

Number of TEcouples

N6 Number of TE couples in the last(innermost) stage

2

Ni/Ni+ 1

Number ratio of TE couples betweenstages (j = 1, . . . ,5)

2

N1 Number of TE couples in the first(outermost) stage

64

Substrate(SiO2 film)

Lsub Length of thin substrate over stage 30 lm

wsub Width of thin substrate 1,500–5,500 lm

dsub Thickness of thin substrate 1.5 lm

Electrodes Lelec Length of electrode between TE couples 50 lmwelec Width of electrode 100 lmdelec Thickness of electrode 0.5 lm

Wire Lwire Length of electrical wire 1,000–4,000 lm

wwire Width of electrical wire 10–100 lmdwire Thickness of electrical wire 0.5 lm

Table 3Material properties used for the optimal planar six-stage design.

Parameter Description

Thermal properties kte,n Thermal conkte,p Thermal conksub Thermal conkwire Thermal con�1 Emissivity o�2 Emissivity o

Thermal/electrical boundary/contact resistances (AkRk)c Thermal con(AkRe)c Electrical co(AkRk)b,n Total bound(AkRk)b,p Total bound

Resistances to heat sinks Rk,h Thermal resRk,c Thermal res

For temperature-dependent (fitted) aS and qe are (measured values are reported in [15]aS;n ¼ ð�7:715� 0:8607Tavg � 7:535� 10�4T2

avg þ 4:596� 10�6T3avgÞ � 10�6,

aS;p ¼ ð94:91� 0:3018 Tavg þ 3:840� 10�3T2avg � 7:053� 10�6T3

avgÞ � 10�6,qe;n ¼ ð5:740� 0:04166 Tavg þ 4:999� 10�4T2

avg � 6:756� 10�7T3avgÞ � 10�6,

qe;p ¼ ð8:651� 0:01255 Tavg þ 1:505� 10�4T2avg � 1:813� 10�7T3

avgÞ � 10�6,where Tavg = (Tc,i + Th,i)/2.


a large number of TE couples improves Peltier cooling in the inner-most stage, the overall cooling performance diminishes. This is dueto the reduced thermal isolation and increased Joule heating forthe lower stages. Thus, the smallest number of TE couples is desir-able in the innermost stage, and it is predicted that only one TEcouple produces the best performance. However, an even numbershould be used to minimize mechanical (structural) damage fromasymmetric thermal stress [17]. Here, two TE couples are used inthe innermost stage, i.e., N6 = 2. The ratio of TE couples over thestages is also critical to the cooling power because it controls thethermal isolation and total electrical resistance. While a large num-ber ratio yields increased Peltier cooling, it produces decreasedthermal isolation and increased Joule heating. TE couple arrange-ments at each stage should be symmetric to minimize mechanicaldamages from an asymmetric thermal stress. With these consider-ations and the optimization approach mentioned above, the ther-mal network model using conjugate-gradient minimizationpredicts the optimal ratio of the TE couples Ni/Ni+1 = 2, as shownin Fig. 5. It is close to the optimal design structure studied in anideal four-stage cooler [1].

Magnitude

ductivity of n-type TE film [20] 1.0 W/m Kductivity of p-type TE film [20] 1.0 W/m Kductivity of substrate [24] 0.7 W/m Kductivity of electrical gold wire [25] 200 W/m Kf packaging shell [21] 0.1f silicon wafer [21] 0.9

tact resistance [20] 1 � 10�7 K/(W/m2)ntact resistance [17] 4.6 � 10�11 X m2

ary resistance at n-type TE [20] 7.2 � 10�8 K/(W/m2)ary resistance at p-type TE [20] 7.4 � 10�8 K/(W/m2)

istances to an ambient from hot stage [21] 10 K/Wistances to the innermost stage from cold stage [21] 10 K/W

),

1.00 1.25 1.50 1.75 2.00 2.25240

260

280

300

320Optimal Planar Six-Stage, Ze,intT@300K = 0.62

δte = 4 μm, wte = 120 μm, Lte = 30 μm

N6 = 2

T c, K

Tc = 249 K

1i iN N +

Fig. 5. Variation of the predicted cold stage temperature of the optimal planar six-stage micro TE cooler, as a function of the ratio of number of TE couples Ni/Ni + 1,using TE film with Ze,intT = 0.62. Detailed specifications are found in Tables 2 and 3.


Table 5Summary of specifications for improved planar design towards pyramid (optimal)design. The design numbers are those marked in Fig. 8.

Design TE Properties dte, lm dsub, lm Re,wire Re,c,Rk,c Qr

Baseline Planar Film [15] 4 1.5 s s s

Design 1 Bulk [3] 4 1.5 s s s

Design 2 Bulk 15 1.5 s s s

Design 3 Bulk 15 0 s s s

Design 4 Bulk 15 0 � s s

Design 5 Bulk 15 0 � � s

Design 6 Bulk 15 0 � � M

Ideal Pyramid Bulk 15 0 � � M

s existing, � removed, M reduced.

Table 4Geometrical parameters for the commercially available pyramid six-stage macrodesign (Fig. 7).

Parameter Description Magnitude

TE columns Lte Length of TE couples 1.8 mmwte Width of TE square section element 2.0 mm

Number of TE couplesin each stage

N6 Number of TE couples in stage 6 1

N5 Number of TE couples in stage 5 2N4 Number of TE couples in stage 4 4N3 Number of TE couples in stage 3 9N2 Number of TE couples in stage 2 21N1 Number of TE couples in stage 1 49


ARTICLE IN PRESS

The predicted cold stage temperatures and power consump-tions in the optimal planar six-stage TE cooler with respect tothe electrical current are shown in Fig. 6. The optimal designachieves DTmax = 51 K with power consumption of Pe = 68 mW.This prediction is considered as a baseline design for the improve-ments in Section 4.3.

When the cooling rate Qc – 0 [Eq. (4)], the optimal TE cooler de-sign is different from the design for D Tmax. The Qc – 0 decreasesDT because it consumes the Peltier cooling capability, and the re-duced DT allows for lower thermal isolation from the surround-ings. The reduced thermal isolation Rk is beneficial for decreasedJoule heating (due to increased cross-section area of TE elementsi.e., low Re). Thus, from Eq. (4), the optimal design for Qc – 0 re-quires reduced thermal resistance Rk, increased Ze,ext, and mini-mum Th � Tc. The reduced Rk in multistage cooler is obtained byan increase in the number of TE elements of each stage and the en-larged width of each element (for given Ze,ext, and Th � Tc).

4.3. Improvements

The micro planar TE cooler has several inherent disadvantagesdue to film deposition constraints and intrinsic structural require-ments, which are not present in an ideal pyramid design. These are,(a) poorer film quality Ze,int, (b) thinner TE film thickness dte, (c)greater substrate thickness dsub, (d) higher electrical wire resis-tances Re,wire, (e) higher interfacial resistances Rk,c, Re,c, and (f) high-er radiation Qr. The benefits from each sequential thermal/electrical improvements for the above factors (a) to (f) are studiedin the planar six-stage design, and are described by design designa-tions 1–6 as listed in Table 5. The baseline design is the predictedoptimal planar six-stage TE cooler discussed in Section 4.2. Design1 uses bulk TE properties Ze,intT (T = 300 K) = 0.74 [3], and Design 2uses thicker TE film dte ? 15lm, Design 3 remove the substratedsub ? 0. Design 4 eliminates the inter-connecting electrical wireresistances Re,wire ? 0, Design 5 removes thermal/electrical contactresistances Rk,c ? 0, Re,c ? 0, and Design 6 eliminates radiationheat gain Qr ? 0. For the ideal design, the design without any dis-advantages [above (a) to (f)] of the planar design, whose cold stagetemperature is close to that of the commercially available six-stagepyramid macro cooler, is used for comparison and ideally im-proved design.

Using design specifications given in Table 4, and the bulk TE n-type Bi2Te3 and p-type Sb2Te3 with Ze,intT (T = 300 K) = 0.74 [3], the

1 2i iN N + =

0 4 8 12 16 20 24 28 32240

250

260

270

280

290

300

310

Pe = 68 mW

Optimal Planar Six-Stage, Ze,intT@300K = 0.62

δte = 4 μm, wte = 120 μm, Lte = 30 μm

N6 = 2,

T c, K

Je , mA

Tc = 249 K

0

25

50

75

100

125

150

P e, m

W

Fig. 6. Variation of the predicted cold stage temperature and power consumption ofthe optimal planar six-stage micro TE cooler, with respect to electrical current usingTE film with Ze,intT = 0.62. The detailed specifications are found in Table 2 and 3.


cold stage temperature Tc is predicted by thermal network modelas shown in Fig. 7. A DTmax = 127 K is predicted at the optimal elec-trical current Je,opt = 5 A. This is in line with the commercially avail-able units. For the six-stage micro pyramid cooler (described inTable 2) gives a DTmax = 130 K (or Tc = 170 K) for Ze,intT(T = 300 K) = 0.74, and it is considered as the ideal micro pyramiddesign, which is an ideally improved reference design. The reasonfor the better performance of this ideal micro pyramid design byDTc = 3 K is its further optimization of the ratio of number of TEcouples in adjacent stages, Ni+1/Ni as shown in Tables 2 and 4.

Variations of the predicted cold stage temperature, with respectto electrical current, of all the design variations including the base-line and ideal pyramid design are shown in Fig. 8. Design 1 using

(-)

(+)

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5160

180

200

220

240

260

280

300

320

Je,opt = 5 A

Prediction byThermal Network Model

T c , K

Je , A

Six-Stage, Pyramid Macro DesignBulk Bi2Te3 and Sb2Te3, Ze,intT@300 K = 0.74

Specifications are Given in Table 4

Performance Curve ofCommercially Available Module

Fig. 7. Predicted cold stage temperature using the thermal network model for Ze,intT(T = 300 K) = 0.74 [3] of the macro pyramid design. The optimal electrical currentJe,opt = 5 A, is also shown. Detailed specifications are given in Table 4.


0 10 20 30 40160

180

200

220

240

260

280

300

320

ΔT = 12 K

0.62 (Film)

Ze,intT@300K = 0.41 (Film)

0.74 (Bulk)

ΔT = 58 K

ΔT = 20 K

Ideal Pyramid Design

T c, K

Je , mA

Six-Stage, Planar Design

Fig. 9. Variation of the predicted cold stage temperatures for Ze,intT (T = 300 K)values of 0.41 (film using bulk k = 1.5 W/m K) [15], 0.62 (film using fitted filmk = 1.0 W/m K), and 0.74 (bulk) [3], as a function of input current.

0 5 10 15 20 25 30160

180

200

220

240

260

280

300

320

ΔT = 11 K

δsub 0 μm

Without Tethered StructureΔT = 63 K

ΔT = 5 K


δsub 0 μm

With Tethered Structure

δsub = 1.5 μm

With Tethered Structure

T c, K

Je , mA



ARTICLE IN PRESS

bulk TE couples, Ze,intT (T = 300 K) = 0.74, shows further cooling ofDT = 20 K. Design 2 manipulates the denominator in Eq. (2) byincreasing TE film thickness, and it is predicted that dte = 15 lmis the optimal TE thickness which results in further DT = 6 K cool-ing at higher electrical current. The higher optimal input current iscaused by reduction in TE film electrical resistance in Eq. (5). In De-sign 3, it is assumed that the thin SiO2 substrate and the glasstether are removed, and it produces further DT = 14 K. The TE filmquality, thickness, and substrate thickness are critical to coolingperformances, which we will discuss these in the following subsec-tions (A)–(C). Without Joule heating by the electrical wires in De-sign 4, an additional DT = 32 K can be achieved. In Designs 5 and6, the interfacial resistances and radiation are reduced, and the re-sults show that these are not critical parameters. For the furtherimprovement, only one TE couple in the innermost stage will resultin an additional cold stage temperature DT = 4 K. Therefore, if theinherent technical challenges mentioned above are resolved inthe planar design, the maximum temperature difference will be in-creased by nearly 2.6-fold.

(A) Thermoelectric Film Properties Ze,intT: Improved TE film qual-ity enhances cooling performance in a micro TE cooler. The filmproperties are discussed in [13–15]. Fig. 9 shows variation of thepredicted cold stage temperature Tc for Ze,intT (T = 300 K) valuesof 0.41 (film, using bulk k = 1.5 W/m K), 0.62 (film, using fitted filmk = 1.0 W/m K), and 0.74 (bulk) [3]. For Ze,intT = 0.41, DTmax = 39 K ispredicted, and with Ze,intT = 0.62 a further DT = 12 K is calculated.Using Ze,intT = 0.74, improvement of DT = 20 K at an increased opti-mal input current is achieved by decreasing electrical resistance,improving Seebeck coefficient, or decreasing the thermal conduc-tivity. Note that the cooling performance is not proportional toZe,intT which does not include geometries. This is caused by differ-ent contributions of Ze,intT to the thermal and electrical resistancesin Eq. (2) for given geometries. Further improvement in Ze,intTwould be desired (i.e., superlattices [22] or alloys [23]).

(B) Substrate Thickness dsub: Maximizing thermal isolation of thestructure by removing the substrate thickness and tether yieldsimproved cooling performance. Fig. 10 shows that cold stage tem-peratures for substrate thicknesses of 0 and 1.5 lm, and with andwithout thermal resistance of the glass tether, Rk,tether = 15,000 K/W[17] as a function of input current. When the substrate is com-pletely removed dsub ? 0, keeping the glass tether, a further

23

0 10 20 30 40 50 60 70 80 90 100160

180

200

220

240

260

280

300

320

ΔT = 32 KΔT = 20 K

Design 2

Macro PyramidDesign@ Je,opt = 5 A

Thermal Symmetry Requirement

Design 6Design 5

Design 4

Design 3

Baseline Planar Design

Design 1


T c, K

Je , mA

Six-Stage, Planar Micro Design

ΔT = 20 K

Fig. 8. Variation of the cold stage temperature with respect to input current, forbaseline planar design, ideal pyramid design, and the six design designationsdescribed in Table 5. The cold stage temperature of a six-stage macro cooler usingbulk TE elements is also shown at current of 5 A, which is close to that of the idealpyramid design.

Fig. 10. Variation of cold stage temperature for dsub = 0 and 1.5 lm with respect toinput current. The effect of glass tether is also shown.


DT = 11 K is achieved at a similar optimal input current. When, inaddition, the glass tether is removed, an extra DT = 5 K is gainedat a similar optimal input current. This is because the fully sus-pended TE structure maximizes thermal isolation.

(C) Thermoelectric Film Thickness dte: Achieving an optimal ratioof Re to Rk in Eq. (2) by manipulating TE film thickness producesimproved cooling performance. Here we limit the TE film thicknessto dte = 4–15 lm, and use dsub = 1.5 lm for our baseline design.Fig. 11 shows the variations of the cold stage temperature, with re-spect to input current, for dte = 4, 10, 15, and with givendsub = 1.5 lm. Thicker TE films improve cooling performance, anda further D T = 7 K is predicted for dte = 15 lm. Fig. 12 shows thecold stage temperatures as a function of TE film thickness. The coldstage temperatures increase sharply as the TE film thickness is re-duced, and then reach the asymptotic cold stage temperature forlarge dte, where conduction through the substrate is negligiblecompared to that through the TE film. As the substrate thicknessdecreases, the cold stage temperature is also reduced and it resultsin DT = 12 K, when the substrate is completely removed. A de-creased substrate thickness results in a thinner asymptotic TE film


0 10 20 30 40 50 60 70 80160

180

200

220

240

260

280

300

320

10 μm

ΔT = 71 K

ΔT = 7 K


15 μmδte = 4 μm

T c, K

Je , mA


Fig. 11. Variation of cold stage temperature with respect to input current for dte = 4,10, 15 lm, and with given dsub = 1.5 lm.

0 2 4 6 8 10 12 14 16 18 20220

230

240

250

260

270

280

290

300

310

320

ΔT = 12 K

0 μm

0.5 μm

Six-Stage, Planar DesignTc at Je,opt

T c, K

δte , μm

δsub = 1.5 μm

Fig. 12. Variation of cold stage temperature with respect to TE film thicknesses fordsub = 0, 0.5 and 1.5 lm. For dsub = 0, the glass tether is also removed. Other designparameters are kept the same as the baseline planar design.

Table 6Significance of material-geometry selections on Seebeck coefficient, thermal conduc-tivity, electrical resistivity, and electrical and thermal resistances.

aS k(Rk,te) Rk,sub Rk,tether qe(Re,te) Re,wire

(a) Figure of Merit Ze,intT s s s

(b) TE film geometry s s

(c) Substrate and tether s s

(d) Electrical Wires s


ARTICLE IN PRESS

thickness, which indicates optimal TE film thickness decreaseswhen we can remove the substrate.

5. Conclusions

A planar six-stage micro TE cooler is designed for cooling to lowtemperatures under vacuum, and a thermal network model isdeveloped to investigate the optimal cooling performance consid-ering interfacial thermal/electrical transport and temperature-dependent TE material properties. With the measured TE film


properties, Ze,intT (T = 300 K) = 0.62 and the current fabrication con-straints, the optimal six-stage micro TE cooler design predictsDTmax = 51 K with a power consumption of 68 mW, while the pre-dicted performance of the five-stage prototype agrees well withthe on-going experimental results.

The performance is influenced by (a) TE film quality Ze,intT (fig-ure of merit), i.e., high aS, low k, and low qe, (b) optimal TE filmstructure Rk,te and Re,te), (c) maximum thermal isolation of the sub-strate structure Rk,sub and tether structure Rk,tether, and (d) mini-mum electrical resistance of wires Re,wire. These criticality of eachparameter is summarized in Table 6.

Further improvements can be achieved by

(a) improving TE film quality Ze,intT (using supperlattice [22], oralloy/doping [23]),

(b) optimizing TE film geometry (i.e., aspect ratio, Section 4.2),(c) increasing thermal isolation of substrate (i.e., removing the

substrate and tether [17]),(d) minimizing inter-connecting electrical wires, (e.g., using

high electrical conductive material Au, Ni, Al, or largecross-section area [17]).

The interfacial effects and radiation gains show minor effects.Without the inherent disadvantages of the planar micro TE cooler,the maximum temperature difference will be increased by nearly2.6-fold.

Acknowledgement

This project is supported by the MCC program of DARPA underGrant No. W31P4Q-06-1-001.

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International Journal of Heat and Mass Transferkaviany/researchtopics/gshwang08MTE.pdfthe thermal isolation from the surroundings. Thus, for the optimal design, thermal isolation through

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