Improved Boundary Scan Design (Based on a paper by Lee Whetsel, Texas Instruments Inc.)

Improved Boundary Scan Design

(Based on a paper by Lee Whetsel, Texas Instruments Inc.)

Introduction

In a situation of which the circuit complexity increases, and no direct access for all places on the board is possible, the use of BS is a good alternative.

There are many advantages of using BS

for testing purposes.

The problem:

Two possible drawbacks concerning the use of BS:

1. Additional space is needed for the BS cells.

2. Signaling delay due to additional circuit components.

The proposed solution:

An innovative method of improving the design of the BS cells.

The method is based on the reuse of functional input/output buffers already in the circuit.

The method is compliant with IEEE 1149.1.

Advantages of the method:

The results of the method:Reduced cell size.Reduced signaling delay.Improved test functionality.

The Method

Traditional 1149.1-

2-state output BSC:

Traditional 1149.1-

2-state output BSC:

Normal operation:Test operation:

For self test

improved 2-state output BSC

Implement Mux2

Implements Mem2

improved 2-state output BSC Cont.

Normal operation:closed

opened

Test control signals

improved 2-state output BSC Cont.

Test operation:

opened

Closed after eachCapture/shiftObservability of output pin state

(improve EXTEST operation and enables pin observation via scan

during production testing)

New feature:

Comparing the two designs:

Reduction in BSC circuitry of approximately 40% over the standard BS 2-state output cell. If S1 and S2 are implemented in the buffer region with the LOB a reduction of about 50% will be achieved.

Improved performance – if S1 implemented as high performance transmission gate, the prop. delay through S1 to LOB is less than that of a core resident Mux2 driving a normal output buffer.

Traditional IEEE 1149.1 3-state output BSC

Normal operation:Test operation:

Improved 3-State Output BSC

2-state output BSC

Used in test mode(to maintain updated test data to the control input of the 3SOB)

Improved 3-State Output BSC

Normal Operation: closed

openedCan capture and shift data

Test operation:

Comparing the two designs:

The reduction in BSC circuitry is slightly less than before since the BH is added.

We still get a reduction in the range of approximately 35% - 45%

Traditional IEEE 1149.1 Input BSC

Adds test circuitry and delays the input signal

Improved input BSC

Normal operation:

closed

opened

Test operation:

opened

Important advantage:

Direct access No need for hi-drive bufferLess space and signal delay

Comparing the two designs:

Since there is no need for hi-drive buffer in the improved design, the expected reduction in circuitry is approximately

45% - 55%.

Improved Input/Output BSC

Comparing the two designs:

The input/output BSC improved design gives the best opportunity to reduce overhead circuitry, since BSCs for input, output and control are involved.

The reduction in the cell size is by three Mux2s, three Mem2s and a hi-drive buffer per I/O pin or approximately

45% - 55%.

TAP Controller of Improved BSCs

Conclusion:

The method described here has the following features:

It gives the opportunity to reduce circuitry of BSCs by up to one half by reuse of functional input and output buffers.

It reduces signaling delays due to the use of S1.