Impact of Advanced Electronics for DoD Today Dr. Jay Lewis, Deputy Director DARPA Microsystems Technology Office (MTO) Electronics Resurgence Initiative Workshop – Day 2 July 19, 2017 Reference herein to any specific commercial product, process, or service by trade name, trademark or other trade name, manufacturer or otherwise, does not necessarily constitute or imply endorsement by DARPA, the Defense Department or the U.S. government, and shall not be used for advertising or product endorsement purposes. DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.
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Impact of Advanced Electronics for DoD Today
Dr. Jay Lewis, Deputy DirectorDARPA Microsystems Technology Office (MTO)
Electronics Resurgence Initiative Workshop – Day 2July 19, 2017
Reference herein to any specific commercial product, process, or service by trade name, trademark or other trade name, manufacturer or otherwise, does not necessarily constitute or imply endorsement by
DARPA, the Defense Department or the U.S. government, and shall not be used for advertising or product endorsement purposes.
DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.
Leading-edge ASICs under development in MTO programs could deliver revolutionary capabilities to the warfighter
CLASS Disguise and dynamically vary signals for inexpensive LPI/LPD comms
SHIELD Verify the authenticity of components at every point in the supply chain
CLASIC Distinguish and classify RF signals for 180 hours on a cellphone battery
Enable real-time machine learning for object recognition on UAVs
DAHI 10x higher dynamic range arbitrary waveform generator for RF applications
ACT** Capture unprecedented volumes of RF data at 64Gs/sec for next-gen arrays
ReImagine Collect different data in a single camera frame with a reconfigurable ROIC
RF-FPGA A software-defined front end that works for 20GHz or below
Build trusted circuits through split integration
DISTRIBUTION A. Approved for public release: distribution unlimited.
ASIC – application specific integrated circuit RF – radio frequency
Example ASIC* Capability
ROIC – readout ICLPI/LPD – low probability of intercept/detection
*ASICs from MTO programs
SPADE
UPSIDE
**Program acronyms are later slide
Leading-edge ASICs under development in MTO programs could deliver revolutionary capabilities to the warfighter
CLASS Disguise and dynamically vary signals for inexpensive LPI/LPD comms
SHIELD Verify the authenticity of components at every point in the supply chain
CLASIC Distinguish and classify RF signals for 180 hours on a cellphone battery
Enable real-time machine learning for object recognition on UAVs
DAHI 10x higher dynamic range arbitrary waveform generator for RF applications
ACT** Capture unprecedented volumes of RF data at 64Gs/sec for next-gen arrays
ReImagine Collect different data in a single camera frame with a reconfigurable ROIC
RF-FPGA A software-defined front end that works for 20GHz or below
Build trusted circuits through split integration
DISTRIBUTION A. Approved for public release: distribution unlimited.
ASIC – application specific integrated circuit RF – radio frequency
Example ASIC* Capability
ROIC – readout ICLPI/LPD – low probability of intercept/detection
*ASICs from MTO programs
SPADE
UPSIDE
**Program acronyms on later slide
Leading-edge ASICs under development in MTO programs could deliver revolutionary capabilities to the warfighter
CLASS Disguise and dynamically vary signals for inexpensive LPI/LPD comms
SHIELD Verify the authenticity of components at every point in the supply chain
CLASIC Distinguish and classify RF signals for 180 hours on a cellphone battery
UPSIDE Enable real-time machine learning for object recognition on UAVs
DAHI 10x higher dynamic range arbitrary waveform generator for RF applications
ACT Capture unprecedented volumes of RF data at 64Gs/sec for next-gen arrays
ReImagine Collect different data in a single camera frame with a reconfigurable ROIC
RF-FPGA A software-defined front end that works for 20GHz or below
SPADE Build trusted circuits through split integration
DISTRIBUTION A. Approved for public release: distribution unlimited.
ASIC – application specific integrated circuitRF – radio frequency
Example ASIC* Capability
ROIC – readout ICLPI/LPD – low probability of intercept/detection*ASICs from MTO programs
6.8m
m
6.5mm
5mm
4mm
Area: 44.2mm2
50% Less Area: 20mm2
40% Less Power
32nm 14nm
ACT
• Enable digital re-use forphased arrays
• Capture unprecedentedvolumes of RF data at 64Gs/sec for next-gen arrays
• Leverage the world’s best digital beamforming system
32nm SOI vs. 14nm FinFet
Leading-edge ASICs under development in MTO programs could deliver revolutionary capabilities to the warfighter
CLASS Disguise and dynamically vary signals for inexpensive LPI/LPD comms
SHIELD Verify the authenticity of components at every point in the supply chain
CLASIC Distinguish and classify RF signals for 180 hours on a cellphone battery
UPSIDE Enable real-time machine learning for object recognition on UAVs
DAHI 10x higher dynamic range arbitrary waveform generator for RF applications
ACT Capture unprecedented volumes of RF data at 64Gs/sec for next-gen arrays
ReImagine Collect different data in a single camera frame with a reconfigurable ROIC
RF-FPGA A software-defined front end that works for 20GHz or below
SPADE Build trusted circuits through split integration
DISTRIBUTION A. Approved for public release: distribution unlimited.
ASIC – application specific integrated circuitRF – radio frequency
Example ASIC* Capability
ROIC – readout ICLPI/LPD – low probability of intercept/detection*ASICs from MTO programs
SHIELD
• Ensure the authenticityof genuine military electronic components
• Tag electronics at low cost with an encrypted 100µm x 100µm ASIC
• Personalization of millions of die at wafer-scale
14nm FinFet
Full AES encryption~30 µm x 30 µm
100
µm
100 µm
MicroscopicSHIELD dielet
Leading-edge ASICs under development in MTO programs could deliver revolutionary capabilities to the warfighter
CLASS Disguise and dynamically vary signals for inexpensive LPI/LPD comms
SHIELD Verify the authenticity of components at every point in the supply chain
CLASIC Distinguish and classify RF signals for 180 hours on a cellphone battery
UPSIDE Enable real-time machine learning for object recognition on UAVs
DAHI 10x higher dynamic range arbitrary waveform generator for RF applications
ACT Capture unprecedented volumes of RF data at 64Gs/sec for next-gen arrays
ReImagine Collect different data in a single camera frame with a reconfigurable ROIC
RF-FPGA A software-defined front end that works for 20GHz or below
SPADE Build trusted circuits through split integration
DISTRIBUTION A. Approved for public release: distribution unlimited.
ASIC – application specific integrated circuitRF – radio frequency
Example ASIC* Capability
ROIC – readout ICLPI/LPD – low probability of intercept/detection*ASICs from MTO programs
25 µm
SOA digital ROIC pixel
layout using 65 nm CMOS
14 nm CMOS pixel with
computation
~10 µm
~6
µmImages courtesy: MIT Lincoln Laboratory
ReImagine
• Achieve full battlespaceawareness with a single reconfigurable ROIC
• Simultaneously collect diverse data types from multiple regions of interest
• ADC with signalprocessing in every pixel
14nm CMOS
Program Names
CLASS Computational Leverage Against Surveillance Systems
SHIELD Supply Chain Hardware Integrity for Electronics Defense
CLASIC Cognitive radio Low-energy signal Analysis Sensor Integrated Circuits
UPSIDE Unconventional Processing of Signals for Intelligent Data Exploitation
DAHI Dense Accessible Heterogeneous Integration
ACT Arrays at Commercial Timescales
ReImagine Reconfigurable Imaging
RF-FPGA Radio Frequency – Field Programmable Gate Array
DISTRIBUTION A. Approved for public release: distribution unlimited.
DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.
Ongoing FY18 Programs in AdvancedComputing and Design
Dr. William Chappell, DirectorDARPA Microsystems Technology Office (MTO)
Electronics Resurgence Initiative Workshop – Day 2July 19, 2017
Reference herein to any specific commercial product, process, or service by trade name, trademark or other trade name, manufacturer or otherwise, does not necessarily constitute or imply endorsement by
DARPA, the Defense Department or the U.S. government, and shall not be used for advertising or product endorsement purposes.
DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.
$141 million in Current Efforts (FY18)
$75 millionOf New Funding
(FY18)
$216 MILLION TOTAL (FY18)
DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.
materials architectures designs
JUMP + Traditional Programs
NATIONAL ELECTRONICS CAPABILITY
2025 - 2030
materials architectures designs• JUMP – Joint University Microelectronics Program
• CHIPS – Common Heterogeneous Integration and IP Reuse Strategies
• HIVE – Hierarchical Identify Verify Exploit
• L2M – Lifelong Learning Machines
• N-ZERO - Near-Zero Power Radio Frequency Receivers
• CRAFT – Circuit Realization at Faster Time Scales
• SSITH – System Security Integrated Through Hardware and firmware
Traditional Programs Currently Funded
JUMP + Traditional Programs
DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.
8/22/2016JUMP
Approved
MTO Electronics Timeline
4/2017HIVE
Kickoff
DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.
4/2016CRAFT Kickoff
1/2017L2M
Approved
11/2015
N-ZEROKickoff
2016 2017 2018 2019
Today
4/2017SSITH
BAA Released
6/2016CHIPS
Approved
• Ultra Low Power Design
• Reduced Design Time
• Pseudolithic Design
• Broad University Support
• In Field Machine Learning
• Graph Processing
• Built in Security
Joint University Microelectronics Program(JUMP)
RF to THz Distributed Computing
Cognitive Computing
IntelligentMemory/Storage
Advanced IC Architectures
Devices/Materials
Industry
40% 60%
DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.
Joint University Microelectronics Program (JUMP)
Predecessor Program STARnet
• 646 Graduate students
• 184 Faculty researchers
• 46 Universities
• 6,118 Research publications
Circuit Realization at Faster Time Scales (CRAFT)
Driving a design methodology that can be used to quickly design flexible, high
performance custom integrated circuits using leading-edge CMOS technology while
driving DoD to use the best commercial fabrication and design practices
Sharply reduce barriers to DoD use of leading-edge custom integrated circuits (ICs) for orders-of-magnitude higher performance
at low power for DoD systems.
DoD (Today)
CRAFT(Future)
Chip Design and Fabrication Time (weeks)
DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.
N-ZERO passive sensor wake-up
Devices are off (zero power consumption) yet continually alert.
10000
1000
100
10
10.01 0.1 1.0 10 100
Unattended Ground Sensors
1 mo.
1 yr.
10 yrs.
Life
time
(Day
s)
Event Activity (% of Time)
Battery leakage, active processing and
N-ZERO wake-up
Battery drainage by active wake-
up circuitry
• Continuous operation and near-zero power processing• Persistent sensing with greatly extended lifetime and reduced cost• Multiple sensing modalities with sensor fusion
DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.
Acoustic Sensor Wake-up
Wake-up to generator and truck at > 5m with 12 nW of power consumptionS. Jeong, et al. "21.6 A 12nW always-on acoustic sensing and object recognition microsystem using frequency-domain feature extraction and SVM classification." Solid-State Circuits Conference (ISSCC), 2017 IEEE International. IEEE, 2017.
Acoustic Signal
Sound of Interest+
Noise
Identify
DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.
Hierarchical identify Verify Exploit (HIVE)
Enabling the DoD to perform graph analytics at the edge of the battlefield and not rely on datacenters back in the United
States; providing greater situational awareness in addition to the ability to do
real time sensor fusion and exploitation at the lowest echelons
Next-generation server processor designed to find patterns in streaming data sets by using graph analytics
DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.
HIVE: An example of blending commercial and DoD interests
CUDA – compute unified device architectureTPU – tensor processing unitGPU – graphics processing unit
TA 3:Evaluator (evaluation framework 100-1000x improvement)
TA 1: Graph analytics accelerator(ref: TPU, GPU)
TA 2:Graph analytics toolkits (ref: Tensorflow, CUDA)
Graph Software
What should be accelerated?
GraphHardware
How should it be accelerated?
Define graph primitives
Create data format model
Define data flow model
Identify/Develop hardware
accelerators for each building block
Create memorycontroller which optimizes data
movement based on sparse mapping
Develop busarchitectures
to avoid congestion in
data movement
Accelerators Memory Scaling
Cyber security
NorthropGrumman
Georgia TechPacific Northwest
Intel
Qualcomm
DISTRIBUTION A. Approved for public release: distribution unlimited.
Lifelong Learning Machines (L2M)
Pursuing approaches for biologically-inspired artificial intelligence utilizing
flexible models to continue adapting during execution in the field
Continual Learning
Mechanisms
Fundamentally new machine learning mechanisms for machines that learn continuously as they operate
DISTRIBUTION STATEMENT A. Approved for public release. Distribution is unlimited.
Cortical Processor results
DISTRIBUTION A. Approved for public release: distribution unlimited.
Adaptive Architectures
Results • Found optimal result278x faster than gridsearch method*
• Slightly higheraccuracy than thehand designed(Neverova et.al. 2015)*12 iterations vs ~3300
System modifies architecture via hyper-parameters and finds best