Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter 9 Memory Organization.

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Chapter 9Chapter 9Memory OrganizationMemory Organization


Chapter OutlineChapter Outline

• Hierarchical Memory SystemsHierarchical Memory Systems

• Cache MemoryCache Memory

• Virtual MemoryVirtual Memory

• Pentium/Windows Memory SystemPentium/Windows Memory System


Memory HierarchyMemory Hierarchy


Associative MemoryAssociative Memory

• Data RegisterData Register




• Mask RegisterMask Register




• Mask RegisterMask Register

• Match RegisterMatch Register




Associative CacheAssociative Cache


Data Lines/BlocksData Lines/Blocks

• Multiple consecutive words form a lineMultiple consecutive words form a line




• All data in a line is moved togetherAll data in a line is moved together




• All data in a line is moved togetherAll data in a line is moved together

• Takes advantage of locality of referenceTakes advantage of locality of reference


Associative Cache with a Line Associative Cache with a Line Size of 4 BytesSize of 4 Bytes


Direct Mapped CacheDirect Mapped Cache


Direct Mapped Cache with a Direct Mapped Cache with a Line Size of 4 BytesLine Size of 4 Bytes


Drawbacks of Direct Mapped Drawbacks of Direct Mapped CacheCache

0000 0000 0000 0000: JUMP 1000H0000 0000 0000 0000: JUMP 1000H

0001 0000 0000 0000: JUMP 0000H0001 0000 0000 0000: JUMP 0000H


Set-Associative CacheSet-Associative Cache


Set-Associative Cache with a Set-Associative Cache with a Line Size of 4 BytesLine Size of 4 Bytes


Data Replacement PoliciesData Replacement Policies

• FIFOFIFO



• FIFOFIFO

• LRULRU



• FIFOFIFO

• LRULRU

• RandomRandom


ExampleExample


ExampleExample


ExampleExample


ExampleExample


Writing Data to CacheWriting Data to Cache

• Write backWrite back

• Write throughWrite through

• Write allocateWrite allocate

• Write no-allocateWrite no-allocate


Cache PerformanceCache Performance

• Hits and missesHits and misses




• Hit ratioHit ratio




• Hit ratioHit ratio

• Average memory access timeAverage memory access time


Cache Activity - Associative Cache Activity - Associative CacheCache

0 0 2 0 1 0 4 5 0 2 1 0 3 2 7 6 0 0A B C A D B E F A C D B G C H I A B


Cache Activity - Associative Cache Activity - Associative CacheCache



Cache Activity - Direct Cache Activity - Direct Mapped CacheMapped Cache



Cache Activity - Direct Cache Activity - Direct Mapped CacheMapped Cache



Cache Activity - 2-Way Set-Cache Activity - 2-Way Set-Associative CacheAssociative Cache



Cache Activity - 2-Way Set-Cache Activity - 2-Way Set-Associative CacheAssociative Cache



2-Way Set-Associative Cache 2-Way Set-Associative Cache with a Line Size of 2with a Line Size of 2



2-Way Set-Associative Cache 2-Way Set-Associative Cache with a Line Size of 2with a Line Size of 2



Virtual MemoryVirtual Memory

• Memory Management Unit (MMU)Memory Management Unit (MMU)




• Swap disk/fileSwap disk/file





• Logical addressLogical address





• Logical addressLogical address

• Physical addressPhysical address


Paging - Pages and FramesPaging - Pages and Frames


MMU ConfigurationMMU Configuration


Page TablePage Table


Address ConversionAddress Conversion


Translation Lookaside BufferTranslation Lookaside Buffer


ExampleExample


ExampleExample


SegmentationSegmentation


FragmentationFragmentation• Internal fragmentationInternal fragmentation



• External fragmentationExternal fragmentation



• External fragmentationExternal fragmentation


Beyond the BasicsBeyond the Basics

• Split cacheSplit cache


Beyond the BasicsBeyond the Basics

• Split cacheSplit cache

• Multilevel page tableMultilevel page table


Multilevel Page TableMultilevel Page Table


Pentium/Windows NT Memory Pentium/Windows NT Memory ManagementManagement

8 KB

8 KB


Pentium/Windows NT Cache Pentium/Windows NT Cache Memory ManagementMemory Management

• 16KB L1 split cache16KB L1 split cache– 2-way set-associative2-way set-associative– Line size of 32 bytesLine size of 32 bytes

• TLB used for cache and virtual memoryTLB used for cache and virtual memory

• Pseudo-LRU replacement policyPseudo-LRU replacement policy

• 256K L2 unified cache256K L2 unified cache– 4-way set-associative4-way set-associative


Pentium/Windows NT Virtual Pentium/Windows NT Virtual Memory ManagementMemory Management

• 4 GB address space4 GB address space– Low-order 2 GB for individual processesLow-order 2 GB for individual processes– High-order 2 GB for Windows NT High-order 2 GB for Windows NT

componentscomponents

• Uses paging, not segmentationUses paging, not segmentation• 10-bit page directory pointer + 10-bit 10-bit page directory pointer + 10-bit

offsetoffset• Uses the same TLBs as cache memoryUses the same TLBs as cache memory


SummarySummary

• Hierarchical Memory SystemsHierarchical Memory Systems

• Cache MemoryCache Memory

• Virtual MemoryVirtual Memory

• Pentium/Windows Memory SystemPentium/Windows Memory System

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter 9 Memory Organization.

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