Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter 5 Register Transfer Languages.

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001

Chapter 5Chapter 5Register Transfer LanguagesRegister Transfer Languages


Chapter OutlineChapter Outline

• Micro-operationsMicro-operations

• RTLRTL

• RTL specificationsRTL specifications

• Realizing RTL specificationsRealizing RTL specifications

• VHDLVHDL


Micro-operationsMicro-operations

• Specify data transferSpecify data transfer

• Do not specify conditions under which Do not specify conditions under which transfers occurtransfers occur

• Do not specify hardware implementationDo not specify hardware implementation


Example: X Example: X Y Y

X


Register Transfer LanguageRegister Transfer Language

• Specify micro-operations and when they Specify micro-operations and when they occuroccur

• Format:Format: conditionsconditions: : micro-operationsmicro-operations


Example: Example: αα: X : X Y Y

X


Simultaneous Data TransfersSimultaneous Data Transfersαα: X : X Y, Y Y, Y Z Z

Q D


Invalid Simultaneous TransfersInvalid Simultaneous Transfers

αα: X : X Y, X Y, X Z Z


Loading Constant Values into Loading Constant Values into RegistersRegisters

αα: X : X 0 0

ββ: X : X 1 1


Making Transfers Mutually Making Transfers Mutually ExclusiveExclusive


Multi-bit Data TransfersMulti-bit Data Transfersαα: X : X Y Y


Bit and Bit-range TransfersBit and Bit-range Transfers


Arithmetic and Logical Micro-Arithmetic and Logical Micro-operationsoperations


Shift Micro-operationsShift Micro-operations


Specifying Digital Specifying Digital Components: D Flip-FlopComponents: D Flip-Flop


Specifying Digital Components: Specifying Digital Components: JK Flip-FlopJK Flip-Flop


Specifying Digital Components: Specifying Digital Components: Left Shift RegisterLeft Shift Register


Specifying Simple SystemsSpecifying Simple Systems


System Implementation – Data System Implementation – Data PathsPaths


System Implementation – Data System Implementation – Data Paths and ControlPaths and Control


System Implementation Using a System Implementation Using a Bus and 3-State BuffersBus and 3-State Buffers


System Implementation Using System Implementation Using a Bus and a Multiplexera Bus and a Multiplexer

n o j


Modulo 6 CounterModulo 6 Counter

• Counts up when U = 1Counts up when U = 1

• Count sequence: 000 Count sequence: 000 001 001 010 010 011 011 100 100 101 101 000 … 000 …

• V is 3-bit output = count valueV is 3-bit output = count value

• C is 1-bit output = 1 when V = 000C is 1-bit output = 1 when V = 000


Modulo 6 CounterModulo 6 Counter State Table State Table

1 1 11 1 1


Modulo 6 CounterModulo 6 Counter State Diagram State Diagram


Modulo 6 CounterModulo 6 Counter RTL RTL SpecificationSpecification


Modulo 6 CounterModulo 6 Counter System System ImplementationImplementation


Modulo 6 CounterModulo 6 Counter Another Another System ImplementationSystem Implementation


Toll Booth ControllerToll Booth Controller

• C = 1 when car is at toll boothC = 1 when car is at toll booth

• I[1..0] indicates coin inputI[1..0] indicates coin input

• Outputs R, G, A:Outputs R, G, A:– Car in toll booth, toll not fully paid: R = 1Car in toll booth, toll not fully paid: R = 1– Toll paid: G = 1Toll paid: G = 1– Car left without paying full toll: R = 1, A = 1Car left without paying full toll: R = 1, A = 1


Toll Booth Controller StatesToll Booth Controller States


Toll Booth Controller State TableToll Booth Controller State Table


Toll Booth Controller State DiagramToll Booth Controller State Diagram


Toll Booth Controller State Toll Booth Controller State AssignmentsAssignments


Converting State Transitions Converting State Transitions to RTL Codeto RTL Code


Converting State Transitions to Converting State Transitions to RTL CodeRTL Code


Toll Booth Controller RTL Toll Booth Controller RTL Specification (excluding outputs)Specification (excluding outputs)


Toll Booth Controller RTL Toll Booth Controller RTL Specification (outputs)Specification (outputs)


VHDL – VHSIC Hardware VHDL – VHSIC Hardware Description LanguageDescription Language

• Formal syntax – portableFormal syntax – portable

• Platform independentPlatform independent

• Design for PLDs, ASICs, or custom Design for PLDs, ASICs, or custom chipschips

• Simulate designsSimulate designs

• Different levels of abstractionDifferent levels of abstraction


VHDL Design StructureVHDL Design Structure

• Library sectionLibrary section

• Entity sectionEntity section

• Architecture sectionArchitecture section


VHDL Library SectionVHDL Library Section

library IEEE;library IEEE;

use IEEE.std_logic_1164.all;use IEEE.std_logic_1164.all;


VHDL Entity SectionVHDL Entity Section


VHDL Architecture SectionVHDL Architecture Section


VHDL – High Level of VHDL – High Level of AbstractionAbstraction

• Modulo 6 counterModulo 6 counter

• Designed as a state machineDesigned as a state machine


Modulo 6 Counter – Library Modulo 6 Counter – Library and Entity Sectionsand Entity Sections


Modulo 6 Counter – One StateModulo 6 Counter – One State


Architecture Section – State Architecture Section – State GenerationGeneration


Architecture Section – State Architecture Section – State Generation (continued)Generation (continued)


Architecture Section – State Architecture Section – State TransitionTransition


VHDL – Low Level of AbstractionVHDL – Low Level of Abstraction


VHDL – Advanced VHDL – Advanced CapabilitiesCapabilities

• ComponentsComponents

• TimingTiming

• SimulationSimulation


SummarySummary

• Micro-operationsMicro-operations

• RTLRTL

• RTL specificationsRTL specifications

• Realizing RTL specificationsRealizing RTL specifications

• VHDLVHDL

Images courtesy of Addison Wesley Longman, Inc. Copyright © 2001 Chapter 5 Register Transfer Languages.

Documents

x y slide

x y x slide

control slide

exclusive slide

x z slide

range transfers slide

hardware implementation

d flipflop slide