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For general informations about the In-Circuit Debugger refer to the “ICE User’s Guide” (ice_user.pdf). All general commands are described in “PowerView Command Reference” (ide_ref.pdf) and “General Commands and Functions”.
Ready to run setup files for most standard compilers can be found on the software CD in the directory …/Demo/M68K/Compiler. All setup files are designed to run the emulator stand alone without target hardware.
The following description should make the initial setup (to run the emulator together with the target hardware) easier. It describes a typical setup with frequently used settings. It is recommended to use the programming language PRACTICE to create a batch file, which includes all necessary setup commands. PRACTICE files (*.cmm) can be created with the PRACTICE editor pedit (Command: PEDIT <file name>) or with any other text editor.
A basic setup file includes the following parts:
1. Set system options
2. Select dual port mode (optional)
3. Set mapper (optional)
4. Select frequency (optional)
5. Activate the emulator
6. Load application file (optional)
7. Initialize registers and chipselect units (optional)
8. Set breakpoints (optional)
9. Start application
10. Stop application (optional)
For the first step we will describe an example which requires a minimum of special emulator settings. This is a “best case” setting. Later we will describe a ”worst case” setting.
• uses all port E control lines (AS-, DS-, SIZ, DTACK)
• uses BR-, BG- and BGACK- line
• uses a clock generator
1. Set system options
The system window controls the CPU specific setup. Please check this window very carefully and set
the appropriate options. Use the button in the main tool bar and click to the option check box (Command: HELP.PICK) to get online help in a pop up window.
2. Select dualport modes (optional)
Dualport allows access to emulation RAM, while emulation is running. This is necessary to display variables, set breakpoints or display the flag listings while the emulation is running. System.access selects how dualport access is done.
system.downsystem.resetsystem.option v33 onsystem.line modclk on
; switch the system down; all system settings to default; on: if 3.3 V module is used; select target clock configuration
system.access request ; request: BR-/BG- line is used; for dualport
The mapper controls the memory access of the CPU. This means the use of internal or external memory, the number of wait states, the bus width etc.
4. Select frequency (optional)
The CPU can be clocked by internal (emulator) or external (target). If the internal clock is used, the clock is provides by the VCO of the emulator. The setting of the internal clock is done by the VCO command.
The current CPU frequency can be displayed in the counter window (Command: Count).
5. Activate the emulator
When the emulator is activated the Background-Debug-Mode interface of the CPU is initialized. This interface allows access to user memory (data.dump, data.list) and registers and gives control to start and stop the emulation.
6. Load application file (optional)
Application can be loaded by various file formats. For information about the load command for your compiler see Compiler.
7. Initialize registers and chipselect units (optional)
For correct data.list and data.dump after RESET it could be necessary to initialize chipselect units. This can be done in the PERipheral window or by data.set commands to the chipselect registers. Stackpointer and program counter should be initialized by hand if debugging is started at RESET until it is initialized by the program. Stack is used for the emulator break system.
8. Set breakpoints (optional)
There are several ways to set breakpoints (Command: Break.Set). Breakpoints can be displayed using the Break.List command. Information regarding HLL lines (for HLL breakpoints) is loaded automatically when a HLL file is loaded.
9. Start application
Application can be started with giving a break address. For example “go main” starts the application and stops at symbol main.
10. Stop application (optional)
Application can be breaked manually by using the Break command. If application executed a halt instruction the command Break.HALT should be used to terminate the application.
It is recommended to check the following chapters for all questions regarding the correct setup:
register.set pc 0x400register.set ssp 0x0fff0
; initialize program counter; initialize stack pointer to; allow; debugging from begin of program
breakpoint.set main /program
breakpoint.set counter /write
; set program break on function; main; set write break on variable; counter
• has a soldered CPU on the board (clip-over adaption)
• uses all chipselect lines, which means: address lines A19..23, function code lines FC0..2, BR-, BG- and BGACK- lines are not enabled.
• uses port E as port, which means: AS-, SIZ0..1 and DTACK are not enabled
• uses DS- line
• uses PLL clock mode
1. Set Module Hardware configuration
There are some special problems with this target configuration.
- Addresslines A19..23 are disabled, but the address information must be reconstructed for the emulator. Please read: Configuration: Address Recovery A19..A31.
- Except DS- all port-E lines are used as port, but the emulator needs the control line information of AS-, SIZE and DTACK. Please read: Configuration: Control Lines Recovery.
- Because of disabled address- and functioncode-lines some dip-switches on the module must be switched off: Please read: Configuration: DIP_Switches
system.system.option once on ; set target CPU to tristate
system.option size off ; SIZ0,1 not enabled (port E)
system.option dsack off ; DTACK0,1 not enabled (port E)
system.option fcode off ; FCode not enabled (ChipSelect)
system.option showberr on ; toggle emulator window if; BusError detected
system.option wdelay on ; Write strobe delay because of; address reconstruction (GAL on; module)
system.option fastterm on ; Enable for CPU internal or; FastTermination cycles
system.option STBY ON ; power for CPU internal RAM
system.o resetext on ; get reset config from target
map.bus8 0x007d000--0x007efff ; mapping for 8Bit memory areas; because SIZE lines are disabled!
system.access halt ; select halt-dualport-mode.
system.clock 32kHz ; emulator clock for 32 kHz PLL; mode.
system.line MODCLK on ; get target MODCLK config
system.mode emulext ; system up: EmulExt;(target, ext. clock); if the target 32 kHz crystal does; not start to oscillate please use; the emulator 32 kHz clock; use command: system.mode EmulInt; (target, int. clock)
Now the CPU is UP. Before running program some registers must be initialized to be sure the system settings, address-recovery and control-lines-recovery works well.
DTACK- line is disabled so enable the CPU internal Bus-Monitor:
All chip selects must be initialized to be sure the Address-Recovery works well. Write-Only chip-selects should be configured for read/write to allow program download.
data.set sd:0x0fffa00 %w 42cf ; set SCIMCR, enable Bus-Monitor
If you are not able to stop the emulation, there may be some typically reasons:
Double Address Error
After a double address error the CPU is in halt state. Use the SYStem.Up command to start again. Double address errors normally occur when the stack pointer is out of memory.
No DTACK Signal This condition occurs, if no DTACK signal is generated and the bus monitor is not activated. External accesses may be limited by SYStem.TimeOut. Internal accesses should be limited by the bus monitor. However some bytes between the peripherals are not monitored and force a hang-up of the emulation system. When the DSACK lines of the chip are used as I/O pins the emulator can’t terminate bus cycles. This can lead to an 'debug port timeout' error, when an address range without internal DSACK is accessed. In this case the CPU internal bus monitor should be enabled.- Clear bit FRZBM (Freeze Bus Monitor enable) of register MCR (Module Configuration Register).- Set bit BME (Bus Monitor External enable) of register SYPCR (System Protection Register).
WATCHDOG In 68332/68HC16 type CPUs the watchdog is enabled on RESET. Don't forget to disable the Software Watchdog (SWE) before starting emulation.
Clock error The clock lines between the target and the oscillator replacement are kept as short as possible. But the 32 kHz oscillator circuit has a very high impedance and correct operation with a crystal in the target cannot be guaranteed. Using the internal 32 kHz clock is recommended in this case. Internal clock must be used, when working in ONCE (On-Circuit Emulation) mode.
Low Speed Low clock frequencies may slow down the speed of the serial debugging interface. If debug timeout errors occur, increase the value TimeDebug to 10ms.
To realize the dualport access (emulation memory) the BR-line of the CPU is used (Request Mode). If these lines are used as chip selects or i/o, it is possible to make the dualport access by controlling the input clock. This “Clock Steal” mode cannot be used when the chip-internal PLL is active. Dualport accesses by bus request are only allowed while no external request to the bus occurs and the CPU cycle is completed. If the emulation CPU is in RESET state the system controller may always access the emulation memory.
Dualport errors may occur by the following conditions:
1. The length of the CPU cycle is extended by wait cycles, so that the request timeout signal is generated.
2. External DMA requests (single cycles) are too long (Request Mode).
3. The BR, BG or BGACK lines are used as ports or chip selects in
4. Request mode (processors with SCIM require only the BR line).
5. Show cycle control bits in SIM/SCIM are set to '10'.
To solve problems with dualport errors first increase the SYStem.TimeReq value. Be sure that the SYStem.TimeOut value is longer than the access time limit. If it is not possible to solve the problem by changing these values, you must switch to DENIED mode. In this mode no access to memory is possible while running realtime emulation. The internal dualport access can increase the reaction time for external DMA requests. The performance reduction by the dualport access is typically 1% with some data windows (dual ported) on the screen and may be at max. 5% when using dynamic emulation memory.
The debugger is accessed via Internet/VPN and the performance is very slow. What can be done to improve debug performance?
The main cause for bad debug performance via Internet or VPN are low data throughput and high latency. The ways to improve performance by the debugger are limited:
In PRACTICE scripts, use "SCREEN.OFF" at the beginning of the scriptand "SCREEN.ON" at the end. "SCREEN.OFF" will turn off screenupdates. Please note that if your program stops (e.g. on error) without exe-cuting "SCREEN.OFF", some windows will not be updated.
"SYStem.POLLING SLOW" will set a lower frequency for target statechecks (e.g. power, reset, jtag state). It will take longer for the debugger torecognize that the core stopped on a breakpoint.
"SETUP.URATE 1.s" will set the default update frequency ofData.List/Data.dump/Variable windows to 1 second (the slowest possiblesetting).
Prevent unneeded memory accesses using "MAP.UPDATEONCE<address_range>" for RAM and "MAP.CONST <address_range>" forROM/FLASH. Address ranged with "MAP.UPDATEONCE" will read thespecified address range only once after the core stopped at a breakpoint ormanual break. "MAP.CONST" will read the specified address range onlyonce per SYStem.Mode command (e.g. SYStem.Up).
Is there a simple way to control target power supply via the ICE to prevent problems after the ICE has been powered off?
Follow the sequence below.
If you own an output probe COUT8, connect it to the STROBE output con-nector.
Type PULSE2. and press F1. You will get the pin out of the output probeCOUT8. Pin 13 (OUT6) delivers +5 V after the emulator has finished its ini-tialization and 0 V if the emulator is powered off. This can be used to drivea relay via a transistor to switch the target power on and off automatically ifthe Pulse Generator is not used for other purposes. The schematic of theswitching unit can be found in the file TARGETC.CMM.
Additionally Pin 13 (OUT6) can be controlled by ICE commands.
Target power supply off. "PULSE2.P +" Target power supply on. "PULSE2.P -"
The following PRACTICE command file creates 3 buttons in the Toolbox for:
Target power on Target power off Target power off and QUIT.
To show the buttons automatically after starting the TRACE32 software, call the script with the DO command from system-settings.cmm in your TRACE32 system directory (create system-settings.cmm if it does not exist).
https://www.lauterbach.com/faq/targetc.cmm
Wrong Location after Break
Ref: 0030
Why is the location after break wrong?
Most emulators use some bytes of user stack for the break system. Therefore it is necessary to have valid stack, if single step or breakpoints are used.
68332
Clip-Over Adaption 68332/68HC16Z
Ref: 0004
Clip-Over Emulation on 68332/68HC16Z?
Clip-Over emulation is possible on 68332, 68HC16Z1 processors. However with some chips the switch-off voltage must be 9 V on the TSC pin. Older ICE-68332 modules must be changed (R932 47K).
The emulation probe supports all Motorola CPUs with 16 bit bus and serial debug interface. A slot for the port analyzer allows tracing all peripheral ports in timing and state mode. A premapper supports full 32 bit mapping in 4 different storage classes.
The emulation system uses the integrated debug interface. Address lines, strobes and FC signals are not buffered to the target. Target system hardware errors may force malfunction of the emulator, but the emulation system is always able to start as the debugging is made via the serial debug interface.
The debugger interface is hardware based to enable fast download and debug control. However the memory access is much slower (ca. 20 KByte/sec.) than on other emulator systems. Download speed may be increased when using dualport access. Some signal lines may not be used in their alternate function. The CLKOUT signal and the AS and DS signals must be available to the emulator system (strobes are always available on processors with SCIM Module).
Using Chip-Select lines instead of address lines to decode the target memory may bring problems for mapping and program trace. This problem can be solved by software address translation or by a GAL circuit. The GAL can translate the Chip-Select signals back to address lines.
If some address lines are used as ports or chip selects, they must be disconnected from the emulation memory to avoid malfunction of the system. A set of switches on the probe disables address and FC lines.
The emulator runs with internal or external clock signals. The emulator system supports a high frequency clock as well as a fixed 32 kHz reference clock for the PLL system on chip.
QFP chips may be emulated on board without desoldering the chip. A special clip-over adapter connects emulator module and target system. The standard adapter shipped with each system is a PGA-like connection, which fits into the footprint of an AMP, or optional 3M/TEXTOOL socket. This connection is very reliable and cheap.
If the address lines of the CPU are configured to have no address line functionality (chip select, port), the emulator will still need the missing addresses, to avoid address decoding conflicts. The probe can use three different methods to accomplish this:
Address Recovery by Register Contents
The CPU generates chip selects for the target and an EPLD device translates them back to addresses for the emulation and breakpoint memory.
Some register contents have to be entered to the SYStem window:
- All Chip Select Base Registers (CSBARBT, CSBAR0...10)
- the register base address (07ff000,0fff000)
- all Chip Select Pin Assignment Registers (CSPAR0,1) and
- the Port E Pin Assignment Register.
With this information the emulator 'knows' which address- and chip-select lines are active. In conjunction with the base addresses it reconstructs the missing address lines.
Furthermore it reconstructs missing control lines like AS-, DS-, SIZ0 or SIZ1.
The register base address (SYStem.Option BASE) defines the reconstructed address for CPU internal accesses (register or internal RAM). CPU internal accesses only can be reconstructed if AS- and DS- are active!
Reconstruct Addresses from Chip Selects.
This is the pre-ferred solution!
Method 1:Some modules have special logic to download the chip select base register contents to reconstruct the missing address lines.
Method 2:For some modules a special PLD device has to be programmed by the user to reconstruct the missing address lines from the Chip Selects.
Address recreation by Software
Software based address translation is possible if only chip select CS6..10 are in use.
Generate Chip Selects by PLD
Program the CPU to generate addresses and generate the Chip Selects by an PLD device on the bottom of the Pod.
The CPU generates Chip Selects for the target and a GAL device translates them back to addresses for the emulation and breakpoint memory. The switches on the probe are left open and a PLD device converts the CS lines back to address lines. If the AS or DS pin is used as a port, the AS and DS signals can be regenerated also by this PLD. The option WDELAY must be activated, when DS synchronized chip selects are used.
NOTE: Please use a 20V8-15ns PLD, DIL package. If the analyzer listing does not show the right reconstructed address lines, it might be useful to solder a capacity of 470pF in between pin 12 and pin 17 of the PLD to delay the signal DSDEL. This way all reconstructed address lines will be valid for a longer time after the CSx becomes inactive.
The CPU produces Chip Selects for the target and a GAL device translates them back to addresses for the emulation and breakpoint memory. The switches on the probe are left open and a PLD device converts the CS lines back to address lines.
The switches on the probe are left open and a standard PLD device converts the CS lines to the emulation memory bus and delays the strobes for correct timing. The translation can only be done with CS6 to CS10. The CS lines are used as regular address lines for the emulation memory. The memory must be mapped to the resulting memory address. The MMU command is used to build an translation table between logical address and Chip-Select address (the address that is seen on the bus). The option WDELAY must be activated, when DS synchronized chip selects are used.
The following example uses CS6 and CS7 lines to decode two 16-bit EPROMs:
An other solution to the chip select problem is to program all address pins to their address function and generate the CS-signals by a GAL or PAL on the bottom part of the probe. The Layout of this socket is made in a way, that when using no GAL, inputs and output may be connected by a zero-ohm resistor network. If some lines are not used as chip select signals, the GAL must be programmed to tristate output and inputs and outputs should be connected by a short wire soldered on the GAL. The pin function must be programmed as an address line. The advantage of this solution is the higher possible emulation speed.
Some control lines of the CPU are required by the emulator. If they are configured for alternate pin functions the information on the pin must still be available to the emulator. There are three different solutions available
Function Codes have alternate Pin Function
When the function code lines have alternate pin function, the DIP-Switches 6, 7 and 8 must be opened and the command SYStem.Option FCode OFF selected. This informs the emulator, that function code lines are not available.
Port-E Control Lines Recovery for SCIM Modules
On probes with integrated port replacement these lines can be used without restriction, as they are driven by the port replacement.
Use CPU internal- oremulator-resources for work around.
• CPU bus monitor for DTACK replacement• MAP.BUS8 for SIZ replacement.
Reconstruct pin-function by hard-ware or PLD logic.
Solution for AS-, DS-, SIZ0, SIZ1.
Generate port func-tion by a port replacement.
Solution for AS-, DS-, SIZ0, SIZ1. Program the CPU to generate control signals and generate the port function by a port replacement on the module.
To prevent hang up conditions the CPU internal bus monitor should be enabled.
• Clear bit FRZBM (Freeze Bus Monitor enable) of register MCR (Module Configuration Register)
• Set bit BME (Bus Monitor External enable) of register SYPCR (System Protection Register)
• Set SYStem.Option DTACK to OFF
AS- has alternate Pin Function
Modules which are equipped with the Address recovery by register contents logic automatically will reconstruct the missing AS- functionality. Show cycles will not work with this configuration. The SYStem.Option WDELAY must be set to ON.
For all other modules where the DS- line is available, it can be connected to the AS- line by connecting pins 15 and 16 together on the socket on top of the emulation pod. DIP-Switch #9 must be opened. Show cycles will not work with this configuration. The SYStem.Option WDELAY must be activated.
DS- has alternate Pin Function
Modules which are equipped with the Address recovery by register contents logic automatically will reconstruct the missing DS- functionality. Show cycles will not work with this configuration. The SYStem.Option WDELAY must be set to ON.
For all other modules where the AS- line is available, it can be connected to the DS- line by connecting pins 15 and 16 together on the socket on top of the emulation pod. DIP-Switch #10 must be opened. Show cycles will not work with this configuration. The SYStem.Option WDELAY must be activated.
When the external memory is either 8 bit or 16 bit read-only memory, the emulator can work without size lines. In this case use the command SYStem.Option SIZE OFF to turn off the size information. The command MAP.BUS8 must be used to mark all 8 bit wide memory areas.
If external 16 bit RAMs have to be supported, the size information is necessary. As the data bus is only 16 bits wide, SIZ1 can be generated from SIZ0 and vice versa.
Modules which are equipped with the Address Recovery by register contents logic automatically will reconstruct the missing SIZ line.
For all other modules:
• To generate SIZ0 from SIZ1 open pin 11 of the AC04 on the pod and connect the pin to pin 12.
• To generate SIZ1 from SIZ0 open pin 13 of the AC04 on the pod and connect the pin to pin 10.
• SIZ0,1 can be generated by a PLD logic from the Chip-Select information. See Address Recovery by PLD logic
AS, DS, SIZ0, SIZ1 Port Replacement
An alternative to reconstruct the strobes and size lines from the Chip-Selects is to use an special port replacement of the emulator. In this case the CPU is programmed to generate the required strobes and the lost I/O ports are replaced by an extra port on the emulation probe.
Enable port replacement if Line is switched OFF. The port replacement becomes active if AS, DS, SIZ0 or SIZ1 is switched off in the SYStem window. The port replacement is only active for the switched off lines. When activated, the target line is connected directly to the CPU. When off, the line from the target is connected to a port replacement unit on the probe.
SYStem.Option PRBASE Peripheral address
Defines the base address of the port replacement unit for the AS, DS, SIZ0 and SIZ1 lines.
The address of the port is adjusted by this command. PRBASE must be outside the internal register area and has to be aligned to a 4 KByte boundary. The whole 4 K address range is reserved for the port replacement. The PortDataRegister is located at address PRBASE+1, PRBASE+5 and is mirrored all 4 bytes. The PortDataDirectionRegister is located at address PRBASE+3, PRBASE+7 and is also mirrored to all 4 bytes.
Bit 7 = PE7/SIZ1
Bit 6 = PE6/SIZ0
Bit 5 = PE5/AS-
Bit 4 = PE4/DS-
Care must be taken if DSACK0,1 are switched off! In this case PRBASE must be set to an address where the chipselect logic creates a DTACK! This means the port replacement takes 4 KByte of a chipselect address range which no more can be used as standard RAM or ROM!
Care must be taken if SIZ0,1 are switched off! In this case there might be problems with word or byte accesses to the port replacement. Please try.
In the case of port replacement the processor line is connected to the emulator and the line from the target is connected to the port replacement. The software must be modified to access the address of the port replacement instead of the internal registers of the CPU. There should be mapped an acknowledge (MAP.A PRBASE++0fffh) for the address range of the port replacement if there is no CPU internal generated one. All other port E3..0 bits are still located at their original address in the CPU internal register range.
Some modules have DIP-Switch on the top of the probe to disconnect address and function code lines which are configured for alternate pin function.
Each address line, which has an alternate pin function, must be switched OFF! The missing address lines can be reconstructed by the Address Recovery by PLD logic method.
All function code lines must be switched OFF if one or more lines have alternate pin function! The SYStem.Option FCode must be set to OFF.
If AS- or DS- is configured for alternate pin function and(!) the missing functionality is reconstructed by a PLD logic the appropriate switch has to be set to OFF. See Control Lines Replacement.
For processors with CPU16 core the (internal) address lines A20 to A23 follow A19. When compilers generate symbols with A20 to A23 set, this logical addresses must be mapped to the lower 1 MBytes physical addresses by a MMU translation:
There are several restrictions when working with ICE-332:
Strobes The AS- and DS-pin should not be used as I/O port. A port replacement is available for the AS and DS lines. The strobes can be recreated also from the chip selects by the GAL on top of the probe. The CLKOUT signal should not be switched off. The analyzer will not work if it is switched off. The SIZ and DTACK pins are not necessary for the emulator function, but if not used the command SYStem.Option SIZE OFF should be set to inform the emulator system. If DTACK pins have other functions, switch off the DTACK option field.
FTERM FTERM cycles are very fast memory cycles, too fast for the synchronous breakpoint system. With frequencies over 17 MHz it is not possible to use FTERM bus cycles and hardware program breakpoints. Zero wait state operation is possible with software breakpoints and fast emulation memory. Fast termination write cycles are not supported by the emulation memory.
Show Cycles Show cycles are very fast memory cycles. At 16.7 MHz they are 120ns wide, which is too fast for the SA120 analyzer, the HA120 analyzer is fast enough. Setting breakpoints to show cycles requires fast breakpoint memory (requirements like for FTERM cycles).
Transparent Mode The 68340 probe doesn't support transparent write modes. The data buffer from CPU is activated on write and blocks the data bus.
DMA Function Code
On DMA cycles (68340) the FC3 bit should always be set to one. Otherwise the program breakpoint system will not work correctly.
Program Access with 8-Bit bus with-out FC lines
The second opfetch (odd byte) cannot be identified as program or data access. The emulator assumes always a program access, to allow program breakpoints. For normal operations this behavior is transparent to the user. The display in the analyzer window will show the correct access class by looking to the context of the access.
Program Execution in Onchip RAM
Program breakpoints and single stepping don't work when executing code in the Standby RAM of the 68332/68HC16.
Synchronous and Asynchronous Breaks (CPU16)
When an asynchronous breakpoint (i.e. stop by trigger) occurs two byte after an active synchronous breakpoint (Program, Spot or Hll) the PC value can be two too less. This is because the CPU16 core gives no information about the reason for entering the BDM state (either BKPT line or BDM instruction).
The BDM interface on the CPU16 allows only word accesses to the program memory (SP: memory class). Non aligned reads will also include the byte before or after the location and make a word access. Byte writes will perform a read operation and write the modified word to the memory.
Side Effects of PER window
Reading some status registers while single stepping can cause different program behavior. The read of the SCSR register will mark the status bits of this register to be cleared with the next SCDR access.
The emulations head can stay in 6 modes. The modes are selected by the SYStem.Up or the SYStem.Mode command.
In active mode, the power of the target is sensed and by switching down the target the emulator changes to RESET mode. The probe is not supplied by the target. When running without target, the target voltage is simulated by an internal pull-up resistor. The command SYStem.Up in Stand-alone doesn't work correctly. Use SYStem.Mode AloneInt to select correct emulation mode.
Defines the base address of the internal peripherals. This value is used by the PER command to display the internal registers.
Furthermore this value defines the address which is reconstructed by the 'Address Recovery by register contents' logic at CPU internal accesses.
Format: SYStem.Access <option>
<option>: RequestClkStealDeniedHalt
Request This is the default method accessing memory in realtime. It works only on if the bus request/bus grant function is enabled. If these pins are changed to alternate function, dualport access will not work correctly. Probes with SCIM Module have an integrated port replacement and require only the BR line.
ClkSteal This method enables dualport accesses by stopping the clock for some cycles. The clock source must be set to clock steal (see Clock Modes) and the internal VCO generates the clock. It is not possible to run this access mode with external clock signals or with 32 kHz clock sources (PLL system active). If dualport access is required and the Request mode cannot be used, the software for the periodic timer and the software watchdog must be modified to use the direct clock input.
Denied No dualport access allowed. On realtime emulation all windows, which need dualport access, are frozen. Breakpoints cannot be set while realtime emulation is running.
Halt This method uses the CPU's HALT pin to get the bus for dualport access. It should be used if Request mode and ClkSteal mode cannot be used.
Either the clock frequency divided by 4 or 8 is used as the BDM clock or a fixed clock rate. The fixed clock rate must be used when the operation frequency is very slow or the clock is turned off.
Auto Automatic frequency select in order to the setting on MODCLK field. If MODCLK is low, the VCO is selected (Direct Input). Otherwise the 32 kHz fixed frequency signal is used to support the clock input (PLL reference clock).
32KHZ frequency fixed to 32 kHz.
VCO/100 VCO frequency divided by 100.
VCO*2 Doubled VCO frequency.
ClkSteal VCO Clock for clocksteal dualport mode. See also SYStem.Access.
External DMA circuits and the IDMA circuit on the target CPU work in the same way: both request the main CPU with the BR signal. In realtime emulation the emulation CPU is stopped and the DMA can get control of the bus. When emulation is stopped, no BG signal is generated and the DMA is waiting till realtime emulation is started.
The DMA accesses make also writes to emulation memory. On read access to internal mapped memory the data information is driven to the target system. Be sure that there is no memory to avoid bus conflicts.
SYStem.Option DSACK DSACK mode
Switch ON if the cpu-dtack-line has dtack functionality.
The DTACK lines may be used normally. In this mode WAIT mapping is possible. In the other way the DTACK control system is disabled. The DTACK pins are directly connected to the target system.
See 'Hang-Up conditions'!
Format: SYStem.Line BusReq [ON | OFF]
Format: SYStem.Option DMATRACE [ON | OFF]
Format: SYStem.Option DMATRANS [ON | OFF]
SYStem.Line Bus-Req
This option allows DMA access without running realtime emulation. External DMA circuits are not stopped on breakpoints.
SYStem.Option DMATRACE
DMA cycles may be traced and trigger system is also active on DMA cycles.
SYStem.Option DMATRANS
The DMA accesses make also writes to emulation memory. On read access to internal mapped memory the data information is driven to the target system. Be sure that there is no memory to avoid bus conflicts.
This option must be used when the system uses fast termination cycles.
SYStem.Option FCode FCODE pins
Switch OFF if not all CPU function-code lines have function-code functionality.
The FC0..FC2 lines may be used normally or as ports. If the lines are used as ports or chip selects, this option must be turned off and the three switches on the probe must be opened.
SYStem.Option LIMITDP Dualport access limitation
Limit dualport access rate for clock steal mode.
Format: SYStem.Option FastTerm [ON | OFF]
Format: SYStem.Option FCode [ON | OFF]
Format: SYStem.Option LIMITDP [ON | OFF]
ON In clock steal mode the performance reduction is limited to 1%
Enable pll mode. The MODCLK input line defines if the CLK input is direct or a 32 kHz reference signal for the PLL. If the SYStem.Line is activated, the line will be connected to the target PIN. If the target PIN is connected directly to supply, this line must be switched off, when the clock mode needs to be changed.
The SYStem.Option selects the value supplied by the emulator through an 100 K resistor.
For 68375/68396:
SYStem.Line/Option VCCSYN PLL mode
SYStem.Option ONCE On-circuit emulation
Set to ON when using the Clip-Over-Adapter with QFP-Packages. The CPU chip on the target board is set to tristate on RESET by setting the TSC (TriStateControl) pin to VCC * 1.6. The TSC pin should be connected to VCC via a resistor. If the pin voltage is less than 7 V an error message occurs. An emulation mode with internal clock must be used (EmulInt or AloneInt). For some derivatives this command is not necessary and locked.
The CPU32/CPU16 processors are checking the data bus on reset in order to set internal registers. In standalone mode or if no option ResetExt is selected, the value of ResetMode defines the state of the data bus when the reset line becomes inactive.
SYStem.Option ShowBreak/ShowTrace Show cycles
Show cycles are CPU access cycles to internal RAM or peripherals. This cycles generate no strobe signals to the external bus, until the bits SHEN0 and SHEN1 in the MCR register are set.
ShowTrace enables the analyzer and trigger features for Show Cycles.
ShowBreak enables the breakpoint memory for Show Cycles.
As show cycles need only 2 clock states either the emulation memory and trace memory must be fast or the clock frequency should not exceed 12.5 MHz. Synchronous PROGRAM breakpoints will not work in internal memory, as there is no access to the CPU bus possible.
Format: SYStem.Option RamWait [ON | OFF]
Format: SYStem.Option ResetMode <vector>
Format: SYStem.Option ResetExt [ON | OFF]
Format: SYStem.Option ShowBreak [ON | OFF]
Format: SYStem.Option ShowTrace [ON | OFF]
NOTE: Don't use the combination 01 if in Request mode (dualport)
Displays bus errors received when reading memory by the BDM display. The data values will toggle between 0 and 0xff to show a bus error. When turned off, the emulator will report the Bus Error. The feature will work only when the bus monitor of the 683xx SIM Module is not frozen.
SYStem.Option Size SIZE pins
Switch OFF if the CPU SIZE lines have no SIZE functionality!
The SIZE lines may be used normally or as ports. If the lines are used as ports, this option must be turned off. The bus size is then determined by the mapping system (command MAP.BUS8).
SYStem.Option STBY Standby voltage
SYStem.Option TEST TEST mode
Enable CPU test mode.
Format: SYStem.Option ShowBERR [ON | OFF]
Format: SYStem.Option Size [ON | OFF]
Format: SYStem.Option STBY [ON | OFF]
ON The STBY pin is always supplied even if the target power is off.
OFF Internal RAM data are lost if target power is off.
One additional wait state is inserted whenever two memory accesses take place back-to-back. This function is necessary in order to ensure that the SA120 analyzer works properly when the minimum time between two cycles is less than150ns (68332 at 20 MHz). Loss in performance is minimal, only a few percent.
SYStem.Option VFPEx Flash programming voltage
Supplies the FLASH programming voltages. The option can be used to program the internal FLASH memories in standalone mode (see also the FLASH command group in the Flash Programming Manual).
SYStem.Option WDELAY Write strobe delay
Delays the write strobe. This option must be used, when addresses or strobes for the emulator are generated by DS synchronized chip selects of the CPU.
Format: SYStem.Option TestClock [ON | OFF]
ON The clock test circuit is active. Clock fails will be detected by the emulator system. The emulator changes to reset state.
OFF No clock check. The EXOFF function (MCR register) may be used, but no trace of program and data is possible.
This modules uses the Address Recovery by PLD Logic method to reconstruct disabled address lines. Please have a look to this chapter for additional information.
Port-E Control Lines
This modules requires some port E control lines. Please have a look to Configuration: Port-E Control Lines recovery, especially for SIM modules.
DIP-Switches This modules has DIP-Switches to cut some CPU signals from the emulator bus interface. See DIP-Switches.
Address Lines A19..23
This module uses the Address Recovery by register contents method to reconstruct disabled address lines. Please have a look to this chapter for additional information.
Port-E Control Lines
Control lines are enabled always. No special setting is needed! See Port-E Control Lines recovery for SCIM modules.
Address Lines A19..23
This modules uses the Address Recovery by PLD Logic method to reconstruct disabled address lines. Please have a look to this chapter for additional information.
Port-E Control Lines
Control lines are enabled always. No special setting is needed! See Port-E Control Lines recovery for SCIM modules.
DIP-Switches This modules has DIP-Switches to cut some CPU signals from the emulator bus interface. See DIP-Switches.
Enable premapper. This function is only needed when address lines A24 to A31 are used for addressing memory. Switch OFF if not used to speed-up memory access.
Address Lines A24..31
This module does not support address recovery!
Control Lines Control lines are enabled always. No special setting is needed!
DIP-Switches This modules has DIP-Switches to cut address lines A24..31 from the emulator bus interface. See DIP-Switches.
ClockMode JumperSettings
There are two jumpers on the module for VDDSYN and XFC. The setting should be done according to your target requirements.Crystal Mode: VDDSYN--VCC, XFC--NCExt.Clock Mode: VDDSYN--GND, XFC--GNDExt.Clock PLL: VDDSYN--VCC, XFC--NC
MODCK setting is done with the command SYStem.Option MODCK ON/OFF
Format: SYStem.Option PreMap [ON | OFF]
Attention: This option must be switched on before any Map.Pre command is done!
Selects the emulated processor type. This function is only required to distinguish pin compatible processors in the same emulation module.
DIP Switches 68336/376
There are dip switches in between the module’s PCBs. Please disconnect the top- from the bottom-PCB and do the following switch setting:
Address Lines A19..23
This modules uses the Address Recovery by PLD Logic method to reconstruct disabled address lines. Please have a look to this chapter for additional information.
Port-E Control Lines
This modules requires some port E control lines. Please have a look to Configuration: Port-E Control Lines recovery, especially for SIM modules.
DIP-Switches This modules has DIP-Switches to cut some CPU signals from the emulator bus interface. See DIP-Switches.
This module uses the Address Recovery by register contents method to reconstruct disabled address lines. Please have a look to this chapter for additional information.
Port-E Control Lines
This module requires some port E control lines. Please have a look to Configuration: Port-E Control Lines recovery, especially for SIM modules.
Enable premapper. Is needed when emulating 68330, 68340 or 68341 processors and the address lines A24 to A31 are used for addressing memory or generating chip-select signals. Switch off if not used to speed-up memory access.
SYStem.Option TRANS DMA modes
This option enables Single-Address DMA for Channel 1 and/or 2..
Address Lines A24..31
This modules uses the Address Recovery by PLD Logic method to reconstruct disabled address lines. Please have a look to this chapter for additional information.
Control Lines Control lines are enabled always. No special setting is needed!
DIP-Switches This modules has DIP-Switches to cut address lines A24..31 from the emulator bus interface. See DIP-Switches.
DMA Modes This CPUs include a DMA controller. The emulator supports Dual-Address DMA without restrictions, without any special system settings needed. Single-Address DMA is just supported for READ DMA!
Format: SYStem.Option PreMap [ON | OFF]
Attention: This option must be switched on before any Map.Pre command is done!
If SYStem.Line is set to ON, the EPEB0 pin will be connected to the target PIN. If the SYStem.Line is set to OFF the SYStem.Option selects the value which is supplied to EPEB0.
SYStem.Option VPP Flash programming voltage
Supplies the FLASH programming voltages. The option can be used to program the internal FLASH memories in standalone mode (see also the FLASH command group in the Flash Programming Manual).
Address Lines A19..23
This modules uses the Address Recovery by PLD Logic method to reconstruct disabled address lines. Please have a look to this chapter for additional information.
Port-E Control Lines
Control lines are enabled always. No special setting is needed! See Port-E Control Lines recovery for SCIM modules.
DIP-Switches This modules has DIP-Switches to cut some CPU signals from the emulator bus interface. See DIP-Switches.
The FASTREF input line defines the slow or fast reference PLL mode.
If the SYStem.Line is activated, the line will be connected to the target PIN. If the target PIN is connected directly to supply, this line must be switched off, when PLL mode needs to be changed.
The SYStem.Option selects the value supplied by the emulator through an 100 K resistor.
The FASTREF input line defines the slow or fast reference PLL mode.
If the SYStem.Line is activated, FASTREF line will be connected to the target PIN. If the target PIN is connected directly to supply, this line must be switched off, when PLL mode needs to be changed.
The SYStem.Option selects the value supplied by the emulator through an 100 K resistor.
Address Lines A19..23
This module uses the Address Recovery by register contents method to reconstruct disabled address lines. Please have a look to this chapter for additional information.
Port-E Control Lines
Control lines are enabled always. No special setting is needed! See Port-E Control Lines recovery for SCIM modules.
Every block in the address space of the CPU has either an 8 or 16 bit bus width. The emulator breakpoint and trace system need this information in realtime in order to work correctly. On setting up the emulator system all areas are defined with 16 bit bus width as default.
The MAP.RESet command sets the bus width definition to 16 bit.
MAP.Onchipp Onchip peripherals
To set the bus driver direction correctly when other bus masters are accessing the internal peripherals (SLVEN = 1) the address range of the peripheral area must be mapped.
Format: MAP.BUS8 [<range>]
Format: MAP.NOBUS8 [<range>]
map.bus8 0x0--0x0fffff ; maps first 1 MB block for 8 bit
The disassembled lines in the analyzer are displayed prior to the resulting data cycles. This dequeueing fails for commands which have not a constant number of data cycles.
Problems with prefetches:
• short forward conditional branches to addresses already prefetched
CODE::BLOCKS - -C++TEST - WindowsADENEO -X-TOOLS / X32 blue river software GmbH WindowsCODEWRIGHT Borland Software
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EASYCODE EASYCODE GmbH WindowsECLIPSE Eclipse Foundation, Inc WindowsRHAPSODY IN MICROC IBM Deutschland GmbH WindowsRHAPSODY IN C++ IBM Deutschland GmbH WindowsCHRONVIEW Inchron GmbH WindowsLDRA TOOL SUITE LDRA Technology, Inc. WindowsUML DEBUGGER LieberLieber Software
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SIMULINK The MathWorks Inc. WindowsATTOL TOOLS MicroMax Inc. WindowsVISUAL BASIC INTERFACE
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TPT PikeTec GmbH WindowsCANTATA QA Systems Ltd WindowsRAPITIME Rapita Systems Ltd. WindowsTESSY Razorcat Development
The emulation probe is designed for running with CPU's up to 25 MHz. The max. speed is limited by the memory speed and the wait states used for memory access.