IBM Assembly Language Coding (ALC) Part 1

IBM Mainframe Assembler Language Coding

Main Storage

Main storage (memory) is measured in terms of 8-bit bytes

and an address is assigned to each. The first byte is assigned

address zero, the second byte address one, etc. Main storage

is directly addressable and provides for high-speed

processing of data. Both data and programs must be loaded

into main storage from input devices before they can be

processed. The amount of main storage available depends on

the model of the CPU.

Mainframes today (1998) can have up to 2 Gigabytes of real

1

Mainframes today (1998) can have up to 2 Gigabytes of real

memory. Worldspan has mainframes with 2 Gigabytes of real

memory. This means that byte addresses on such a computer

run from 0 to 2,097,143,807 (7CFFDFFF in hex).

last updated 12/29/99


Each processor (CPU) contains 16 General Purpose Registers.

The registers are numbered 0 - 15 (0 - F in hexadecimal

notation). Each register contains 32 bits or the equivalent of

four bytes of main storage. The bits within each register are

numbered 0 - 31 from left to right. The General Registers are

used to contain binary data in the form of accumulators,

counters or in conjunction with binary arithmetic operations.

In addition, 15 of the 16 general registers may be used as

base-address and index registers in address generation.

Register zero specifies that no base or index is to be applied,

General Registers

2

Register zero specifies that no base or index is to be applied,

and, thus, general register zero cannot be designated as a

base or index register.


Program-Status Word

The current Program-Status Word (PSW) in the CPU contains information required for the execution of the currently active program. The PSW is 64 bits in length and includes the instruction address, condition code, and other control fields. In general, the PSW is used to control instruction sequencing and to hold and indicate much of the status of the CPU in relation of the program currently being executed.

0

PSW bits

18 19 32 33 63Instruction Address

3

Condition Code (CC): Bits 18 and 19 are used to contain the condition code. The condition code is set to 0, 1, 2 or 3, depending on the result obtained in executing most arithmetic and logical operations as well as some other operations.

Addressing Mode: Bit 32 controls the size of effective address generation. When the bit is zero, 24-bit addressing is specified. When the bit is one, 31-bit addressing is specified.

Instruction Address: Bits 33 - 63 form the instruction address. This address designates the location of the leftmost byte of the next instruction to be executed.

Condition CodeAddress Mode


Assembler Programming Conventions

• names/tags/labels must begin in column 1. They :

– should be 8 characters or less

– can only consist of A - Z, 0 - 9, $, @, #

– must start with a letter or national character

– there are company naming standards for labels.

• operation codes should begin in column 10.

• operands should begin in column 16 and must not continue beyond column 71.

• lower case (or a mixture of cases) is not recognized by the assembler for labels or operands.

• to continue a line:

– stop coding at column 71 or before

4

– put any non-blank character in column 72

(requires command - set trunc 72)

– start the next line in column 16

• to code comments:

– leave at least one space after the operands, then code comments out to column 71

– or place an asterisk in column 1 and code comments in columns 2 - 71

– comments are not included in the object module, but they are printed on the assembly listing. They help provide narrative documentation of the program.



Types of Instructions

• Machine Instructions: cause the system to execute the program instructions one by one at run time. e.g. MVC, LR. Machine Instructions are produced by the Assembler.

• Assembler instructions: are instructions to the assembler program. They are interpreted by the Assembler at assembly time e.g. DS, DC. The Define Storage instruction will not produce any object code but the Define Constant will.

• Macro instructions: are expanded by the assembler into several machine instructions to save development time e.g. OPEN, CLOSE, GET, PUT.

5


Machine Instructions Characteristics

The following statements are generally true about the S/370

formats (there are some exceptions).

• RR format:

– The mnemonic operation code ends in “R”.

– Two register operands.

– The result of the operation is placed in the first operand.

• RX format:

– One register operand and one storage operand.

– The storage operand is addressed by the left-most byte.

– The storage operand is usually boundary aligned.

6

– The storage operand is usually boundary aligned.

– The storage operand is usually fixed length, i.e. halfword, fullword, doubleword.

• RS format:

– Two register operands and one storage operand.

• SI format:

– One storage operand (one byte in length) and one byte

of “immediate” data within the instruction.

– The “immediate” data operates on the first operand.


Machine Instructions Characteristics

• SS format:

– Two storage operands.

– The result of the operation is placed in the first operand.

– Each operand is addressed by the left-most byte.

– The length codes in the machine language instruction is one less than the total number of bytes specified in the operands.

– The method of instruction execution depends on the presence of one or two length codes in the instruction.

• SS1 format, one length code:

– The maximum operand size is 256 bytes.

7


– Operands are operated upon left to right within each operand.

– The length of the first operand controls the execution. Therefore, both operands should be the same length.

• SS2 format, two length codes:

– Each operand has its own length.


– Operands are operated upon from right to left within each field. (The data address is still the left-most byte; the length code is used to get over to the right-most byte for execution.)


Load Fullword

L R6,CE1CR0

CE1CR0 before: CE1CR0 after:

00 F2 CE 83 00 F2 CE 83

Reg 6 before: Reg 6 after:

00 00 10 0C 00 F2 CE 83

8


00 00 00 CC

An arithmetic expression appended to a symbol allows modification of the displacement that is generated by the assembler.

L R3,FIELDA+12

L R4,FIELDA+((3-1)*4)

Relative Address

00 00 00 FFFIELDA

00 00 00 EE

00 00 00 DD

R3 After

R4 After

9

00 00 00 DD

00 00 00 CC 00 00 00 DD

R4 After


Move Characters Instruction

The Move Characters instruction actually copy data from onememory location to another.

MVC - The Move Character copies L bytes (where L <= 256) from the memory location designatedby the 2nd operand to the memory locationdesignated by the 1st operand. The result is abyte-for-byte move.

MVC D1(L,B1),D2(B2)

MVC 10(17,R3),0(R4)

10

MVC 10(17,R3),0(R4)

MVC LABEL1,LABEL2

MVC 10(17,R3),LABEL2


Move Character Example

VAL1 DC C'ABCDE'

VAL2 DC C'1*!?2'

MVC VAL2,VAL1

VAL2 before:

1 * ! ? 2

VAL2 after:

A B C D E

11

A B C D E



RESULT DC CL8' '

VAL1 DC C'ABCD'

VAL2 DC C'XY'

VAL3 DC C'GARBAGE'

MVC RESULT,VAL1

RESULT before:

b b b b b b b b

RESULT after:

12

RESULT after:

A B C D X Y G A

MVC RESULT(4),VAL1

RESULT before:

b b b b b b b b

RESULT after:

A B C D b b b b



RESULT DC CL8' '

VAL1 DC C'ABCD'

VAL2 DC C'XY'

VAL3 DC C'GARBAGE'

MVC RESULT+4,VAL2

before:

b b b b b b b b A B C D X Y

RESULT VAL1 VAL2

13

after:

b b b b X Y G A R B A G X Y

RESULT VAL1 VAL2



B1 DC C' '

OUTPUT DS CL133

MVC OUTPUT,OUTPUT-1

before:

b ? ? ? ? ? ? ? ? .....

B1 OUTPUT

14

after:

b b b b b b b b b .....

B1 OUTPUT



RESULT DC CL8' '

VAL1 DC C'ABCD'

VAL2 DC C'XY'

VAL3 DC C'GARBAGE'

MVC RESULT+4(2),VAL2

before:

b b b b b b b b A B C D

RESULT VAL1

15

after:

b b b b X Y b b A B C D

RESULT VAL1


Model Program

BEGIN NAME=ZOO1,VERSION=II

*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*

*=-= ZOO1 -- PROGRAM 0 =-=*

*=-= THIS PROGRAM ... =-=*

*=-= =-=*

*=-= INPUT -- B@x… =-=*

*=-= OUTPUT -- SCREEN =-=*

*=-= =-=*

*=-= LEVELS -- D0 -- A-06-IMG INPUT MESSAGE BLOCK =-=*

*=-= =-=*

*=-= REGISTERS -- R0 -- =-=*

*=-= -- R1 -- =-=*

*=-= -- R2 -- =-=*

*=-= -- R3 -- =-=*

*=-= -- R4 -- =-=*

*=-= -- R5 -- =-=*

*=-= -- R6 -- =-=*

*=-= -- R7 -- =-=*

*=-= -- R14 -- =-=*

*=-= -- R15 -- =-=*

*=-= =-=*

*=-= WORKAREAS -- EBW000-063 -- OUTPUT MESSAGE LINES =-=*

16

*=-= WORKAREAS -- EBW000-063 -- OUTPUT MESSAGE LINES =-=*

*=-= -- EBXnnn-nnn -- ………. =-=*

*=-= =-=*

*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*

*

MI0MI REG=R1 ADDRESABILITY TO INPUT MESSAGE

L R1,CE1CR0 BASE OF INPUT MESSAGE

*

*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*

*=-= BODY OF PROGRAM =-=*

*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*

* GET , GET AN INPUT RECORD

* PUT , DISPLAY A LINE OF OUTPUT

*

*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*

*=-= CLOSING ROUTINES =-=*

*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*

*

* PUTEXIT , DISPLAY A LINE OF OUTPUT AND

* TERMINATE THE ENTRY

*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*

*=-= DEFINE CONSTANTS =-=*

*=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=*

*

FINIS , TERMINATE TPF PROGRAM

END , TERMINATE ASSEMBLY



Entry Control Block

Workarea .. 1/A EBW000 - EBW103

104 Bytes

D0 - CE1CR0 - a core address

nnnnnnnn

nnnnnnnn

R9

. . . . .

17

Workarea .. 2/B EBX000 - EBX103

104 Bytes

D8 - CE1CR8 - a core address

nnnnnnnn

. . . . .


18


EXERCISE #1

PROGRAM 1.

Instructor will walk the class through this exercise.

Save the input message.

Move the input message to a designated output area.

Display the message on the terminal.

Requires two instructions added to shell.

Shell is ZOO1ii assemble.

19

Input: b@lastname+

Move data (length 15) from input message block to

EBX000-014.

Move data (length 15) from EBX000 to EBW000-014.

Use the PUTEXIT macro.

'HARDCOPY' the source code and the listing.

When above is working - modify program to handle

length equal to number of characters in your last name.


20


Address Generation

Prior to the advent of the System/370 Extended Architecture (370-XA) feature, storage addresses were limited to a 24-bit binary number, up to 16,777,216 (decimal) or 16 mega-bytes of addressable storage. While retaining this capability, 370-XA provides for storage addresses to be a 31-bit binary number, up to 2,147,483,648 (decimal) or 2 giga-bytes of addressable storage

Bimodal Addressing: The addressing mode is controlled by bit 32 of the Program Status Word (PSW). Instructions are provided that examine and set the mode. This permits combining old programs, which must operate in 24-bit mode, and new programs, which can take advantage of the 31-bit addressing mode.

21

addressing mode.

Address Mode Bit: Off (0) = 24-bit addressing

On (1) = 31-bit addressing

0

PSW bits

32 40 63

Address ModeBit

33

24-bit address

31-bit address


Address Generation

The address used to refer to main storage either is contained in a register designated by the "R" field in the instruction or is calculated from the following three binary values:

•Base Address

– A binary number contained in a general register specified by the program in a 4-bit field called the "B" field in the instruction.

•Index

– A binary number contained in a general register designated by the program in a 4-bit field called the "X" field in the instruction. It is included only in the address specified by the RX instruction format.

•Displacement

22

•Displacement

– A 12-bit number contained in a field called the "D" field in the instruction. The displacement provides for relative addressing designated by the base register.

A zero in either the "X" or "B" fields indicates the absence of the corresponding address component. For the absent component, a zero is used in forming the address, regardless of the content of register zero. A displacement of zero has no special significance (it simply means 0 displacement).

Because of the significance of zero indicating the absence of a component of an instruction, register zero should never be used as a Base register or Index register in any instruction.

Register zero cannot be designated as containing a branch address. A value of zero in the R2 field causes the instruction to be executed without branching.


Address Generation

In computing the address, an intermediate sum is first calculated. The base address and index value are treated as 32 bit binary integers. The displacement is treated as a 12-bit binary integer, and 20 zeroes are appended on the left. The three are added as 32-bit binary numbers, ignoring overflow. The sum is always 32 bits long and is used as an intermediate value to form the effective address. When an instruction specifies that the address is contained in a general register, the register contents are used as the 32-bit intermediate value. The effective address is formed from the intermediate value as follows:

•In the 24-bit addressing mode, the rightmost 24 bits of the sum are retained. The leftmost 8 bits are set to zero.

•In the 31-bit addressing mode, the rightmost 31 bits of the

23

•In the 31-bit addressing mode, the rightmost 31 bits of the sum are retained. The leftmost bit is set to zero.

The bits of the address are numbered 8-31 and 1-31, respectively, corresponding to the numbering of base-address and index bits in a general register:

31-bit address

0 311

24-bit address

0 318


Assembler Procedure

Phase 1

•Functions

– Maintenance of location counter

– Address assignment

– Construction of symbol table

•Terms

– The location counter is a binary counter that contains the 24-bit address of the current instruction or data field. This counter is initialized to the value in the 'Start' statement operand. Thereafter, as the assembler assigns addresses, the location counter is incremented by the number of bytes required by each assembled instruction

24

number of bytes required by each assembled instruction or data field.

– The Symbol Table is constructed from the symbols appearing in the name field of each instruction or data field. Each entry contains the symbol, the 24-bit binary address assigned by the assembler and the length attribute.



Assembler Procedure

Phase 2

• Functions

– Construction of a base register table.

– Assignment of base and displacement values to instruction operands.

– Generation of object module and assembly listing.

• Terms

– The base register table is constructed to contain the register number specified in the second operand of the Using statement and the value that the base register will contain at execution time (specified in the first operand of the Using statement). The entry is made

25

operand of the Using statement). The entry is made when the assembler encounters the Using statement.

– When a symbolic operand is encountered in an instruction requiring a storage address, the assembler uses the symbol table to obtain the 24-bit address of the symbol. The difference between that address and a promised base register value is used as the displacement in the assembled operand. (This number must not excede 12 bits - FFF16 - 409510.)


Number Systems

Background

It is important to be familiar with not only the decimal numbering system but also the binary and hexadecimal numbering systems. The last two numbering systems are used extensively in the data processing environment.

The number of digits in a given numbering system determines its base power. The value of each digit in a number is a multiple of the base power of the number. This is referred to as positional notation or positional value.

Positional Values Within Numbers

•Decimal

– Contains ten digits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 with a base power of ten. The value of the decimal number 423 is

26

power of ten. The value of the decimal number 423 is computed as:

4 2 34 x 102 + 2 x 101 + 3 x 100

400 + 20 + 3 = 423

•Binary

– Contains two digits 0 and 1 with a base power of two. The value of the binary number 10101 is computed as:

1 0 1 0 1

1 x 24 + 0 x 23 + 1 x 22 + 0 x 21 + 1 x 20

16 + 0 + 4 + 0 + 1 = 2110


Number Systems

• Hexadecimal

– Contains sixteen digits 0 through 9 and A through F with a base power of sixteen. The positional values of the digits in the hexadecimal number A423 is computed as follows:

A 4 2 3

10 x 163 + 4 x 162 + 2 x 161 + 3 x 160

40960 + 1024 + 32 + 3 = 42,01910

163 = 4096 162 = 256 161 = 16 160 = 1

27last updated 12/29/99


Number Systems

It is also important to become familiar with the representations of the first sixteen binary and hexadecimal integers since both forms are used extensively in the data processing environment.

Representations of Integers

Decimal Binary Hexadecimal

0 0000 0

1 0001 1

2 0010 2

3 0011 3

4 0100 4

28

4 0100 4

5 0101 5

6 0110 6

7 0111 7

8 1000 8

9 1001 9

10 1010 A

11 1011 B

12 1100 C

13 1101 D

14 1110 E

15 1111 F

16 10000 10


Number Systems

Binary Addition and Subtraction

• Addition is a simple matter since there are only four rules to learn: 0 + 0 = 0, 0 + 1 = 1, 1 + 0 = 1 and 1 + 1 = 10 (two in binary). In the last rule, a carry of 1 is generated and must be added to the next higher-order digit, an operation analogous to the handling of carries in decimal addition.

Some examples:

10110 10110 11111 11001

+ 1100 + 11 + 1 + 11001

---------- ---------- ----------- ----------

100010 11001 100000 110010

29

100010 11001 100000 110010

• Subtraction is also straight forward, since the only situation in which a borrow operation can arise is that of subtracting 1 from 0. A borrow of 1 is necessary when the first digit is smaller than the second.

Examples:

10110 10110 10000 10010

- 101 - 1010 - 1 - 1101

----------- ----------- ----------- -----------

10001 1100 1111 101


Number Systems

Hexadecimal Addition and Subtraction

• In addition, the sum is a single digit if its value is less than sixteen; otherwise a carry of 1 is generated.

Examples:

4 4 A DE FFF

+ 6 + A + 6 + C8 + 1

---- ----- ----- ------ -------

A E 10 1A6 1000

30

• In subtraction, a borrow of 1 (decimal sixteen ) is necessary.

Examples:

B 10 18 DE 40C

- 6 - 8 - 9 - C8 - E

------ ------- ------ ------- --------

5 8 F 16 3FE


Number Systems

Conversions of integers from one base to another

The simplest method is to utilize the Hexadecimal and Decimal Conversion Table located at the back of the Enterprise Systems Architecture/390 Reference Summary as follows:

•Decimal to Hexadecimal

– Follow the instructions on the conversion table and convert the decimal number to its hexadecimal equivalent.

•Decimal to Binary

– First convert the decimal number to its hexadecimal equivalent. Then convert each hexadecimal digit to its four-bit binary equivalent.

31

four-bit binary equivalent.

•Binary to Hexadecimal

– Convert every four consecutive binary digits to their hexadecimal equivalent starting from the right-hand digit and adding zeroes on the left, if necessary.

•Binary to Decimal

– First convert the binary number to its hexadecimal equivalent. Then convert to decimal using the conversion table.

•Hexadecimal to Decimal

– Convert the hexadecimal digits to decimal using the conversion table.

•Hexadecimal to Binary

– Convert each hexadecimal digit to its four-bit binary representation.



Formating The Source Listing

TITLE - The TITLE instruction provides for headingsfor each page of the assembly listing of thesource module.

SPACE - The SPACE instruction inserts one or moreblank lines in the listing of the source module.

EJECT - The EJECT instruction stops the printing ofthe assembly listing on the current page andcontinues printing on the next page.

END - The END statement terminates the assembly of a program. It must always be the last

32

of a program. It must always be the laststatement in the source module.

Example:

LABEL TITLE 'THIS IS PROGRAM XYZ1'

SPACE 2

EJECT

END

These and the DS/DC instructions are explained in theHLASM (High Level Assembler) Language Reference SC26-4940which can be found in the HLASM Bookshelf.



Conversion from /to EBCDIC and Packed Decimal Format

From: PACK D1(L1,B1),D2(L2,B2)

To: UNPK D1(L1,B1),D2(L2,B2)

Some guidelines:

1. The first operand is the result field. The second operand undergoes no changes.

2. L1 and L2 are lengths of the 2 operands. Each is required to be less than or equal to 16. The lengths need not be equal but care must be taken not to lose significant digits.

33

equal but care must be taken not to lose significant digits.

3. The sign contained in the low order byte in each format will be carried through the conversion.

4. No validity check is made on the two fields - so you can pack or unpack anything.

5. Neither instruction sets the condition code.

6. Processing proceeds right-to-left through the operands.


Conversion from/to Binary and Decimal Format

CVD R1,D2(X2,B2)

CVB R1,D2(X2,B2)

Some guidelines:

1. The Convert to Decimal instruction converts a 32-bit binary integer into an 8-byte packed decimal number. The binary integer must be in a register and the receiving field will be 8 bytes long.

2. The Convert to Binary instruction converts an 8-byte

34

2. The Convert to Binary instruction converts an 8-byte packed decimal number into a 32-bit binary integer in a register specified by the R1 operand. The sending field must be a valid packed decimal number.


Pack (Packed Decimal Zoned Decimal)

PACK PACKED,ZONED

Before

ZONEDPACKED

After

00 00 00 00 F1 F2 F3 C4

35

00 01 23 4C

After

ZONEDPACKED

F1 F2 F3 C4



PACK PACKED(3),ZONED(4)

Before

ZONEDPACKED

After

00 00 00 00 F1 F2 F3 C4

36

After

ZONEDPACKED

01 23 4C 00 F1 F2 F3 C4



PACK ZONED,ZONED

Before:

ZONED

After

F1 F2 F3 C4

37

After:

ZONED

00 01 23 4C


Conversion from Packed Decimal Format to Binary

CVB R6,PKDDBL

Before

After

REG 6

00 00 00 00 00 00 10 1C

00 00 00 00 00 00 10 1C

PKDDBL

00 F1 88 08

00 00 00 65

38

REG 6

00 00 00 00 00 00 10 1C

PKDDBL

00 00 00 65


Multiply Register

MR R6,R3

Before:

REG 6

00 00 01 23

REG 7

21 19 1CFA

39

00 00 00 00 00 00 04 8C

After:

REG 6 REG 7

00 00 00 04

REG 3

00 00 00 04

REG 3


Conversion from Binary Format to Decimal

CVD R6,PKDDBL

Before:

After:

REG 6 PKDDBL

00 00 00 64

00 00 00 64

00 10 20 30 40 50 6F FF

00 00 00 00 00 00 10 0C

40

REG 6 PKDDBL

00 00 00 64 00 00 00 00 00 00 10 0C


UNPK (Zoned Decimal Packed Decimal)

UNPK ZONED,PACKED

Before:

ZONED

After:

PACKED

F1 F2 F3 C4 45 6D

41

After:

ZONED PACKED

F0 F4 F5 D6 45 6D



UNPK NOTBIG,TOOBIG

Before:

NOTBIG

After:

TOOBIG

01 23 45 6C

01 23 45 6C

00 00 00 00

F3 F4 F5 C6

42

Truncation of significant digits occurs. The receiving field was not large enough to receive all digits, but processing continues with, perhaps, undesireable results.

NOTBIG TOOBIG

01 23 45 6CF3 F4 F5 C6




UNPK PACKED,PACKED

Before:

ZONED

After:

01 23 45 6C

43

Do not Unpack a field into itself!!

ZONED

?? ?? ?? C6



Move Zone

This instruction copies only the left-most 4 bits of each of thedesignated bytes of the source fields into the destination fields.The right-most 4 bits are not altered.

Format: MVZ D1(L1,B1),D2(B2)

SAVE DC Z'1234'

MVZ SAVE+3(1),SAVE+2

SAVE before:

44

SAVE before:

F1 F2 F3 C4

SAVE after:

F1 F2 F3 F4


EXERCISE #2

PROGRAM 2.

Input: rate hours name.

Message: b@hhrrname+

name is max 15 characters

Process: calculate gross pay; rate x hours.

Input and output numbers are character format.

Arithmetic is in binary format.

45

Arithmetic is in binary format.

Output: name gross pay.

Name occupies first 15 positions starting in position 1.

Gross salary starts in 3rd position after name.

Gross salary has no editing characters ($ , .).


46


Define Constants - Format

{LABEL} DC {D} T {LN} 'CONSTANT'

{LABEL} - Label or name

DC - Operation code

{D} - Duplication factor

T - Type (B, C, Z, P, H, F, D, X, A, V)

{LN} - Length

'CONSTANT' - Actual constant value (nominal

value)

– Items within brackets are optional.

47

– Items within brackets are optional.

– Constant data, within single apostrophes, must be coded.

– Maximum length of 256 for define constants.


Types of Constants for DC Instructions

Type

Code Meaning Alignment Comments

C Text or Byte Each character is

characters converted to its 8-bit

EBCDIC representation.

The characters are stored

in consecutive bytes.

Padding occurs with

blanks in unoccupied

bytes to the right.

Truncation may occur, on

48

Truncation may occur, on

the right.

F Binary Fullword The number is converted

Integer to its 32-bit binary integer

(4 bytes) format (including sign).

Max value 2,147,483,647

H Binary Halfword The number is converted

integer to its 16-bit binary integer

(2 bytes) format (including sign).

Max value 32,767

D Binary Doubleword Approximate max value:

number 7.2 x 10(75). Floating point

(8 bytes) constants not used in TPF.



Type


P Decimal Byte Each digit is converted tonumbers a 4-bit binary integer. (packed) Max of 31 digits. Decimal

point is ignored, e.g.

P'3.5' is the same as P'35'.

Zero fill with 4-bit zeroes

to the left and truncation

is on the left.

Z Decimal Byte Each digit is converted to

numbers an 8-bit EBCDIC format,

49

numbers an 8-bit EBCDIC format,

(zoned) max of 16 digits. The

decimal point is ignored

as in packed format. Zero

fill with character zeroes

(F0) to the left and

truncation is on the left.

X Hexadecimal Byte Each digit must be one of

the 16 hex digits and will

be represented by a 4-bit

binary number. Decimal

point not allowed. Zero

fill left, truncation on left.



Type


B Bit data Byte The bits are represented as

given in the DC statement

8 bits per byte. Zero fill to

the left and truncation on

the left.

A Address Fullword The value of the symbol as

constant a binary integer will be

be stored.

V Address Fullword Space is reserved for an

50

V Address Fullword Space is reserved for an

constant external address.


Define Constant - Object Listing

LOC OBJECT CODE ADDR1 ADDR2 STMT SOURCE STATEMENT

3 **

4 ** CONSTANTS OF

ZERO

5 **

000000 0000000000000000 6 DOUBLE DC D'0'

000008 00 7 HEX DC X'0'

000009 000000

00000C 00000000 8 FULLWORD DC F'0'

000010 0000 9 HALFWORD DC H'0'

000012 0C 10 DECIMAL DC P'0'

000013 00 11 BINARY DC B'0'

000014 F0 12 CHAR DC C'0'

000015 C0 13 ZONED DC Z'0'

51

14 **

15 ** CONSTANTS OF ONE

16 **

000016 01 17 AHEX DC X'1'

000017 00

000018 00000001 18 AFULL DC F'1'

00001C 0001 19 AHALF DC H'1'

00001E 1C 20 ADEC DC P'1'

00001F 01 21 ABIN DC B'1'

000020 F1 22 ACHAR DC C'1'

000021 C1 23 AZONE DC Z'1'


Define Constant - Object Listing

LOC OBJECT CODE ADDR1 ADDR2 STMT SOURCE STATEMENT

24 **

25 ** CONSTANTS OF -1

26 **

00002E 0000

000030 FFFFFFFF 27 BFULL DC F'-1'

000034 FFFF 28 BHALF DC H'-1'

000036 1D 29 BDEC DC P'-1'

000037 60F1 30 BCHAR DC C'-1'

000038 D1 31 BZONE DC Z'-1'

32 **

33 ** CONSTANTS OF ONE

34 ** WITH PADDING

35 **

52

35 **

000039 000000000000001C 36 CDEC DC PL8'1'

000041 F140404040404040 37 CCHAR DC CL8'1'

000049 F0F0F0F0F0F0F0C1 38 CZONE DC ZL8'1'

39 END


Define Constant - Halfword Data

HALF1 DC H'+18'

HALF1

HALF2 DC H'18'

HALF2

HALF3 DC H'-18'

00 12

00 12

53

HALF3 DC H'-18'

HALF3

HALF4 DC 2H'4'

HALF4

FF EE

00 04 00 04


Define Constant - Fullword Data

FULLWD1 DC F'+32'

FULLWD1

FULLWD2 DC F'32'

FULLWD2

FULLWD3 DC F'-32'

00 00 00 20

00 00 00 20

54

FULLWD3 DC F'-32'

FULLWD3

FULLWD4 DC 2F'32'

FULLWD4

FF FF FF E0

00 00 00 20

00 00 00 20


Multiply Fullword

M R6,FULL

Before:

REG 6

00 00 00 10

REG 7

N'T CA REDO

55

00 00 00 00 00 00 00 40

After:

REG 6 REG 7

00 00 00 04

FULL

00 00 00 04

FULL


Multiply Halfword

MH R5,HALF

After:

00 00 00 0A 00 03

Before:

REG 5 HALF

56

00 00 1E 00 03

REG 5 HALF

00


Add Register

AR R3,R4

After:

01 A2 30 11 02 13 75 A6

Before:

REG 3 REG 4

57

03 B5 A5 B7 02 13 75 A6

REG 3 REG 4


Subtract Register

SR R3,R4

00 00 00 39 00 00 00 12

Before:

REG 3 REG 4

58

00 00 00 27 00 00 00 12

After:

REG 3 REG 4


Divide Register

DR R6,R2

Before:

REG 6

00 00 00 2E

REG 7

00 00 00 08

00 00 0000

59

00 00 00 06 00 00 00 05

After:

REG 6 (REM.) REG 7 (QUOTIENT)

00 00 00 08

REG 2

00 00 00 08

REG 2


Add Fullword

A R3,FULL

After:

00 00 00 06 00 00 00 04

Before:

REG 3 FULL

60

00 00 00 0A 00 00 00 04

REG 3 FULL


Subtract Fullword

S R3,FULL

00 00 00 0A 00 00 00 C8

Before:

REG 3 (+10) FULL (+200)

After:

61

00 00 00 C8

After:

REG 3 (-190) FULL (+200)

42FFFFFF


Divide Fullword

D R6,FULL

Before:

REG 6

00 00 36 92

REG 7

00 00 00 03

00 00 0000

62

00 00 00 02 00 00 12 30

After:

REG 6 (REM.) REG 7 (QUOTIENT)

00 00 00 03

FULL

FULL


Divide Fullword

Remember that the machine will look at all 8 bytes of the two registers as the dividend. Therefore, you must make certain that the sign bit (bit 0 of the 64 bits) reflects the true sign of the number.

You must also propagate the sign of the number through the padding bits in the even register. This is a very good way of doing that (presuming the dividend does not exceed a fullword):

M 6,=F'1'

63

Regardless of the value in the odd register, the dividend now occupies registers 6 and 7 with the correct sign and padding.


Add Halfword

AH R3,HALF

After:

00 00 00 0A 00 03

Before:

REG 3 HALF

64

00 00 00 0D 00 03

REG 3 HALF


Add Halfword

AH R3,HALFNEG

After:

00 00 00 0A FF F1

Before:

REG 3 (+10) HALFNEG (-15)

65

FF FF FB FF F1

REG 3 (-5) HALFNEG (-15)

FF


Subtract Halfword

SH R3,HALF

After:

00 00 00 0A 00 03

Before:

REG 3 HALF

66

00 00 00 07 00 03

REG 3 HALF


Load Register

LR R4,R5

Reg 4 before: Reg 5 before:

00 81 34 77 00 00 12 11

Reg 4 after: Reg 5 after:

00 00 12 11 00 00 12 11

67

00 00 12 11 00 00 12 11


Load Halfword

LH R7,TWOBYTS

Reg 7 before: TWOBYTS

before:

00 12 33 F0 00 48

Reg 7 after: TWOBYTS after:

68

00 00 00 48 00 48

IBM Assembly Language Coding (ALC) Part 1

Documents

maximum operand size

machine instructions

instruction address

main storage

condition code

updated 12 29 99

storage operand

code comments