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I2C & SPI Master Synchronous Serial Port ECE Senior Design 15 March 2017
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I2C & SPI - seniordesignlab.comseniordesignlab.com/sdl_docs/EE496/PIC_MSSP.pdf · I2C & SPI Master Synchronous ... •Master / Slave (Multi-Master) •Master Initiates All Communication

Mar 30, 2018

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Page 1: I2C & SPI - seniordesignlab.comseniordesignlab.com/sdl_docs/EE496/PIC_MSSP.pdf · I2C & SPI Master Synchronous ... •Master / Slave (Multi-Master) •Master Initiates All Communication

I2C & SPIMaster Synchronous

Serial Port

ECE Senior Design

15 March 2017

Page 2: I2C & SPI - seniordesignlab.comseniordesignlab.com/sdl_docs/EE496/PIC_MSSP.pdf · I2C & SPI Master Synchronous ... •Master / Slave (Multi-Master) •Master Initiates All Communication

I2C – Inter-Integrated Circuit

• Developed by Philips (NXP) in 1982

• 2 Wire Synchronous Serial (Half-Duplex)

• Bidirectional Open Collector Bus

• Master / Slave (Multi-Master)

• Master Initiates All Communication

• Up to 3.2Mb/s (100kb/s & 400kb/s common)

• Unique 7b address for Each Device

Page 3: I2C & SPI - seniordesignlab.comseniordesignlab.com/sdl_docs/EE496/PIC_MSSP.pdf · I2C & SPI Master Synchronous ... •Master / Slave (Multi-Master) •Master Initiates All Communication

I2C Bus Connection

Page 4: I2C & SPI - seniordesignlab.comseniordesignlab.com/sdl_docs/EE496/PIC_MSSP.pdf · I2C & SPI Master Synchronous ... •Master / Slave (Multi-Master) •Master Initiates All Communication

I2C Data Transfer

Page 5: I2C & SPI - seniordesignlab.comseniordesignlab.com/sdl_docs/EE496/PIC_MSSP.pdf · I2C & SPI Master Synchronous ... •Master / Slave (Multi-Master) •Master Initiates All Communication

SPI – Serial Peripheral Interface

• Developed by Motorola (NXP) in 1987

• 3 Wire + nSS Serial (Full-Duplex)

• Master / Slave Relationship

• Operates as a Simple 16b Shift Register

• Capable of Very High Speed Data Transfers

• 4 Modes for Clock Polarity and Phase

• No Formal Standard (many variations)

Page 6: I2C & SPI - seniordesignlab.comseniordesignlab.com/sdl_docs/EE496/PIC_MSSP.pdf · I2C & SPI Master Synchronous ... •Master / Slave (Multi-Master) •Master Initiates All Communication

SPI Bus Connection

Page 7: I2C & SPI - seniordesignlab.comseniordesignlab.com/sdl_docs/EE496/PIC_MSSP.pdf · I2C & SPI Master Synchronous ... •Master / Slave (Multi-Master) •Master Initiates All Communication

SPI – Shift Register

Page 8: I2C & SPI - seniordesignlab.comseniordesignlab.com/sdl_docs/EE496/PIC_MSSP.pdf · I2C & SPI Master Synchronous ... •Master / Slave (Multi-Master) •Master Initiates All Communication

SPI – Data Transfer

Page 9: I2C & SPI - seniordesignlab.comseniordesignlab.com/sdl_docs/EE496/PIC_MSSP.pdf · I2C & SPI Master Synchronous ... •Master / Slave (Multi-Master) •Master Initiates All Communication

SPI Clock Polarity and Phase

SPI Mode Clock Polarity Clock Phase

0 0 0

1 0 1

2 1 0

3 1 1

Page 10: I2C & SPI - seniordesignlab.comseniordesignlab.com/sdl_docs/EE496/PIC_MSSP.pdf · I2C & SPI Master Synchronous ... •Master / Slave (Multi-Master) •Master Initiates All Communication

MSSP (SPI MODE)

SSP1STAT – Status

SSP1CON1 – Control 1

SSP1CON3 – Control 3

(slave settings)

SSP1BUF – Data Buffer

SSP1ADD – Address

(slave settings)

SSP1SR – Shift Register

(not accessible)

Page 11: I2C & SPI - seniordesignlab.comseniordesignlab.com/sdl_docs/EE496/PIC_MSSP.pdf · I2C & SPI Master Synchronous ... •Master / Slave (Multi-Master) •Master Initiates All Communication

Buffer Full Status Flag (Exchange Done)

Set Active Clock Edge

Set Input Sampling

Page 12: I2C & SPI - seniordesignlab.comseniordesignlab.com/sdl_docs/EE496/PIC_MSSP.pdf · I2C & SPI Master Synchronous ... •Master / Slave (Multi-Master) •Master Initiates All Communication

Master Mode & Bus Speed

Set Clock Polarity

Enable SPI

Clear WCOL

Page 13: I2C & SPI - seniordesignlab.comseniordesignlab.com/sdl_docs/EE496/PIC_MSSP.pdf · I2C & SPI Master Synchronous ... •Master / Slave (Multi-Master) •Master Initiates All Communication

MCP4151 – Digital Potentiometer

• 8-bit: 256 Resistors (257 Steps)

• SPI Serial Interface (10 MHz)

• 1.8V to 5.5V Operation

• SDI/SDO Multiplexed