Hsinchu, Taiwan December 6, 2000 1 International Technology Roadmap for Semiconductors (ITRS 2000) Assembly & Packaging International Technical Working.

Hsinchu, Taiwan December 6, 2000

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International Technology Roadmap

for Semiconductors (ITRS 2000)

Assembly & Packaging

International Technical Working GroupDecember 6, 2000

Hsinchu, Taiwan December 6, 2000

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2000 Changes• Cost/pin

– Hand Held, Cost Performance• upper range costs were lowered

– Hand Held, Cost Performance, Harsh, Memory• cost labeled as “No Known Solution” due to increases

which will be driven by new environmental materials

– Memory for 2001• determine how to address memory categories for 2001

update– deal with increasing complexity

– incorporate performance memory

Hsinchu, Taiwan December 6, 2000

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2000 Changes• Chip Size

– incorporated ORTC data• cost-performance have minor changes• high performance decreases 20-30% • memory increases 20-30%

– determine how to address small chip issues that are highly cost sensitive (RF/mixed signal) in 2001

• Power– High Performance-minor increases

• Core Voltage– Harsh- more rapid migration to 1.8V

Hsinchu, Taiwan December 6, 2000

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Table 59a Assembly & Packaging Technology Requirements—Near TermYEAR

TECHNOLOGY NODE

1999180 nm

2000 2001 2002130 nm

2003 2004 2005100 nm

Cost (Cents/ Pin) [A]

Low cost 0.40–0.90 0.38–0.86 0.36-0.81 0.34-0.77 0.33-0.73 0.31-0.70 0.29-0.66

Hand-held 0.50–1.30 0.48-1.00 0.45-0.95 0.43-0.90 0.41-0.86 0.39-0.82 0.37-0.78

Cost-performance 0.90–1.90 0.86-1.40 0.81-1.33 0.77-1.26 0.73-1.20 0.70-1.14 0.66-1.08

High-performance 3.10 2.95 2.80 2.66 2.52 2.40 2.28

Harsh 0.50–1.00 0.48–0.95 0.45–0.90 0.13-0.86 0.41-0.81 0.39-0.77 0.37-0.74

Memory 0.40–1.90 0.38–1.71 0.36–1.54 0.34–1.39 0.33–1.25 0.31–1.12 0.29–1.01

Chip Size (mm2)

Low cost 53 55 57 59 61 63 65

Hand-held 53 55 57 59 61 63 65

Cost-performance 170 170 170 178 186 195 204

High-performance 310 310 310 325 340 356 372

Harsh 53 55 57 59 61 63 65

Memory 131 129 127 141 157 175 147

Power: Single-Chip Package (Watts) [B]

Low cost n/a n/a N/a n/a n/a n/a n/a

Hand-held 1.4 1.7 2.0 2.1 2.3 2.4 2.6

Cost-performance 48 54 61 75 81 88 96

High-performance 90 108 130 140 150 160 170

Harsh 14 14 14 14 14 14 14

Memory 0.8 1.0 1.2 1.4 1.6 1.8 2

Core Voltage (Volts)

Low cost 1.8 1.8 1.5 1.5 1.2 1.2 1.1

Hand-held 1.5 1.5 1.2 1.2 0.9 0.9 0.8

Cost-performance 1.8 1.8 1.5 1.5 1.2 1.2 1.1

High-performance 1.8 1.8 1.5 1.5 1.2 1.2 1.1

Harsh 5.0 3.3 3.3 3.3 2.5 1.8 1.8

Memory 1.8 1.8 1.5 1.5 1.2 1.2 1.1

Hsinchu, Taiwan December 6, 2000

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2000 Changes• Pincount

– Harsh- verify high end of range starting in 2000- check Europe, Japan, U.S.

– High Performance- reconcile w/ Jisso

• Package Profile– determine how to address stacked chips and

thin/flexible packaging in 2001

Hsinchu, Taiwan December 6, 2000

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2000 Changes• Performance on chip

– Cost Performance , High Performance- matched to Design ITWG values

– Memory- accelerated 166 and 200Mhz introductions for system memory and peripheral bus speed

– review all other categories/ reconcile w/ Jisso

Hsinchu, Taiwan December 6, 2000

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2000 Changes• Performance chip to board

– Cost Performance- accelerated 166 and 200 Mhz introductions consistent w/ Memory changes

– High performance- numbers look to be in error- should be 50% of on chip numbers ?!?!

– need a new way to deal with game products (consider making it the high end of Low Cost) in 2001

Hsinchu, Taiwan December 6, 2000

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2000 Changes• Junction Temperature

– determine how to address need for 150 C junction for in cabin automotive application (add to Harsh or change another category in 2001 update)

– Hand Held- determine how to reconcile w/ Jisso roadmap which shows 100C for 2000

• Operating Temperature– High Performance- need to reconcile w/Jisso– Hand Held- need to reconcile w/Jisso

Hsinchu, Taiwan December 6, 2000

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Table 59a Assembly & Packaging Technology Requirements—Near Term (continued)YEAR

TECHNOLOGY NODE

1999180 nm

2000 2001 2002130 nm

2003 2004 2005100 nm

Performance: On-Chip (MHz)

Low cost 300 350 415 460 510 570 633

Hand-held 300 350 415 460 510 570 633

Cost-performance 600 693 800 890 989 1100 1225

High-performance 1200 1386 1600 1724 1857 2000 2155

Harsh 25 40 60 60 60 60 60

Memory(D/SRAM)

166/346 166/400 200/445 200/494 200/550 200/612

Performance: Chip-to-Board for Peripheral Buses (MHz)

Low cost 75 75 100 100 100 100 100

Hand-held 75 75 100 100 100 100 100

Cost-performance[D]

133/300 166/346 166/400 200/445 200/494 200/550 200/612

High-performance[E]

480 652 885 932 982 1035 1090

Harsh 25 40 60 60 60 60 60

Memory(D/SRAM) [D]

133/300 166/346 166/400 200/445 200/494 200/550 200/612

J unction Temperature Maximum (°C) [F]

Low cost 125 125 125 125 125 125 125

Hand-held 115 100 100 100 100 100 100

Cost-performance 100 95 90 85 85 85 85

High-performance 100 95 90 85 85 85 85

Harsh 155 155 155 155 155 155 175

Memory 100 100 100 100 100 100 100

Operating Temperature Extreme: Ambient (°C) [F]

Low cost 55 55 55 55 55 55 55

Hand-held 55 55 55 55 55 55 55

Cost-performance 45 45 45 45 45 45 45

High-performance 45 45 45 45 45 45 45

Harsh -40 to 150 -40 to 150 -40 to 150 -40 to 150 -40 to 150 -40 to 150 -40 to 170

Memory 55 55 55 55 55 55 55

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Key Issues for 2001• Market sector redefinition• cost of new environmentally friendly materials• MEMS

• sensors (eg. Pressure and acceleration)• relays (eg. Cell phone transmit/receive switch)

• Optical interconnect• SCP, SIP, MCP,MCM, substrate distinctions• Performance memory• Gaming products- where do they fit?• Stacked/ultra thin chip packaging• Small chip issues (RF/mixed signal)

Hsinchu, Taiwan December 6, 2000

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Assembly & Packaging Potential Solutions

Hsinchu, Taiwan December 6, 2000

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2000 Changes• Chip to Next Level Interconnect

– aggressive acceleration of wire bond pitch2001 2002 2003 2004 2005

ball bond (um) 45 35 30 25 20wedge (um) 40 35 30 25 20– some acceleration of area array flip chip pitchesarea array (um) 175 175 150 150 130peripheral (um) 150 130 120 110 100– removed TAB– add Flip Chip on Tape/Chip on Flex category

Hsinchu, Taiwan December 6, 2000

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Table 60 Current L imits of 63Sn/ 37Pb Flip Chip Solder Bumps

Current Limits for 100,000 hour MTTF at Average BumpTemperatures of

Bump Pitch Passivation Opening 100C250 m 85m 150 mA200 m 80 m 130 mA150 m 65 m 90 mA

Note: The electromigration limits for 63Sn/Pb solder is still being determined for junction temperatures in the range of 85 to 115C. Thedata represented in Table 60 is a 2x improvement over the 1999 roadmap. A more complete update will be provided in the 2001 roadmap .

Table 61a Chip-to-Next Level Interconnect Potential Solutions—Near TermYEAR

TECHNOLOGY NODE

1999180 nm

2000 2001 2002130 nm

2003 2004 2005100 nm

Chip Interconnect Pitch (µm)

Wire bond—ball 50 50 45 35 30 25 20

Wire bond—wedge 45 45 40 35 30 25 20

Flip Chip on Tape 50 50 40 40 40 40 30

Flip chip (areaarray) for cost-performance andhigh-performance

200 200 175 175 150 150 130

Flip chip forhandheld, lowcost, and harsh

180 165 150 130 120 110 100

Note: The Chip Interconnect Pitch for area array flip chip in cost-performance and high-performancemarket segments have been changed from those of ITRS 1999. The corresponding changes in Table 65 willbe provided in the 2001 Roadmap.

Chip Interconnect Solutions