Hsinchu, Taiwan December 6, 2000 1 International Technology Roadmap for Semiconductors (ITRS 2000) Assembly & Packaging International Technical Working.

Hsinchu, Taiwan December 6, 2000

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International Technology Roadmap

for Semiconductors (ITRS 2000)

Assembly & Packaging

International Technical Working GroupDecember 6, 2000


ITWG MEMBERSHIPITWG MEMBERSHIP EUROPE Jean-Pierre Moscicki, STMicroelectronics Bernd Roemer, Infineon

Co van Veen, Philips TAIWAN Ho-Ming Tong, First Int’l. Computer

Enboa Wu, ERSO/ITRI KOREA S.Y. Kang, Samsung

H.S. Chun, Hyundai

JAPAN Seiji Hamano, Fujitsu Henry Utsunomiya, MITI Consultant

U.S. Alex Oscilowski, Kulicke & Soffa Bill Bottoms, 3rd Millenium Test Solutions

John Prince, University of Arizona

Special Topics Jurgen Wolf, FraunhoferChi Shih Chang, Kulicke & Soffa


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• System -on-a-chip (SoC) Packaging• Wafer Level Packaging • Mixed-signal and Radio Frequency Packaging• Multi-Chip Packaging (MCP)• Single Chip Packages (SCP)• Flip Chip Interconnect (Direct Chip Attach (DCA)• Bonding/Chip/Package/Substrate Design• Chip Carrier Substrates• Thermal Power/Ground Management• Electrical/Performance Characterization• Issues to be resolved in 2001:

– how to distinguish between single chip packages, few chip packages/modules, MCP, and substrates

Scope


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• The ITRS AP roadmap and the NEMI packaging roadmap have been linked since 1996– The ITRS roadmap provides much of the content for the NEMI

packaging roadmap– Both roadmaps were updated in 2000– A majority of DTWG members are common

• The ITRS and the Jisso Roadmaps are closely coordinated– The Jisso roadmap provides valuable chip, package, and board level

data– The Jisso chair and co-chair are ITWG members

Compatibility Between Roadmaps


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Typical Products by SectorMarket Sectors Products

Low Cost Consumer, disk drives,displays (Play Station II ?)

Hand Held Battery powered:camcorders, cell phones,PDAs

Cost-performance Notebooks, desktop PCs,telecom line cards

High-performance Servers, high endworkstations, avionics,military

Harsh Automotive under hood,some military and telecom

Memory flash, SRAM, DRAM (newcategories needed 2001)

Note: Major review of sectors planned for 2001 update


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Overall Industry Factors• Communications markets, especially wireless, will equal and

likely surpass PCs as the predominant end use market over the next 5 years

• chip and board level assembly are converging- this drives the need for amore comprehensive approach to technology and cost

• outsourcing continues to accelerate, and technology development continues to shift from OEMs to EMS providers and suppliers

• materials continue to dominate the cost of chip assembly and packaging


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Chip Packaging Factors• Area array packages continue to experience CAGR 2X

industry average• CSPs are growing faster than BGAs and are driving

cost and technology (thin die,<= 0-.5mm ball pitch, etc…)

• CSPs from Wafer Level Packaging (WLP) can shift the chip packaging paradigm and are limited by a lack of wafer level test/burn in capability (memory)

• chip interconnect will continue to drive packaging densification for all chip to next level connections (TAB, Wire bond and Flip Chip)

• chip interconnect is limited by substrate, probe, and encapsulation capability, all of which drive packaging cost


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• Pb free solder requirements are driving requalification of components, equipment, and materials at higher processing temperatures

• Elimination of Sb and Br from encapsulants and substrates requires the selection and qualification of suitable replacement materials

• Life cycle product management and “take back” requirements could drive changes in packaging design and material selection

These factors are becoming requirements for doing business in Japan and Europe, could be differentiators in the U.S and have major cost implications

Environmental Factors


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Environmental Factor Cost Impact• Low Cost and Memory segment Cost/pin have No

Known Solutions beginning in 2001 due to environmental factors for most aggressive targets:– 10-15% cost Increases anticipated to accommodate :

• Pb free solders• Sb and Br free mold compounds and substrates

– new materials solutions should achieve roadmap cost targets in 12-18 months


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Table 58 Assembly & Packaging Difficult Challenges

FIVE DIFFICULT CHALLENGES

100 nm / THROUGH 2005

SUMMARY OF ISSUES

Improved organic substrates for high I/O area array flip chip Tg compatible with Pb and Pb free solder processing

r approaching 2.0

Increased wireability at low cost

Lower CTE* approaching 6.0 ppm/CLow moisture absorption

High density substrate test

Improved underfills for high I/O area array flip chip

Reliability limits of flip chip on organic substrates

Improved manufacturability (fast dispense/cure), betterinterface adhesion, lower moisture absorption, flow fordense bump pitch

Reliability up to 170°C for automotiveComprehensive parametric knowledge of packaging

components (chip size, underfill, substrate, heat sink,UBM/bump**)

Coordinated design tools and simulators to address chip,package, and substrate complexity

Physical designThermal/thermo-mechanicalElectrical (power disturbs, EMI†, signal integrity associated

w/higher frequency/current, lower voltage, mixed-signalco-design)

Commercial EDA‡ supplier support

System reliability impact of Cu/low on packaging Bump and underfill technology to assure low dielectricintegrity

Mechanical strength of dielectricsInterfacial adhesion

Cost effective cooling for cost-performance and high-performance sectors

Meeting 40°C above ambient temperatureLocalized on-chip power density

Pb, Sb, and Br free packaging materials Major issue is meeting new requirements includinghigher reflow temperatures at the present cost goals.

Difficult Challenges


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Assembly & Packaging Technology Requirements


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2000 Changes• Cost/pin

– Hand Held, Cost Performance• upper range costs were lowered

– Hand Held, Cost Performance, Harsh, Memory• cost labeled as “No Known Solution” due to increases

which will be driven by new environmental materials

– Memory for 2001• determine how to address memory categories for 2001

update– deal with increasing complexity

– incorporate performance memory


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2000 Changes• Chip Size

– incorporated ORTC data• cost-performance have minor changes• high performance decreases 20-30% • memory increases 20-30%

– determine how to address small chip issues that are highly cost sensitive (RF/mixed signal) in 2001

• Power– High Performance-minor increases

• Core Voltage– Harsh- more rapid migration to 1.8V


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Table 59a Assembly & Packaging Technology Requirements—Near TermYEAR

TECHNOLOGY NODE

1999180 nm

2000 2001 2002130 nm

2003 2004 2005100 nm

Cost (Cents/ Pin) [A]

Low cost 0.40–0.90 0.38–0.86 0.36-0.81 0.34-0.77 0.33-0.73 0.31-0.70 0.29-0.66

Hand-held 0.50–1.30 0.48-1.00 0.45-0.95 0.43-0.90 0.41-0.86 0.39-0.82 0.37-0.78

Cost-performance 0.90–1.90 0.86-1.40 0.81-1.33 0.77-1.26 0.73-1.20 0.70-1.14 0.66-1.08

High-performance 3.10 2.95 2.80 2.66 2.52 2.40 2.28

Harsh 0.50–1.00 0.48–0.95 0.45–0.90 0.13-0.86 0.41-0.81 0.39-0.77 0.37-0.74

Memory 0.40–1.90 0.38–1.71 0.36–1.54 0.34–1.39 0.33–1.25 0.31–1.12 0.29–1.01

Chip Size (mm2)

Low cost 53 55 57 59 61 63 65

Hand-held 53 55 57 59 61 63 65

Cost-performance 170 170 170 178 186 195 204

High-performance 310 310 310 325 340 356 372

Harsh 53 55 57 59 61 63 65

Memory 131 129 127 141 157 175 147

Power: Single-Chip Package (Watts) [B]

Low cost n/a n/a N/a n/a n/a n/a n/a

Hand-held 1.4 1.7 2.0 2.1 2.3 2.4 2.6



Harsh 14 14 14 14 14 14 14

Memory 0.8 1.0 1.2 1.4 1.6 1.8 2

Core Voltage (Volts)

Low cost 1.8 1.8 1.5 1.5 1.2 1.2 1.1

Hand-held 1.5 1.5 1.2 1.2 0.9 0.9 0.8

Cost-performance 1.8 1.8 1.5 1.5 1.2 1.2 1.1

High-performance 1.8 1.8 1.5 1.5 1.2 1.2 1.1

Harsh 5.0 3.3 3.3 3.3 2.5 1.8 1.8

Memory 1.8 1.8 1.5 1.5 1.2 1.2 1.1


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2000 Changes• Pincount

– no changes

• Package Profile– determine how to address stacked chips and thin/flexible

packaging in 2001

• Performance on chip– Cost Performance , High Performance- matched to Design

ITWG values– Memory- accelerated 166 and 200Mhz introductions for system

memory and peripheral bus speed


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2000 Changes

• Performance chip to board– Cost Performance- accelerated 166 and 200 Mhz

introductions consistent w/ Memory changes– need a new way to deal with game products (consider

making it the high end of Low Cost) in 2001– new algorithm needed to relate chip to board and on

chip performance targets in 2001 update


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2000 Changes

• Junction Temperature– determine how to address need for 150 C junction for in

cabin automotive application (add to Harsh or change another category in 2001 update)

• Operating Temperature– no changes


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Table 59a Assembly & Packaging Technology Requirements—Near Term (continued)YEAR

TECHNOLOGY NODE

1999180 nm

2000 2001 2002130 nm

2003 2004 2005100 nm

Performance: On-Chip (MHz)

Low cost 300 350 415 460 510 570 633

Hand-held 300 350 415 460 510 570 633



Harsh 25 40 60 60 60 60 60

Memory(D/SRAM)

166/346 166/400 200/445 200/494 200/550 200/612

Performance: Chip-to-Board for Peripheral Buses (MHz)

Low cost 75 75 100 100 100 100 100

Hand-held 75 75 100 100 100 100 100

Cost-performance[D]

133/300 166/346 166/400 200/445 200/494 200/550 200/612

High-performance[E]

480 652 885 932 982 1035 1090

Harsh 25 40 60 60 60 60 60

Memory(D/SRAM) [D]

133/300 166/346 166/400 200/445 200/494 200/550 200/612

J unction Temperature Maximum (°C) [F]

Low cost 125 125 125 125 125 125 125

Hand-held 115 100 100 100 100 100 100



Harsh 155 155 155 155 155 155 175

Memory 100 100 100 100 100 100 100

Operating Temperature Extreme: Ambient (°C) [F]

Low cost 55 55 55 55 55 55 55

Hand-held 55 55 55 55 55 55 55



Harsh -40 to 150 -40 to 150 -40 to 150 -40 to 150 -40 to 150 -40 to 150 -40 to 170

Memory 55 55 55 55 55 55 55


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Key Issues for 2001• Market sector redefinition• cost of new environmentally friendly materials• MEMS

• sensors (eg. Pressure and acceleration)• relays (eg. Cell phone transmit/receive switch)

• Optical interconnect• SCP, SIP, MCP,MCM, substrate distinctions• Performance memory• Gaming products- where do they fit?• Stacked/ultra thin chip packaging• Small chip issues (RF/mixed signal)


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Assembly & Packaging Potential Solutions


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2000 Changes• Chip to Next Level Interconnect

– aggressive acceleration of wire bond pitch2001 2002 2003 2004 2005

ball bond (um) 45 35 30 25 20wedge (um) 40 35 30 25 20– some acceleration of area array flip chip pitchesarea array (um) 175 175 150 150 130peripheral (um) 150 130 120 110 100– removed TAB-revisit in 2001 based on JISSO input– add Flip Chip on Tape/Chip on Flex category


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Table 60 Current L imits of 63Sn/ 37Pb Flip Chip Solder Bumps

Current Limits for 100,000 hour MTTF at Average BumpTemperatures of

Bump Pitch Passivation Opening 100C250 m 85m 150 mA200 m 80 m 130 mA150 m 65 m 90 mA

Note: The electromigration limits for 63Sn/Pb solder is still being determined for junction temperatures in the range of 85 to 115C. Thedata represented in Table 60 is a 2x improvement over the 1999 roadmap. A more complete update will be provided in the 2001 roadmap .

Table 61a Chip-to-Next Level Interconnect Potential Solutions—Near TermYEAR

TECHNOLOGY NODE

1999180 nm

2000 2001 2002130 nm

2003 2004 2005100 nm

Chip Interconnect Pitch (µm)

Wire bond—ball 50 50 45 35 30 25 20

Wire bond—wedge 45 45 40 35 30 25 20

Flip Chip on Tape 50 50 40 40 40 40 30

Flip chip (areaarray) for cost-performance andhigh-performance

200 200 175 175 150 150 130

Flip chip forhandheld, lowcost, and harsh

180 165 150 130 120 110 100

Note: The Chip Interconnect Pitch for area array flip chip in cost-performance and high-performancemarket segments have been changed from those of ITRS 1999. The corresponding changes in Table 65 willbe provided in the 2001 Roadmap.

Chip Interconnect Solutions


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Assembly & Packaging Cross TWG Opportunities


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Cross TWG Opportunities for 2001• Test

– AP TWG should:• add system level thermal modeling statement to text to address

integrated AP/Test/Design issues• discuss how to push industry to deliver thermal models for standard

package types• add thermal management recommendations• review package electrical modeling section for high frequency with

Design– Test TWG should

• address pitch reduction issues for contactors• address 1+ Ghz issues with Design including package electrical

models


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Cross TWG Opportunities for 2001

• Factory Integration– the FI TWG agreed to add needs and potential

solutions for AP and Test to provide• unit level traceability

• mis-processing avoidance

• cycle time reduction

• improved equipment utilization


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Cross TWG Opportunities for 2001 • Interconnect

– develop a common section in both TWGs to address materials and integration issues

• Pete Elenius and Jurgen Wolf for AP• Bob Gefken from Interconnect

– incorporate specific needs and solutions in the respective roadmap sections

• identify overall issues – Cu wire bond– bump technology with low k

• determine which issues are specific vs common• act on issues/incorporate in 2001


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Summary• Linkages between ITRS, NEMI, and Jisso roadmaps help provide

a unified message to the industry• major changes to date include:

– chip size for cost-performance, high-performance, memory– accelerated memory performance and related impact on cost-performance

segment– accelerated wire bond pitch

• linkages with other TWGs require follow up• unresolved issues to be addressed in 2001update are an

opportunity to further improve the quality and impact of the ITRS• active participation from all regions is key to success

Hsinchu, Taiwan December 6, 2000 1 International Technology Roadmap for Semiconductors (ITRS 2000) Assembly & Packaging International Technical Working.

Documents

packaging slide

chip packagesmodules

years chip

valuable chip

cost of chip assembly

nemi packaging roadmap

itrs roadmap

update slide