-
HighHigh StepStep--up Ratio DCup Ratio DC--DC DC Converter
TopologiesConverter Topologies
P. P. TentiTenti, L. , L. RossettoRossetto, G. , G.
SpiazziSpiazzi, S. , S. BusoBuso, P. , P. MattavelliMattavelli, ,
L. L. CorradiniCorradini
Dept. of Information Engineering Dept. of Information
Engineering DEIDEIUniversity of PadovaUniversity of Padova
Speaker: G. Speaker: G. SpiazziSpiazzi
Part IIPart II
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2Seminar OutlineSeminar Outline
Why we need high step-up ratio converters? Application
fields
Low power high step-up ratio topologies Coupled inductors
High power high step-up ratio topologies Non isolated
Isolated
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3Cascaded Boost ConverterCascaded Boost Converter
Reduced SReduced S11 and Dand D11 voltage stressvoltage stress
High flexibilityHigh flexibility Suitable for high power
applications through Suitable for high power applications
through
interleaving connectionsinterleaving connections Total power
processed twiceTotal power processed twice High SHigh S22 and Dand
D22 voltage stressvoltage stress
Voltage conversion ratio:Voltage conversion ratio:
U1
D2D1
S1 UoC1 C2S2
L1 L2
Ug Ro
i1 i2Io
21g
1
1
o
g
o
d11
d11
UU
UU
UUM
===
-
4Boost with Voltage Multiplier CellsBoost with Voltage
Multiplier Cells
D
Dm2Dm1S UoCo
L1Lr
Ug Ro
i1ir
Io
Cm1
Cm2
u1
u2
Voltage multiplier cell Voltage multiplier cell d1
2UUM
g
o
=
Reduced switch and diode voltage stress (UReduced switch and
diode voltage stress (UDSDS UUoo/2)/2) ZCS and soft diode turn off
through the use of a resonant ZCS and soft diode turn off through
the use of a resonant
inductor inductor LLrr Suitable for high power applications
through interleaving Suitable for high power applications through
interleaving
connectionsconnections
Maximum and minimum dutyMaximum and minimum duty--cycle
limitation to guarantee cycle limitation to guarantee soft
commutationssoft commutations
High switch RMS currentHigh switch RMS current Voltage stress
reduction related to the number of cells Voltage stress reduction
related to the number of cells
Voltage conversion Voltage conversion ratio:ratio:
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5Boost with Voltage Multiplier CellsBoost with Voltage
Multiplier Cells
d11M
UUM
g
o
+=Voltage conversion ratio:Voltage conversion ratio:
Switch voltage stress:Switch voltage stress: 1MUU oDS +
D
S UoCo
L1
Ug Ro
i1Io
Voltage Voltage multipliermultipliercell cell #1#1
Voltage Voltage multipliermultipliercell cell #2#2
Voltage Voltage multipliermultipliercell cell #M#M
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6Converter Operation (CCM)Converter Operation (CCM)
D
S UoCo
L1
Ug Ro
i1Io
T01 = t1-t0
t1 t2 t3 t4t0 t5
ir
iL
iD1iD2
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7Converter Operation (CCM)Converter Operation (CCM)
D
Dm1 UoCo
L1Lr
Ug Ro
i1ir
Io
Cm1
Cm2
u1
u2
T12 = t2-t1
ir
iLiD1
t1 t2 t3 t4t0 t5
iD2
-
8Converter Operation (CCM)Converter Operation (CCM)
D
UoCo
L1Lr
Ug Ro
i1ir
IoCm2
u2
T23 = t3-t2
t1 t2 t3 t4t0 t5
ir
iL
iD1iD2
Soft DSoft Dm1m1 turn offturn off
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9Converter Operation (CCM)Converter Operation (CCM)
D
S UoCo
L1Lr
Ug Ro
i1ir
IoCm2
u2
T34 = t4-t3
t1 t2 t3 t4t0 t5
ir
iL
iD1iD2
Soft D turn offSoft D turn off
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10
Converter Operation (CCM)Converter Operation (CCM)
D
Dm2S UoCo
L1Lr
Ug Ro
i1ir
Io
Cm1
Cm2
u1
u2
T45 = t5-t4
iL
t1 t2 t3 t4t0 t5
ir
iD1iD2 Soft DSoft Dm2m2 turn offturn off
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11
Dual Boost ConverterDual Boost Converter
Voltage conversion ratio:Voltage conversion ratio: d1d1
UUM
g
o
+==
U1
U2
D2
D1
S1
Uo
C1
C2S2
L1
L2
Ug Ro
i1
i2
Io
Ig
d11
UUM
UUM
g
22
g
11
====
Output voltage of each Output voltage of each
converter:converter:
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12
Dual Boost ConverterDual Boost Converter
U1
U2
D2
D1
S1
Uo
C1
C2S2
L1
L2
Ug Ro
i1
i2
Io
Ig
Reduced switch and diode voltage Reduced switch and diode
voltage stressesstresses
Inductor LInductor L11 and Land L22 rated roughly at rated
roughly at half of total input currenthalf of total input
current
Suitable for high power applications Suitable for high power
applications through interleaving connections of through
interleaving connections of each moduleeach module
Need for isolated gate driverNeed for isolated gate driver
Floating load connectionFloating load connection Limited switch
voltage stress Limited switch voltage stress
reductionreduction
Penalty in the converter efficiency Penalty in the converter
efficiency (negligible for high conversion ratios)(negligible for
high conversion ratios)
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13
Dual Boost ConverterDual Boost Converter
Efficiency reduction:Efficiency reduction:
U1
U2
D2
D1
S1
Uo
C1
C2S2
L1
L2
Ug Ro
i1
i2
Io
Ig
( )( ) ( ) ogd
og
dog21
og21
do
o
g
oT IUPP2
IUP2P2IUUU
IUUUP2P
PPP
+
=
++
+=
+==
d1
1
g
11 PP
PPP
+==
1
1
11
1
1
11
1T 1M
M
11MM
1M21M2
M211
M211
+
=
+
=
=
=
Power processed by each module:
PIUPIUP o22o11 ====
Efficiency of each module:
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14
Dual Boost ConverterDual Boost Converter
Efficiency reduction:Efficiency reduction:1
1T 1M
M+
=
2 3 4 5 6 7 8 9 100.89
0.9
0.91
0.92
0.93
0.94
0.9511 = 0.95= 0.95
11 = 0.94= 0.94
11 = 0.93= 0.93
Voltage conversion ratio MVoltage conversion ratio M
O
v
e
r
a
l
l
e
f
f
i
c
i
e
n
c
y
O
v
e
r
a
l
l
e
f
f
i
c
i
e
n
c
y
T
T
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15
Interleaved Boost with Voltage MultiplierInterleaved Boost with
Voltage Multiplier
Reduced switch and diode voltage stress (UReduced switch and
diode voltage stress (Uoo/2)/2) Inductor LInductor L11 and Land L22
rated at half of total input currentrated at half of total input
current Reduced input current ripple due to interleaved Reduced
input current ripple due to interleaved
operationoperation
Voltage multiplier cell operation requires d > Voltage
multiplier cell operation requires d > ddminmin More ringing on
switch voltage due to capacitor ESLMore ringing on switch voltage
due to capacitor ESL
Voltage conversion Voltage conversion ratio d > 0.5:ratio d
> 0.5:
d12
UUM
g
o
==
2UUU o21 ==
u2
D2 Uo
C1 C2
S2
L1 L2
Ug
Ro
i1 i2
Io
D4 D3
u1
D1
u2
D2 Uo
C1 C2
S2
L1 L2
Ug
Ro
i1 i2
Io
D4 D3D1
u2
D2 Uo
C1 C2
S2
L1 L2
Ug
Ro
i1 i2
Io
D4 D3D1
S1
u1
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16
Current Waveforms d > 0.5Current Waveforms d > 0.5
2UUU o21 ==
i1 i2
iD1
iD3
iD2
iD4
S1S2
u2
D2 Uo
C1 C2
S2
L1 L2
Ug
Ro
i1 i2
Io
D4 D3
u1
D1
u2
D2 Uo
C1 C2
S2
L1 L2
Ug
Ro
i1 i2
Io
D4 D3D1
u2
D2 Uo
C1 C2
S2
L1 L2
Ug
Ro
i1 i2
Io
D4 D3D1
S1
u1
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17
Interleaved Boost with Voltage MultiplierInterleaved Boost with
Voltage Multiplier
i2
uDS2
uDS1
uo
Ug = 20V, Pg = 1280W, Uo = 400V, Po = 1080W
Unbalance due to slightly different switch on times
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18
i1
uDS2
uDS1
uo
Interleaved Boost with Voltage MultiplierInterleaved Boost with
Voltage Multiplier
Ug = 20V, Pg = 1280W, Uo = 400V, Po = 1080W
Effect of capacitor ESL and layout parasitic inductances
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19
Boost with Voltage Boost with Voltage DoublerDoubler
u2 UoC2 Ro
i2
Iou2 UoC2 Ro
i2
Iou2
D2
UoC2
S2
L1
L2
Ug Ro
i2
Io
D3
S1i2i1
Co
Voltage conversion ratio d > 0.5:Voltage conversion ratio d
> 0.5: d12
UUM
g
o
==
2UU o2 =
Similar behavior as the interleaved boost with voltage
multiplier
Problem:Problem: for d < 0.5 the switch voltage for d <
0.5 the switch voltage stress (Sstress (S11) becomes the output
voltage ) becomes the output voltage
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20
Extension to Higher StepExtension to Higher Step--up Ratiosup
Ratios
Voltage conversion ratio d > 2/3:Voltage conversion ratio d
> 2/3: d13
UUM
g
o
==
u2 UoC2Ro
i2
IoUo Ro
i2
Io
D2
Uo
S2
L1
L2
Ug Ro
i2
Io
D1
S1i1
Co
i2i2S3
L3 i3
D3
u3C3
3U
2UU o32 ==
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21
Boost with Voltage Boost with Voltage DoublerDoubler
u2
D2 Uo
C1 C2
S2
L1 L2
Ug
Ro
i1 i2
Io
D4 D3
u1
D1
u2
D2 Uo
C1 C2
S2
L1 L2
Ug
Ro
i1 i2
Io
D4 D3D1
u2
D2 Uo
C1 C2
S2
L1 L2
Ug
Ro
i1 i2
Io
D4 D3D1
S1
u1
Co
Interleaved boost with voltage multiplier Interleaved boost with
voltage multiplier versus versus Boost with voltage Boost with
voltage doublerdoubler
Similar behavior for dutySimilar behavior for duty--cycle higher
than cycle higher than 50% but the structure becomes50% but the
structure becomes asymmetricasymmetric
u2 UoC2 Ro
i2
Io
i2
Io
D2
S2
L1
L2
Ug
i2
Io
D3
S1 Coi1
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22
Boost with ThreeBoost with Three--state Switching Cellstate
Switching Cell
Voltage conversion Voltage conversion ratio (d > 0.5):ratio
(d > 0.5):
u1
u2D2
D1
S1
Uo
C1
C2
S2
L1Ug
Ro
is
ig
Io
Dp
D3 u3 C3
Np
Np
Ns
d11
n
1nUUM
g
o
+==
s
p
NN
n =
Reduced switch and diode voltage stress (depending on Reduced
switch and diode voltage stress (depending on nn)) Reduced input
current ripple due to interleaved operationReduced input current
ripple due to interleaved operation Voltage multiplier cell
operation requires d > Voltage multiplier cell operation
requires d > ddminmin Correct operation requires LCorrect
operation requires L > > LLminmin Operation modes with very
low gainOperation modes with very low gain
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23
Boost with ThreeBoost with Three--state Switching Cellstate
Switching Cell
Voltage conversion ratioVoltage conversion ratio
DCM operation with DCM operation with very low gainvery low
gain
uu22 = u= u33 00
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24
Interleaved Boost with Coupled Inductors and Interleaved Boost
with Coupled Inductors and Voltage MultiplierVoltage Multiplier
Voltage conversion Voltage conversion ratio d > ratio d >
ddminmin (CCM):(CCM):
U2
U1D1
Ld
S1
Uo
C2
C1
S2Ug
Ro
is
i2
Io
D2
np
npi1
Ld
D3
Lmim1
Lmim2
nsns
ig
U3C3D4
d11
n
2nUUM
g
o
+=
s
p
NN
n = 1LLL
dm
m
+
Normalized switch Normalized switch voltage stress:voltage
stress: 2n
n
UU
UUU
o
3
o
swswN +
==
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25
Interleaved Boost with Coupled Inductors and Interleaved Boost
with Coupled Inductors and Voltage MultiplierVoltage Multiplier
Voltage conversion Voltage conversion ratio d > ratio d >
ddminmin (CCM):(CCM):
U2
U1D1
Ld
S1
Uo
C2
C1
S2Ug
Ro
is
i2
Io
D2
np
npi1
Ld
D3
Lmim1
Lmim2
nsns
ig
U3C3D4
Reduced switch and diode voltage stress (depending on Reduced
switch and diode voltage stress (depending on nn)) Reduced input
current ripple due to interleaved operationReduced input current
ripple due to interleaved operation No reverse recovery losses (ZCS
turn on)No reverse recovery losses (ZCS turn on) Voltage multiplier
cell operation requires d > Voltage multiplier cell operation
requires d > ddminmin High switch current stressHigh switch
current stress
d11
n
2nUUM
g
o
+=
s
p
NN
n = 1LLL
dm
m
+
-
26
i1i2
im2
im1
t1 t2 t3 t4 t5 t6t0 t7 t8
T01 = t1-t0
Operation for d > Operation for d > ddminmin
(CCM)(CCM)
U2
U1D1
Ld
S1
Uo
C2
C1
S2Ug
Ro
is
i2
Io
D2
np
npi1
Ld
D3
Lmim1
Lmim2
nsns
ig
U3C3D4
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27
i1
i2
im2
im1
t1 t2 t3 t4 t5 t6t0 t7 t8
T12 = t2-t1
Operation for d > Operation for d > ddminmin
(CCM)(CCM)
U2
U1D1
Ld
S1
Uo
C2
C1
S2Ug
Ro
is
i2
Io
D2
np
npi1
Ld
D3
Lmim1
Lmim2
nsns
ig
U3C3D4
Soft DSoft D33 turn offturn off
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28
i1i2
im2
im1
t1 t2 t3 t4 t5 t6t0 t7 t8
T23 = t3-t2
Operation for d > Operation for d > ddminmin
(CCM)(CCM)
U2
U1D1
Ld
S1
Uo
C2
C1
S2Ug
Ro
is
i2
Io
D2
np
npi1
Ld
D3
Lmim1
Lmim2
nsns
ig
U3C3D4
SS11 ZC turn onZC turn on
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29
i1i2
im2
im1
t1 t2 t3 t4 t5 t6t0 t7 t8
T34 = t4-t3
Operation for d > Operation for d > ddminmin
(CCM)(CCM)
U2
U1D1
Ld
S1
Uo
C2
C1
S2Ug
Ro
is
i2
Io
D2
np
npi1
Ld
D3
Lmim1
Lmim2
nsns
ig
U3C3D4
Soft DSoft D11 turn offturn off
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30
im2
im1
i1i2
t1 t2 t3 t4 t5 t6t0 t7 t8
T45 = t5-t4
Operation for d > Operation for d > ddminmin
(CCM)(CCM)
U2
U1D1
Ld
S1
Uo
C2
C1
S2Ug
Ro
is
i2
Io
D2
np
npi1
Ld
D3
Lmim1
Lmim2
nsns
ig
U3C3D4
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31
i2
i1
im2
im1
t1 t2 t3 t4 t5 t6t0 t7 t8
T56 = t6-t5
Operation for d > Operation for d > ddminmin
(CCM)(CCM)
U2
U1D1
Ld
S1
Uo
C2
C1
S2Ug
Ro
is
i2
Io
D2
np
npi1
Ld
D3
Lmim1
Lmim2
nsns
ig
U3C3D4
Soft DSoft D44 turn offturn off
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32
i2
im2
im1
i1
t1 t2 t3 t4 t5 t6t0 t7 t8
T67 = t7-t6
Operation for d > Operation for d > ddminmin
(CCM)(CCM)
U2
U1D1
Ld
S1
Uo
C2
C1
S2Ug
Ro
is
i2
Io
D2
np
npi1
Ld
D3
Lmim1
Lmim2
nsns
ig
U3C3D4
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33
Operation for d > Operation for d > ddminmin
(CCM)(CCM)
i1i2
im2
im1
t1 t2 t3 t4 t5 t6t0 t7 t8
T78 = t8-t7
U2
U1D1
Ld
S1
Uo
C2
C1
S2Ug
Ro
is
i2
Io
D2
np
npi1
Ld
D3
Lmim1
Lmim2
nsns
ig
U3C3D4
SS22 ZC turn onZC turn on
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34
Operation for d < Operation for d < ddminmin
(CCM)(CCM)
i1 i2
Im1=im2
Voltage conversion Voltage conversion ratio d < ratio d <
ddminmin (CCM):(CCM):
The multiplier cell is disabled (uThe multiplier cell is
disabled (u1 1 = = uu2 2 0, U0, U33 UUoo))
The switch voltage stress becomes equal to the The switch
voltage stress becomes equal to the output voltageoutput
voltage
The magnetizing currents are in phaseThe magnetizing currents
are in phase
d211
UUM
g
o
=
s
p
NN
n = 1LLL
dm
m
+
-
35
Voltage Conversion Ratio (CCM)Voltage Conversion Ratio (CCM)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10
5
10
15
20
25
30
35
duty-cycle
M
n = 1
n = 0.7
n = 0.5
Disabled multiplier
cell
dmin
minmin d11
22n
d211
+=
4n2dmin +
=
-
36
Minimum Switch Voltage StressMinimum Switch Voltage Stress
Normalized switch voltage Normalized switch voltage stress for d
= stress for d = ddminmin::
nM4n
M1
d211
UUU
mino
swN1sw
+=
=
Normalized switch voltage Normalized switch voltage stress at
nominal stress at nominal conditions (d > conditions (d >
ddminmin):): n2
n
UUU
o
swN2sw +
=
Optimum turns ratio:Optimum turns ratio: N2swN1sw UU =
( )
++
= 1M9811
1M3
nopt
-
37
Minimum Switch Voltage StressMinimum Switch Voltage Stress
5 7 9 11 13 15 17 19 21 23 250.25
0.3
0.35
0.4
0.45
0.5
M
UswNmin
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38
Isolated Interleaved High Gain ConverterIsolated Interleaved
High Gain Converter
U2
U1D1Ld
S1
Uo
C2
C1
S2Ug
Rois
i2
Io
D2
np
npi1
Ld
S3 S4Lmim1
Lmim2
nsnsig
UCL CCL
Active clamp
Voltage multiplier
Reduced switch and diode voltage stressReduced switch and diode
voltage stress Reduced input current ripple due to interleaved
operationReduced input current ripple due to interleaved operation
No reverse recovery losses (ZVSNo reverse recovery losses (ZVS--ZCS
switch turn on)ZCS switch turn on) Same operation mode independent
of dutySame operation mode independent of duty--cycle valuecycle
value High switch and winding current RMS valueHigh switch and
winding current RMS value
-
39
Main WaveformsMain Waveforms
T01 = t1-t0
im2
im1
t1 t2 t3 t4 t5 t6t0
i1i2
U2
U1Ld
S1
Uo
C2
C1
S2Ug
Ro
i2
Io
np
npi1
Ld
Lmim1
Lmim2
nsnsig
-
40
Main WaveformsMain Waveforms
T12 = t2-t1
t1 t2 t3 t4 t5 t6t0
i1
im2
im1
i2
U2
U1Ld
Uo
C2
C1
S2Ug
Rois
i2
Io
np
npi1
Ld
Lmim1
Lmim2
nsnsig
D1
UCL CCL S3
SS33 ZV & ZC turn onZV & ZC turn on
-
41
Main WaveformsMain Waveforms
T23 = t3-t2
i1
im2im1
t1 t2 t3 t4 t5 t6t0
i2
U2
U1Ld
S1
Uo
C2
C1
Ug
Rois
i2
Io
np
npi1
Ld
Lmim1
Lmim2
nsnsig
D1
S2
SS11 ZV & ZC turn onZV & ZC turn on(i(i11 is negative
when Sis negative when S33
turns off)turns off)
-
42
Main WaveformsMain Waveforms
T34 = t4-t3
im2im1
t1 t2 t3 t4 t5 t6t0
i1i2
U2
U1Ld
S1
Uo
C2
C1
S2Ug
Ro
i2
Io
np
npi1
Ld
Lmim1
Lmim2
nsnsig
Soft DSoft D11 turn offturn off(no reverse recovery (no reverse
recovery
problem)problem)
-
43
Main WaveformsMain Waveforms
T45 = t5-t4
i1
t1 t2 t3 t4 t5 t6t0
im2im1
i2
U2
U1Ld
S1
Uo
C2
C1
Ug
Rois
i2
Io
D2np
npi1
Ld
S4Lmim1
Lmim2
nsnsig
UCL CCL
SS44 ZV & ZC turn onZV & ZC turn on
-
44
Main WaveformsMain Waveforms
T56 = t6-t5
t1 t2 t3 t4 t5 t6t0
i1
im2im1
i2
SS22 ZV & ZC turn onZV & ZC turn on(i(i22 is negative
when Sis negative when S44
turns off)turns off)
U2
U1Ld
S1
Uo
C2
C1
S2Ug
Rois
i2
Io
D2
np
npi1
Ld
Lmim1
Lmim2
nsnsig
-
45
Main WaveformsMain Waveforms
T01 = t1-t2
t1 t2 t3 t4 t5 t6t0
i1
im2im1
i2Soft D2 turn off
(no reverse recovery problem)
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46
Mismatch SensitivityMismatch Sensitivity
In case of parameter and/or duty-cycle mismatch between the
interleaved boost sections severe current mismatch occurs.
The solution is to employ individual clamp capacitors for each
subsection (in this case, the mismatch is absorbed by a small
difference between the clamp capacitor voltages)
U2
U1D1Ld
S1
Uo
C2
C1
S2Ug
Rois
i2
Io
D2
np
npi1
Ld
S3 S4Lmim1
Lmim2
nsnsig
UCL1
CCL1UCL2
CCL2
Individual clamp capacitors
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47
Isolated Interleaved High Gain Resonant Isolated Interleaved
High Gain Resonant ConverterConverter
Different operation mode is achieved by reducing Different
operation mode is achieved by reducing the capacitor value of the
voltage multiplier cellthe capacitor value of the voltage
multiplier cell
HalfHalf--cycle resonances occur between capacitor Ccycle
resonances occur between capacitor C11and Cand C22 and transformer
leakage inductances Land transformer leakage inductances Ldd..
U2
U1D1Ld
S1
Uo
C2
C1
S2Ug
Rois
i2
Io
D2
np
npi1
Ld
S3 S4Lmim1
Lmim2
nsnsig
UCL CCL
Co
Resonant capacitors
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48
Hard SHard S11 and Sand S22 turn onturn on
Soft DSoft D11 and Dand D22 turn offturn off
ZV & ZC turn on ZV & ZC turn on ofof SS33 and Sand
S44
t1 t2 t3 t4 t5 t6t0
i1
im2im1
i2
Main WaveformsMain Waveforms
offoffoffonT56 = t6-t5
onoffoffonT45 = t5-t4
offoffononT34 = t4-t3
offoffonoffT23 = t3-t2
offononoffT12 = t2-t1
offoffononT01 = t1-t0
D2D1S2S1
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49
Preliminary Experimental ResultsPreliminary Experimental
Results
uGS1
uDS1is
u2
UUgg = 35V, = 35V, UUoo = 360V, P= 360V, Poo = 2500W, = 2500W,
ffswsw = 40kHz = 40kHz
High voltage ripple High voltage ripple on clamp capacitors on
clamp capacitors
Current waveform is Current waveform is half way between half
way between non resonant and non resonant and resonant behaviors
resonant behaviors
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50
ConclusionsConclusions
For high power applications, high step-up converters working
with a quite high input current value should have a continuous
input current absorption.
Interleaved operation at input side helps to reduce the input
current ripple as well as to share the total input current between
different conversion subsections.
A voltage multiplier at the output side avoids the use of
dissipative snubbers across the output diodes.
Isolated structures operate in the same manner independent of
the duty-cycle value (they are better than the non-isolated
ones)