Function-Architecture Co-design. zThe essence of function/architecture codesign methodology yCapture and iterate heterogeneous system behavior, both dataflow.

Function-Architecture Co-design

Function-Architecture Co-design

The essence of function/architecture codesign methodology Capture and iterate heterogeneous

system behavior, both dataflow and control

Compose behavior by linking them with discrete event semantics

Capture a minimal or relaxed product architecture

Function-Architecture Co-design: Cadence Approach

Function

Architecture

Function to Architecture Mapping

Virtual Component InterfaceGoal

Maximum portability No requirements of modification of VCs.

Assumption Initiator/Target connection(point-to-point

connection)Peripheral VCIBasic VCIAdvanced VCI

VCI characterization

Request and response protocol

Peripheral VCI

PVCI protocol

Operation Type Read8, Read16, Read32, Read N cells

Write8, Write16, Write32, Write N cells

Handshake protocol

Basic VCI

Basic VCI

Cell, packet, packet chainCommand, i.e. transaction

NOP (optional), Read, Write, Locked-Read(optional)

Addressing Mode Random address mode Contiguous mode Wrap mode Constant

BVCI READ and WRITE operation

Packet Chain Transfer

Advanced VCI

An Optimal extension of BVCI for multi-processor SoC

Incompatibility with BVIC Out-of-order transfer Advanced packet model

Protocol Advanced packet model Multi-thread transaction Out-order transfer Arbitration hide mode

Advanced Packet Model

Out-of-order transfer

Arbitration Hide Mode

Q3: Dynamic Power Management in On-Chip Communication?Not yet, but …

Techniques of on-chip communication power reduction Encoding/decoding relationship

E.g. Bus invert coding, …

Reducing voltage swing (diff. signaling)

Recent work by Prof. De Micheli

On-chip bus error rate v.s. average energy/useful bit Error sources

Crosstalk, EMI, timing errors, soft errors

Advanced Bus Architecture:Error-resilient Coding

Error-detection code or error-correction code Energy trade-off between

RetransmissionError-correction coder/decoder

Energy Issue in On-chip Bus Arbitration

Centralized bus arbitration As bus scale grows up, energy inefficient

Energy cost of communicating with the arbiter and the arbiter complexity grows up more than linearly.

Distributed bus arbitration Code division multiple access (ISSCC’00) Just began to consider this problem.

Low-Power Bus Topology Design: Pedram, DATE00

Single bus?

Split two buses?

Which one consumesless bus power?

Manual work is possible in func/arch codesign flow?

Manual work in the flow Practically, always necessary to

optimize system performance or minimize the cost.

Vendor dependent situationAt least, after manual optimization

Validation by simulation may be possible.

Transaction and Transfer in VCI

Explained in VCI

Newly designed VC and Wrapper Latency

Bus Architectures and Their Performance Comparison

Bus architectures PCI, AMBA, Pentium Others: CoreConnect, PI bus

VCI specification Most of useful bus functions are

included.Benchmark reports

Little/Big EndianCost & Performance

To convert them, A barrel shifter type converter will be

enough.

Pros and Cons:Bus versus Network