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A 5GHz, 32mW CMOS FrequencySynthesizer with an Injection–Locked

Frequency Divider

Hamid Rategh, Hirad Samavati, Thomas Lee

OUTLINE

� motivation

� introduction

� synthesizer architecture

� synthesizer building blocks

– injection–locked frequency divider (ILFD)

– voltage–controlled oscillator (VCO)

– prescaler

– charge pump and loop–filter

� summary

� conclusion

MOTIVATION

� large demand on wideband wireless LAN systems

– 20+Mb/s data rate

– low cost

– low power

� new released frequency band

– unlicensed national information infrastructure (U–NII) band

GOAL

� design a 5GHz frequency synthesizer for a U–NII bandwireless–LAN receiver (HIPERLAN compatible)

� implement in CMOS

� minimize power consumption

FREQUENCY OF OPERATION

23.5 MHz

5.15 5.30 5.35 5.8255.725

HIPERLAN U-NII

(a)

(b)5.15 GHz

GHz

5.35

RECEIVER ARCHITECTURE

90o

LNA

Q

FrequencySynthesizer

I

� fRF =5.15–5.35GHz

� fLO = 1617fRF

� H. Samavati et al., “A 12.4mW CMOS Front–End for a 5GHz Wireless–LANReceiver”, 1999 Symposium of VLSI Circuits, Session 9.2.

INTEGER–N FREQUENCY SYNTHESIZER

VCO

M

PFD

Loop Filter

Channel Selection

foutf =M.frefref

� fout = M� fref

� M = Mo + S

S = 0; 1; 2; :::; 7

PULSE SWALLOW FREQUENCY DIVIDER

N/N+1fin

S

M

P

Program Counter

Reset

Swallow Counter

fout

ModulusControl

Channel Selection

Prescaler

� one output cycle =

(N + 1)S + (P� S)N = PN + S input cycles.

� fin = (PN + S)� fout

� M = PN+ S = Mo + S

PROPOSED ARCHITECTURE

12

N/N+1

f

Charge PumpPFD

M

ModulusChannelSelect Control

Loop Filter VCO

VCDILFD

f

PrescalerProgram &

CountersPulse Swallow

outref

� fref=11MHz

� fo=4.840–4.994GHz

� 8 channels

� M=220–227

� N=22

ILFD SIMPLIFIED PICTURE

f(e) = e2

iω iω2

iωi2

ωi2

ω

i2

ωi Η(ω)e uω

2,

,

3@

� oscillator feedback model with perturbation

� oscillation conditions should be satisfied in the presence of theincident signal

VOLTAGE–CONTROLLED DIFFERENTIAL ILFD

Vin

Vout

Vc

M1M2

M3M4 R1R2

Ibias

Vdd

- - ++

� 0.24�m CMOS

� Vdd=1.5V

� Ibias=300�A

� fo=2.25GHz

� fi=4.5GHz

INDUCTOR DESIGN (ILFD)

� maximum locking range) maximize L

� minimum power consumption) maximize LQ

INDUCTOR DESIGN

Cox Cox

Csi

RsLs

Cs

Rsi Csi Rsi

Sub

w

s

OD

� design parameters:

– w: metal width

– s: metal spacing

– OD: outer dimension

– n: number of turns

INDUCTOR DESIGN (ILFD)

� in planar spiral inductors maximizing L does not maximize LQ

+

maximize L for a given LQ

VCDILFD FREQUENCY RANGE

3800 4000 4200 4400 4600 4800 5000

0.3

0.4

0.5

0.6

0.7

0.8

Incident frequency (MHz)

Inci

dent

am

plitu

de (

V)

Vc=0.0VVc=2.0V

� 0.24�m CMOS

� Vdd=1.5V

� Ibias=300�A

TRACKING ILFD

12

Vc

VVi o

VCDILFDVCO

� locking range extension

ILFD SUMMARY

maximum frequency of operation 5GHz

output frequency tuning 110MHz� 5%

input–referred locking range 450MHz� 10% @ 0.7mW

900MHz� 20% @ 1.0mW

technology 0.24�m CMOS

die area 0.186mm2

flip–flop–based divider

0.24�m CMOS (simulation) 7mW @ 5GHz

0.1�m CMOS 2.6mW @ 5GHz(Razavi et al., JSSC Vol. 30, No.2, pp 101–109, Feb. 1995)

VOLTAGE–CONTROLLED OSCILLATOR

Vc

M1M2

M3

Ibias

Vdd

Vout

+ +- -

� 0.24�m CMOS

� Vdd=1.5V

� Ibias=2.0mA

� fo=4.85GHz

VARACTOR

-n -n +n+n

G

N-well

Sub

S/D

VFB VGS

G

S/D

+

-

C

� accumulation mode MOS capacitor

– large quality factor (> 60 @ 5GHz)

– flat–band voltage� zero

� A. S. Porret et al., CICC Digest, pp 641-644, 1999.

� T. Soorapanth et al., Symposium on VLSI Circuits Digest, pp 32–33, 1998.

INDUCTOR DESIGN (VCO)

� maximum Q) minimum inductor noise

� if inductors are not the main source of noise, maximum LQ)

– maximum oscillation amplitude for a given bias current

– minimum phase noise

VCO FREQUENCY TUNING

0.5 1 1.5 2

4.65

4.7

4.75

4.8

4.85

4.9

4.95

5

Control voltage (V)

Fre

quen

cy (

GH

z)

� 0.24�m CMOS

� Vdd = 1.5V

� Ibias = 2.0mA

� �f = 370MHz

� 7.7%

� �Vc =1.5V

� ( dfdv)max =500MHz/V

PRESCALER

2/3ClkMC

Q 2/3ClkMC

Q 2/3ClkMC

Q 2 QClk

ClkQ

D Q

ClkQ

D Q

MC

In Out

� divide by 22/23

� N = 24 + S1:20 + S2:21 + S3:22

PRESCALER (ZERO GATE DELAY)

����

����( 2/3)2

����

��( 2/3)1

����

����( 2/3)3

����������( 2)

���������

���������

���������

���������

�����������

�����������

�����������

����������� 20 238 15 17 212 3 4 5 6 7 9 10 11 12 13 14 16 18 19 221

� N = 24 + S1:20 + S2:21 + S3:22

� Tclk = 400ps

� DFO4 = 160ps (Slow process + high temperature)

PRESCALER (NON ZERO GATE DELAY)20 238 15 17 212 3 4 5 6 7 9 10 11 12 13 14 16 18 19 221

��������

��������( 2/3)3

����

����( 2/3)2

������������( 2/3)1

��������( 2)

� problem: gate delays add

� solution:

– make gates faster) burn more power– use quadrature outputs to generate swallow commands

CHARGE PUMP AND LOOP–FILTER

Op

C1C2

R3

C3

R1

Vddvco

Vc

I

U

DD

U

1

I

M4

M1M2

M3

On

� I=50�A

� R1=47k

� R3=8k

� C1=30pF

� C2=3.3pF

� C3=2pF

LOOP–FILTER NOISE

104

105

106

107

−150

−140

−130

−120

−110

−100

−90

Offset frequency (Hz)

Pha

se n

oise

(dB

c/H

z)

noise of R1noise of R3

� L=-107dBc/Hz@ 1MHz

� L=-137dBc/Hz@ 10MHz

� L=-145dBc/Hz@ 22MHz

PLL PHASE NOISE

104

105

106

107

−120

−110

−100

−90

−80

−70

Offset frequency (Hz)

Pha

se n

oise

(dB

c/H

z)

� L=-101dBc/Hz@ 1MHz

� L=-127.5dBc/Hz@ 22MHz

SYNTHESIZER CHIP MICROGRAPH

VCDILFD

VCO

PRESCALER

BIAS FILTERLOOP

PFD &CHG PUMP

COUNTERS

� 0.24�m CMOS

� area=1.6mm2

(1mm� 1.6mm)

SUMMARY

Synthesized frequencies 4.840–4.994GHz

Reference frequency 11MHz

LO spacing 22MHz

Spurs � -45dBc @ fref , � -54dBc @ 2 �fref

Phase noise -101dBc/Hz @ 1MHz

VCO power 3.0mW

VCDILFD power 1.2mW

Prescaler power 25.4mW

Total power 32mW

Supply voltage 2.0V (1.5V for VCO & VCDILFD)

Die area 1.6mm2

Technology 0.24�m CMOS

COMPARISON

reference f (GHz) power L FM comment

Parker, JSSC 98 1.6 90mW 0.6�m 10.6 integer–N

Craninckx, ISSCC 98 1.8 51mW 0.4�m 14.1 fractional–N

Shahani, JSSC 98 1.6 36mW 0.5�m 22.2 dividerless

This work 5.0 32mW 0.24�m 37.5 integer–N

� FM= f�L

power

CONCLUSION

� A 5GHz frequency synthesizer is fully integrated in 0.24�mCMOS

� power consumption is reduced by

– employing a voltage–controlled ILFD

– optimizing spiral inductors for the VCO and ILFD

– taking advantage of quadrature outputs in the prescaler

� loop–filter noise is kept small by using reasonably smallresistors

� low spurious side bands are achieved by

– using a semi–differential charge pump

– designing a fourth–order loop

ACKNOWLEDGMENTS

M. Hershenson

S. Mohan

T. Soorapanth

National Semiconductor

Stanford Graduate Fellowship Program