FPGA To ASIC CONVERSION-RPT

8/7/2019 FPGA To ASIC CONVERSION-RPT

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FPGA To ASIC CONVERSION

Independent Study Seminar Project Report

Submitted by

SHEENAM

ELECTRONICS & COMMUNICATION

07EL308

Faculty Incharge

Mr. J.P.SHIVHARE & Mr. GYANENDRA NATH TRIPATHI

B.E. VIIIth

SEMESTER

2010-2011

Department of Electronics & Communication Engineering

ITM University

Gurgaon


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ACKNOWLEDGEMENT

I, SHEENAM SAINI the student of Electronics & Communication Engineering

discipline, Institute of Technology & Management, Gurgaon, would like to deliver

my sincere thanks to my Mentor,Mr. Neeraj Shukla who provided me with a

wonderful project on FPGA to ASIC CONVERSION

I would even like to thank my project guide Mr. Rajeev Kamal who has helped me

throughout and actually explaining the projects details and made me well versed

with the intricacies of the project and was always available to solve my queries

however trifle they may be.


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ABSTRACT

Now-a days designing chips is no more challenging like earlier when there were no powerful

eda tools available, with evergrowing technology ,engineers now have new considerations to

balance while choosing for the best way to implement their designs. High-end field-

programmable gate arrays (FPGAs) are growing in density (gate count) while handling higher-

speed applications and more complex designs. On the other hand, high-end application-specific

integrated circuits (ASICs) are considered unpredictable at 90 nm and below. So the big question

with a chip designer is of choosing the best way out to implement a design. Although there are

no more distinctions between some traditional ASIC and FPGA applications, the basic ground

rules are still in application. Yet designers should appreciate the subtle differences between

each target platform optimising both on area,power,delay norms . This report will fetch out of

the confusion and offer some insights into the best pathway to silicon implementation


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TABLE OF CONTENTS

CHAPTER NO. PAGE NO.

1. Introduction2. M 1

6. Conclusion 25

7. References 27


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INTRODUCTION

Earlier standard-cell ASICs were considered the best implementation choice for high-volume,

price-sensitive applications whereas FPGAs were restricted to low-volume, price-insensitive

applications. FPGAs were used mainly to prototype parts and portions of a large ASIC design

.Structured ASICs, which have some limited design flexibility, fell somewhere midway.

Are all these generalizations of past hold still true? Havent latest trends in FPGAs included

higher speeds, higher gate counts, lower non-recurring engineering (NRE) costs? How does theprocess flow affect the selection between an ASIC and an FPGA? And what is the key concern

in design complexity ? The answers to these and many more must be understood before one canselect the best and apt route to silicon implementation. As with most engineered solutions, the

final answer relies greatly upon a variety of design-tradeoff studies. Even with the results ofthese studies, however, each decision point carries a host of forewarnings. But this is sort of

technical balancing act that most engineers enjoy.A chip can be implemented as a programmable logic device(FPGA or CPLD) or an ASIC as per

requirement.FPGA: A Field-Programmable Gate Array (FPGA) is a semiconductordevice containing

programmable logic components called "logic blocks", that can be configured usingprogrammable switches . Logic blocks can be programmed a multiple times to perform the

function of basic logic gates such as AND,OR, XOR, or more complex combinational functionssuch as decoders or any mathematical functions.

ASIC: An application-specific integrated circuit (ASIC) is an integrated circuit designed for aspecific application, rather than intended for general-purpose use. Processors, RAM, ROM, etc

areexamplesofASICs.


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MEASURING GAP BETWEEN FPGAs AND ASICs

Application-specific integrated circuits(ASICs) or full-custom design, field programmable gate

arrays (FPGAs) offer many advantages - reduced nonrecurring engineering costs , shorter time tomarket and capability of partial reconfiguration-process of configuring a portion of FPGA while

other part is still running. However, all these advantages come at the cost of an increase insilicon area, a decrease in performance, and an increase in power consumption when designs are

implemented on FPGAs. The existence of these kind of efficiency issues in FPGA-basedimplementations is widely known , but there have been a very few efforts to assess these

differences. These differences result in an area, performance and power consumption gapbetween ASIC or full-custom designs and FPGAs.

We were motivated to measure this FPGA to ASIC gap for the following reasons.

1) In the early stages of system design, when system architect choose their implementation

medium, they often choose between FPGAs and ASICs. Such decisions are based on thedifferences in cost (which is related to area),performance, and power consumption between theseimplementation media, but to date, there have been few attempts to quantify these differences. A

system architect can use these measurements to assess whether implementation in an FPGA isfeasible. These measurements can also be useful for those building ASICs that contain

programmable logic by quantifying the impact of leaving part of a design to be implemented inthe programmable fabric.

2) FPGA makers seeking to improve FPGAs can gain insight by quantitative measurements of

these metrics, particularly when it comes to understanding the benefit of less programmable (but

more efficient) hard heterogeneous blocks such as block memory , multipliers/accumulators , and

multiplexers that modern FPGA often employ.


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SOC DESIGN ISSUES

There are seven primary issues to consider when starting a SoC design: Cost, Time-To-Market

(TTM), Capacity, Performance, Power, Quality and IP. This section will define all seven ofthem.

COST

The minimization of cost on any engineering project is important. The main issue with FPGAs

is their high per unit cost and with ASICs , high up-front cost or NRE (Non-RecurringEngineering)-one-time cost of researching, designing, and testing of a new product. So which

technology offers the most cost effective solution? This question will be answered in thefollowing sections . Finally, a recommendation will be made on the most cost effective solution.

TIME-TO-MARKET (TTM)Time-to-Market or TTM is another very vital issue that has to be taken care of when starting a

new SoC development project. TTM is not only critical in defending competitors to market but it

also impacts the overall cost of the project . The longer it takes to market a product , the greateris the impact to market share. In fact, every month a product is delayed, costing company a 14%loss in market share. Projects having longer development spans require additional resources

(man-hours, tool licensing, etc.). The bottom line is also affected by such additional resources.Between the impact to market share and the cost of additional resources, it is easy to understand

the importance TTM possesses to every project.

CAPACITY

Capacity is another key issue when talking of SoC design. Presently, communication SoCs thatare available can easily reach into the millions of gates. Size may be the determining factor

when considering whether to implement the SoC as an FPGA or as an ASIC. However, even forlarge SoC designs , a methodology including the shorter FPGA verification cycle is desired to be

put to use.

PERFORMANCEAs communication systems are evolving, terms like bandwidth and bit-rate grab greater

importance. SoC designs within those systems are needed to give out as much performance aspossible to keep up with data rates measured in gigabits per second(gps). Achieving higher

performance is always a goal while designing complex SoCs used in communication systems.

POWERPower is another critical resource in today's communication systems. As portable wireless

devices are getting smaller and smaller the available power is decreasing while at the same timethe complexity of the device is increasing. SoC designs used in such devices must conserve as

much power as possible. Lower power equates to smaller and less expensive power supplies,savings on board space and fewer cooling components, which ultimately helps in reducing

overall cost.

QUALITY

Design quality and manufacturing quality are two types of quality to be examined. The firstquality issue, design quality, refers to whether or not the application functions are as specified.

The second quality issue, manufacturing quality, refers to the quality and reliability of eachmanufactured device. Both are critical in providing quality parts to the customer.


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IPDesign reuse in the form of proven IP cores can greatly reduce TTM and increase quality for

SoC designs. According to Dataquest by 2005 SoCs will contain 80% pre-define IP blocks and20% custom logic. By 2010 the percentage of IP contained in a SoC is predicted to grow to 95%.

This increase in demand for IP cores has lead to an explosion of IP core vendors in the market.

The use of IP cores gives designers the flexibility to concentrate most of their time on theapplication specific material while spending a small amount of time on common design blocks.The final effect is a substantial increase in overall productivity, which leads to a substantial

decrease in TTM. Also, once an IP block is mature (has been used in numerous designs) the riskassociated with implementing the core is minimal and results in higher design quality.


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CAD FLOWS

FPGA DESIGN FLOW

Netlist

Bitstream

Design Specifications

HDL+Simulation

Logic Synthesis

Place & Route

Static Time Analysis

Dump code & Verify on FPGA


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ASIC DESIGN FLOW(RTL to GDS II)

Netlist

Bitstream

GDS II

HDL+Simulation

Logic Verification

Floor Planning & Auto Place and

Route

Logic Synthesis(mapping logic on

Gates)

Physical Design Verification &

Advanced Verification(LVS AND DRC)

Design Specifications


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first dumped onto a FPGA and then tested for accurate results. Once the design is proven error

free then it is forwarded for further steps . Its almost clear that FPGA may be needed for

designing an ASIC.

Non Recurring Engineering Expenses

When budgeting for a a particular project, NRE must be considered in order to assess if a new

product will be profitable or not.NRE refers to the one-time cost of researching, designing, and

testing a new product, generally associated with ASICs.There are no such associations with

FPGA. Hence FPGA designs are cost effective.

Simpler Design Cycles

Due to software handling much of the routing, placement, and timing, FPGA designs have

smaller design cycles than ASICs.The FPGA design flow eliminates the complex and time-

consuming floor planning, place and route, timing analysis, and mask / re-spin stages of the

project since the design logic has already been synthesized to be placed onto an already verified,characterized FPGA device.

One of the most time-consuming portions of the ASIC flow is all of the hand-off points, for

place and route, test vector generation, and for prototype fabrication. Since the FPGA flow is

integrated within a single front-to-back development system, there are no hand-off points and no

loss of control during the design phase.

More Predictable Project Cycle

Due to elimination of potential re-spins, wafer capacities, etc. FPGA designs have better project

cycle.

Tools

Tools used for FPGA design implementations are relatively cheaper than ASIC designs.

Re-Usability

A single FPGA can be used for various applications, by simply reprogramming it (dumping new

HDL code). By definition ASIC are application specific cannot be reused.


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HALF ADDER-A CASE STUDY

Let us look upon the implementation of half adder design

Circuit Diagram

A B S C

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Truth Table

Testing of a design is of two kinds:-

1)Functional Testing-Functional testingis a type of black box testing that bases its test cases on

the design under test (DUT)specifications. Designs are tested by feeding them with input and

examining the output, and internal program structure is rarely considered.

Functional testing typically involves five steps:

1. The identification of functions that the software is expected to perform2. The creation of input data based on the function's specifications3. The determination of output based on the function's specifications4. The execution of the test case5. The comparison of actual and expected outputs


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Verilog Code:

module half_adder( sum,carry, a, b

);

input a , b;

output sum, carry;

assign sum = a ^ b;

assign carry = a & b;

endmodule

Circuit Simulation using ModelSim v5.4

2) Electrical Testing/FPGA Emulation- Electrical testing of a design is done on virtualplatform using synthesis tools e.g. Altera,Xilinx etc connecting Xilinx Spartan3 kit(FPGA) . We

provide inputs using configurable switches on kit and obtain the required output as perinput.Oncethe design is successfully tested on FPGA,real time synthesis can be performed

implementating that specific design as an ASIC as per above given ASIC design flow.


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RTL Designs


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User Constraint File(given input and output locations)


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FPGA Emulation (Bit file successfully dumped on FPGA)

Xilinx Spartan3AN kit


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NETLIST COMPARISON-ASIC &FPGA

SYNTHESIS TOOL:LEONARDO SPECTRUM

ASIC NETLIST

*******************************************************

Cell: half_adder View: INTERFACE Library: work

*******************************************************

Cell Library References Total Area

AN2T0 scl05u 1 x 5 5 gates

XR2T0 scl05u 1 x 5 5 gates

Number of ports : 4

Number of nets : 4

Number of instances : 2

Number of references to this view : 0

Total accumulated area :

Number of gates : 10

Info, Command 'report_area' finished successfully


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->set report_delay_slack_threshold 0

0

->report_delay -num_paths 1 -critical_paths -clock_frequency

Using default wire table: SCL_CORE_4K

Critical Path Report

Critical path #1, (unconstrained path)

NAME GATE ARRIVAL LOAD

------------------------------------------------------------------------------

a/ 0.00 0.00 up 0.19

ix7/X XR2T0 0.20 0.20 dn 0.04

s/ 0.00 0.20 dn 0.00

data arrival time 0.20

data required time not specified

------------------------------------------------------------------------------



----------

unconstrained path


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------------------------------------------------------------------------------

Info, Command 'report_delay' finished successfully

->auto_write C:/Exemplar/LeoSpec/v20001b/demo/sheenam_ha_0.v

-- Saving the design database in C:/Exemplar/LeoSpec/v20001b/demo/sheenam_ha_0.xdb

-- Writing file C:/Exemplar/LeoSpec/v20001b/demo/sheenam_ha_0.xdb

-- Writing XDB version 1999.1

-- write C:/Exemplar/LeoSpec/v20001b/demo/sheenam_ha_0.v

-- Writing file C:/Exemplar/LeoSpec/v20001b/demo/sheenam_ha_0.v

Info, Command 'auto_write' finished successfully

Info: Finished Synthesis run

->view_schematic -rtl -view

->view_schematic -view

->set report_delay_slack_threshold 1000.0

1000.0

->report_delay -num_paths 1 -show_schematic 1 -critical_paths

Using default wire table: SCL_CORE_4K

Critical Path Report


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Critical path #1, (unconstrained path)

NAME GATE ARRIVAL LOAD

------------------------------------------------------------------------------

a/ 0.00 0.00 up 0.19

ix7/X XR2T0 0.20 0.20 dn 0.04

s/ 0.00 0.20 dn 0.00



------------------------------------------------------------------------------



----------

unconstrained path

------------------------------------------------------------------------------

Info, Command 'report_delay' finished successfully

->set report_delay_slack_threshold 0

0

->_gc_read_init

->_gc_run_init

->set input_file_list { C:/Exemplar/LeoSpec/v20001b/demo/sheenam_ha.v }

C:/Exemplar/LeoSpec/v20001b/demo/sheenam_ha.v


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->set part EPM9400LC84

EPM9400LC84

->set process 15

15

->set chip TRUE

->set macro FALSE

FALSE

->set delay FALSE

FALSE

->set bubble_tristates TRUE

TRUE

->set hierarchy_auto TRUE

TRUE

->set hierarchy_preserve FALSE

FALSE

->set output_file C:/Exemplar/LeoSpec/v20001b/demo/sheenam_ha.edf

C:/Exemplar/LeoSpec/v20001b/demo/sheenam_ha.edf

->set novendor_constraint_file FALSE

FALSE

->set target max9

max9

->_gc_read

-- Reading target technology max9

Reading library file `c:\Exemplar\LeoSpec\v20001b\lib\max9.syn`...

Library version = 0.5


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Delays assume: Process=15

-- Reading module generator description from file

c:\Exemplar\LeoSpec\v20001b\data\modgen\max9.vhd

-- Reading vhdl file c:\Exemplar\LeoSpec\v20001b\data\modgen\max9.vhd into library OPERATORS

-- Modgen File max9.vhd Version 4.4

-- read -tech max9 { C:/Exemplar/LeoSpec/v20001b/demo/sheenam_ha.v }

-- Reading file 'C:/Exemplar/LeoSpec/v20001b/demo/sheenam_ha.v'...

-- Loading module half_adder

-- Compiling root module 'half_adder'

-- Pre Optimizing Design .work.half_adder.INTERFACE

-- Boundary optimization.

Info: Finished reading design

->_gc_run

-- Run Started On Tue Apr 05 16:06:43 India Standard Time 2011

--

-- optimize -target max9 -effort quick -chip -area -hierarchy=auto

-- Start optimization for design .work.half_adder.INTERFACE

est est

Pass LCs Delay EXPs DFFs TRIs PIs POs --CPU--

min:sec

1 2 15 0 0 0 2 2 00:00

FPGA NETLIST

*******************************************************

Cell: half_adder View: INTERFACE Library: work


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*******************************************************

Number of ports : 4

Number of nets : 10

Number of instances : 8

Number of references to this view : 0

Total accumulated area :

Number of LCs : 2

***********************************************

Device Utilization for EPM9400LC84

***********************************************

Resource Used Avail Utilization

-----------------------------------------------

IOs 4 55 7.27%

LCs 2 400 0.50%

DFFs 0 400 0.00%

EXPs 0 400 0.00%

-----------------------------------------------

-- Design summary in file 'C:/Exemplar/LeoSpec/v20001b/demo/sheenam_ha.sum'

-- Saving the design database in C:/Exemplar/LeoSpec/v20001b/demo/sheenam_ha.xdb

-- Writing file C:/Exemplar/LeoSpec/v20001b/demo/sheenam_ha.xdb

-- Writing XDB version 1999.1


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-- Writing file C:/Exemplar/LeoSpec/v20001b/demo/sheenam_ha.edf

Info, About to call 'setacf' for generating/modifying ACF file

Info, 'setacf' done.

-- CPU time taken for this run was 1.5 sec

-- Run Successfully Ended On Tue Apr 05 16:06:44 India Standard Time 2011

0

Info: Finished Synthesis run


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FPGA TO ASIC CONVERSION-THE BENEFITS

y With an effective FPGA-to-ASIC conversion, system designers can quickly get theirsystem designed and into production using FPGA technology. Then, once the design isfully proven on all means, can be converted to a structured ASIC rapidly and cost-

effectively

y The low nonrecurring-engineering (NRE) charges associated with a structured ASIC,coupled with the much lower unit cost, make this strategy of conversion a powerful tool

to achieve low overall costs and improve competitive advantage.

y To achieve the full benefit of a conversion, it is important to prototype with conversion inmind. Any differences in core voltage, for example, can be accounted for and theadvanced FPGA design moved to a larger-process-geometry structured ASIC. Package

requirements and board layout must be considered, bearing in mind that, even thoughFPGA conversion targets pin-for-pin drop-in replacement, the design may fit into a

lower-pin-count package once it is migrated to an ASIC. If, for example, the productionASIC can use a lower-performance industry-standard package with lower ball counts,

device costs can be further reduced over a typical drop-in replacement.

y It is also important to understand long-term intellectual-property needs. Many FPGAvendors make small modifications to standard IP. Licensing agreements will prevent thedesigner from moving the FPGA vendor-specific IP to an ASIC, and the small

modifications made to the IP mean that off-the-shelf third-party IP may not work as adrop-in replacement. If the design team believes a program will go into volume

production, third-party IP should be used and a license agreement negotiated that allowsIP used in the FPGA to be migrated to a structured ASIC.

y The ability to convert from even the most complex FPGAs to structured ASICs iscreating a symbiotic relationship between FPGA and ASIC vendors that provides OEMs

with the best of both worlds-flexible and rapid development at minimal cost, combinedwith compact, low-power, low-cost components for final manufacture.


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y We have successfully converted thousands of designs from costly FPGAs to efficientASICs throughout the past few decades. The lower unit cost of an ASIC has long been a

key motivating factor in such conversions. However, the appeal of FPGA to ASICconversions goes far beyond the cost savings. The significant power savings realized

through using an ASIC in the place of an FPGA significantly increases battery life.Applications, such as hand-held devices, find this to be a tremendous advantage. In

contrast to the programmable logic used in FPGAs, the hard-coding of the logic in anASIC, does not allow reprogramming of the device, thereby increasing security and

reliability. This added reliability makes ASICs the obvious choice for flight-criticalapplications where SRAM based FPGAs are typically not qualified.

y Moreover, by planning for FPGA-to-ASIC conversion from the outset, and to work witha conversion company that can offer the necessary IP taking an FPGA prototype andconverting it to a structured ASIC, it is possible to have ASICs ready as soon as FPGA-

based product trials are complete, thus minimum time-to-market and maximumcompetitive advantage are ensured.


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CONCLUSION


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REFERENCES

[1] http://chipdesignmag.com/display.php?articleId=115&issueId=11

[2 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITSAND SYSTEMS, VOL. 26, NO. 2, FEBRUARY 2007

[3]http://www.design-reuse.com/articles/4360/fpga-to-asic-strategy-for-communication-soc-designs.html

[4] http://en.wikipedia.org/wiki/Functional_testing[5] http://www.xilinx.com/company/gettingstarted/fpgavsasic.htm

[6] http://www.xilinx.com/products/virtex/asic/methodology.htm[7] http://only-vlsi.blogspot.com/2008/05/fpga-vs-asic.html

[8] http://www.design-reuse.com/articles/8664/fpga-to-asic-conversion-a-crucial-concern.html[9] http://www.onsemi.com/PowerSolutions/content.do?id=16788


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FPGA To ASIC CONVERSION-RPT

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