[Sample Course Title Slide Insert Presentation Title]© 2009 Xilinx,
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FPGA vs. ASIC Design Flow
Curriculum
Path
for
ASIC to FPGA Coding
Don’t forget to listen to these FREE RELs…
FPGA and ASIC Technology Comparison, Part 2
FPGA vs. ASIC Design Flow
ASIC to FPGA Coding Conversion, Part 1 and 2
Virtex-5 Coding Techniques, Part 1 and 2
Spartan-3 Coding Techniques, Part 1 and 2
Fundamentals is a very essential course if you are new to FPGA
design. I recommend that all customers take this course every 3-5
years, since the tools change every year.
Welcome
If you are an experienced ASIC designer transitioning to FPGAs,
this course will help you reduce your learning curve by leveraging
your ASIC experience
Careful attention to how FPGAs are different than ASICs will help
you create a fast and reliable FPGA design
Most ASIC designers struggle with understanding the tools Xilinx
offers. The best way to get up to speed on the ISE Design Suite is
to attend Fundamentals.
Describe key differences between ASIC and FPGA design flows,
including
Design methodology
Verification techniques
Test-generation logic
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FPGA and ASIC Technology Comparison - *
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FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
Design Flow
ASIC and FPGA design and implementation methodologies differ
moderately
Xilinx FPGAs provide for reduced design time and later bug
fixes
No design for test logic is required
Deep sub-micron verification is done
No waiting for prototypes
For high-performance designs, FPGAs may require some
pipelining
When retargeting code from an ASIC to an FPGA, the code usually
requires optimization (instantiation)
Basically, Xilinx FPGAs are a guaranteed off the shelf product.
They are proven devices. However, there can be reasons why a design
will not work. Those reasons are rarely about the silicon not
working, and most likely involve asynchronous design,
metastability, or ground bounce.
The reason we say no waiting for prototypes is that testing only
takes as long as the designer takes to build their HDL,
synthesizing, and implement their design. This is a fraction of the
length of time to build and test an ASIC.
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FPGA and ASIC Technology Comparison - *
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FPGA and ASIC Technology Comparison - *
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ASIC Design Flow
Post-synthesis static timing analysis and equivalency checking are
musts for sign off to foundry
Verification of deep sub-micron effects (second- and third-order
effects) is required for ASICs
Internal, deep sub-micron effects are already verified for Xilinx
FPGAs
The ISE Design Suite does support running from scripts, however,
not all the utilities support this.
The Implementation process (place and route) supports
scripting.
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FPGA and ASIC Technology Comparison - *
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FPGA and ASIC Technology Comparison - *
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FPGA Design Flow
capabilities
After the design passes behavioral simulation and static timing
analysis, verification is completed most efficiently by verifying
in circuit
Fast turnaround times
Static timing analysis is used to verify timing of the design
Timing simulation is supported
This is a simplified/typical design flow
With an FPGA there is no time spent to complete an equivalency
check or to have the device made at a foundry. This save months of
development time.
Static Timing Analysis is supported with the Xilinx Timing Analyzer
which provides worst-case timing delay reporting. Typical FPGA
designers spend most of this time determining why their timing
constraints failed. This is usually resolved with making design
changes.
Some users do complete a timing simulation, but the more
experienced designers (that have experience building FPGA designs)
generally only check certain system transitions.
Most FPGA customers spend 80% of their simulation time doing
behavioral, and 20% doing timing simulation.
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FPGA and ASIC Technology Comparison - *
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FPGA and ASIC Technology Comparison - *
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ASIC Implementation
Create HDL
Synthesis
(BIST, Scan, and JTAG)
Foundry tools, Cadence, AVANT
Design for test includes:
ATPG - Automatic Test Pattern Generation: Test vectors generated
and run through the circuitry to test the part.
BIST - Built-In Self Test: Used to test functionality of memory
resources (specifically RAM)
Scan - Internal Scan chain: Creates an internal shift register to
test the functionality of the part.
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FPGA and ASIC Technology Comparison - *
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FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
FPGA Implementation
Create HDL
performance
Synthesis
Pushbutton flow, scripting capabilities
ISE Design Suite (Integrated Synthesis Environment). The ISE
software tools encompass the entire flow.
XST: Xilinx Synthesis Technology is a synthesis tool provided with
the ISE software.
Synopsys and Mentor are the primary 3rd party synthesis tool
vendors that support the FPGA industry. Synopsys now includes
Synplify synthesis.
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FPGA and ASIC Technology Comparison - *
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FPGA and ASIC Technology Comparison - *
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ASIC Verification
Post-place & route equivalency checking
Post-place & route timing simulation*
effects
Post-synthesis timing simulation and Post-place & route timing
simulation are also often done.
In general, equivalency checking and static timing analysis are
replacing timing simulation verification steps.
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FPGA and ASIC Technology Comparison - *
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FPGA and ASIC Technology Comparison - *
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FPGA Verification
Behavioral simulation
Post-synthesis gate-level simulation
and post-place & route timing simulations can be done for
production sign off
Post-place & route timing
to verify board- and system-level timing
Most FPGA customers spend 80% of their simulation time doing
behavioral, and 20% doing timing simulation.
Some users do complete a timing simulation, but the more
experienced designers (that have experience building FPGA designs)
generally only check certain system transitions.
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FPGA and ASIC Technology Comparison - *
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FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
Deep Sub-Micron Effects
Second- and third-order effects
Silicon-induced design flaws due to the small wire delays and
narrow silicon of deep sub-micron processes
They include cross talk, interconnect delays, and Simultaneously
Switching Outputs (SSO)
Xilinx FPGAs inherently have fewer deep sub-micron silicon
issues
Pre-engineered standard product alleviates complex deep sub-micron
design issues
Recovers design innovation time and facilitates
time-to-market
Xilinx pre-engineers deep sub-micron silicon issues out of the
devices.
The only issues with interconnect delays an FPGA designer might
have involve getting their timing objectives to be met by the
implementation tools. This is discussed in detail in the Designing
for Performance course.
SSO guidelines are provided in the each FPGAs User Guide. This
defines the maximum number of SSO pins that can switch at one timer
per IO bank. You should note that this number is dependent on the
IO standard chosen and the slew rate.
Design Phase
ASIC Design
FPGA and ASIC Technology Comparison - *
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FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
Design for Test Logic
ASIC test-generation logic is not required in a Xilinx FPGA
Because of the capability to test in-circuit, automatic test
pattern generation logic is
normally not included
This reduces the time spent on creating and inserting test logic,
and allows more time to be
spent “on the bench” testing the design
Xilinx FPGAs already contain JTAG (boundary scan) logic
Xilinx FPGAs have readback capability that is similar to scan
logic
Readback can verify the configuration as well as the internal
status of registers and memory
Readback and JTAG resources are dedicated in the FPGA and do not
have to be “designed in”. So using these features does not use any
general logic resources.
For more information on the readback capability, refer to the
following Xilinx application notes:
Application Note XAPP138: Virtex FPGA Series Configuration and
Readback
Application Note XAPP139: Configuration and Readback of Virtex
FPGAs Using (JTAG) Boundary-Scan
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FPGA and ASIC Technology Comparison - *
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FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
In-Circuit Verification Tools
ChipScope Pro software Integrated Logic Analysis (ILA) provides
in-circuit logic verification through the dedicated JTAG pins
No need for extra headers
The ChipScope Pro software is a standalone tool for logic
analysis
Data channels from 1 to 256;
sample sizes from 256 to 4096
To use the ChipScope Pro software ILA, all that is required is a PC
running the ChipScope ILA software, a MultiLINX/parallel cable
(JTAG connection), and an FPGA with the appropriate ChipScope cores
added.
Triggers are setup via the ChipScope software. When a trigger
occurs, data is stored in Block RAM in the FPGA to be read back
through the download cable.
For more information, go to www.xilinx.com/chipscopepro.
There is also a FREE REL on ChipScope.
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FPGA and ASIC Technology Comparison - *
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FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
Firmware Development
Firmware development begins much earlier in the design cycle for
FPGAs
No waiting time for prototypes
Hardware and software can develop in tandem
ASIC Design Flow
FPGA and ASIC Technology Comparison - *
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FPGA and ASIC Technology Comparison - *
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Design Flow Comparison
FPGA and ASIC Technology Comparison - *
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FPGA and ASIC Technology Comparison - *
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Advanced FPGA Tool Flow
Static timing analysis
Xilinx FPGA Editor
Equivalency checking is not required, but some ASIC designers feel
more comfortable using an equivalency software product in an FPGA
flow.
Amplify allows designers to place area constraints on their design
at the synthesis level. Some customers like doing this.
PlanAhead allows designers to place area constraints early in the
design flow and has functionality that enables designers to make
better area constraints.
XPower is a power estimation utility included with the ISE Design
Suite.
The FPGA Editor allows designers complete control of the FPGA
design. It also allows changing the design without re-implementing
the design.
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FPGA and ASIC Technology Comparison - *
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FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
Quiz1
FPGA and ASIC Technology Comparison - *
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FPGA and ASIC Technology Comparison - *
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Equivalency Checking
Equivalency checking (also known as formal verification) determines
if two versions of a design are functionally equivalent
For example, an RTL versus a post-synthesis design
Fast and efficient verification of large designs without the use of
test vectors
Far faster than simulating post-synthesis and post-place &
route netlists
This is screen shot from Synopsys Formality. Not many of our
customers complete an equivalency check.
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FPGA and ASIC Technology Comparison - *
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FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
Floorplanning and Layout
PlanAhead software are used for design layout
The Flooplanner utility is covered in the Advanced FPGA
Implementation course.
The PlanAhead software has its own course titled Designing with the
PlanAhead Analysis and Design Tool.
PlanAhead also allows you to implement the logic on an area
constraint basis and maintain the placement of logic in IP.
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FPGA and ASIC Technology Comparison - *
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FPGA and ASIC Technology Comparison - *
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ISE Tool Floorplanner
White Floorplan window shows the area constraints you have
made
Grey Placement window shows the placement found by the
implementation tools
Design Hierarchy
Highlights a selected net in the design
The Floorplanner allows designers to make area constraints.
However, it does not have the analysis capabilities that the
PlanAhead software has.
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FPGA and ASIC Technology Comparison - *
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FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
PlanAhead Software
Challenging designs
Designs experiencing implementation issues
Designs requiring implementation control
Visualize design issues from many aspects
Block-based designs
Virtex®-4 FX140 FPGA
Many resource types
The productivity gains enabled by the PlanAhead tool will help to
reduce the overall design cycles of large and high performance
designs.
Designers who need extra performance out of their designs or who
have to squeeze a tight design into a particular device are typical
users, as well as designers who have experienced implementation
issues in the past.
The PlanAhead software is not integrated with the ISE tools. It has
to be installed and licensed separately.
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FPGA and ASIC Technology Comparison - *
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FPGA and ASIC Technology Comparison - *
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PinAhead
Tool includes a DRC check and WASSO analysis
Allows you to see both a Package and Pin view of your design
Makes it easy to make pin assignments and attributes
I/O Ports View
Package Pins View
Clock Regions View
The PinAhead view layout allows easy selection, sorting, and
placement of I/O ports and package pins.
The main benefit of using this tool is that it has a Design Rule
Checker (DRC) that helps avoid common pin assignment mistakes. It
also has a WASSO analysis tool that helps designers avoid creating
an SSO problem in their pin layout.
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FPGA and ASIC Technology Comparison - *
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FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
Xilinx SmartGuide Technology and Partitions
SmartGuide™ technology is used to maintain as much of the place
& route as possible, while still enabling place & route
changes to improve timing
Works best when there are small design changes and the original
design met timing
Saves place & route run time
Partitions are used to maintain a place & route solution for
unmodified logic in a partition
Works best if you have large amounts of design changes between each
iteration
Works best if a single partition has a high percentage of
changes
Timing-critical paths should not cross any boundaries
Saves place & route run time
SmartGuide and partitions are covered in the Advanced FPGA
Implementation course. This functionality is designed to maintain
results so you don’t have to re-simulate/re-verify if your design
has to change some.
Both options are integrated as part of the ISE tools.
Note that neither will improve the speed of components that are not
allowed to change. So be sure that you like the timing of the
components that you are keeping.
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FPGA and ASIC Technology Comparison - *
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FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
FPGA Editor
Device resources
The FPGA Editor is commonly used to
View device resources
Make minor modifications
Does not require re-implementation of the design
Changes are NOT back-annotated to the source files
Insert probes
FPGA Editor is covered in the Advanced FPGA Implementation
course.
Note that when users make changes to their design with the FPGA
Editor, the changes are not back-annotated to the source files. So
the changes are not recorded or re-traceable unless the user makes
their own notes.
What is great about this tool is that it gives the designer
complete control of the silicon. So a designer can override the
place and route solution found by the tools, although this is not
very common.
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FPGA and ASIC Technology Comparison - *
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FPGA and ASIC Technology Comparison - *
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Xilinx XPower
the power consumption and
ambient temperature
You can also supply design activity data from simulation (VCD
file)
There is also a Power Estimator worksheet that is available to
designers. The worksheet allows you to estimate your power
consumption while you are still estimating the resources your
design might have (concept level).
The XPower utility is still an estimate because power consumption
is dependent on the actual activity rates of your system. To find
the actual power of your system you will have to use the
appropriate lab equipment attached with your programmed
device.
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FPGA and ASIC Technology Comparison - *
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FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
Synopsys PrimeTime
tool targeting complex multimillion gate designs
Ideal for system-on-a-chip designs
multimillion-gate FPGAs
Some customers feel better about their FPGA system if they can use
a tool to give them an ASIC-quality sign off.
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
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FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
Quiz2
FPGA and ASIC Technology Comparison - *
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FPGA and ASIC Technology Comparison - *
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Summary
FPGAs provide for reduced design time and later bug fixes
No design for test logic is required
Deep sub-micron verification has been completed
No waiting for prototypes
Firmware development starts sooner in the design cycle for the FPGA
design flow
Faster production ramp up
The Xilinx ChipScope Pro software tool provides powerful in-circuit
verification
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
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FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
Where Can I Learn More?
Xilinx online documents
Virtex-5 FPGA Packaging and Pinout Specifications (Pinout tables,
PCB design rules, etc.)
Virtex-5 FPGA Configuration User Guide (Configuration overview,
JTAG, readback, etc.)
Xilinx Training
Timing Analyzer is taught in the Designing for Performance
course
FPGA Editor, Floorplanner, SmartGuide technology, and partitions
are taught in the Advanced FPGA Implementation course
Free recorded e-Learning modules
FPGA and ASIC Technology Comparison - *
© 2007 Xilinx, Inc. All Rights Reserved
FPGA and ASIC Technology Comparison - *
© 2009 Xilinx, Inc. All Rights Reserved
End of Design Flow
The next course in the ASIC curriculum sequence is
ASIC to FPGA Coding Conversion, Part 1
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© 2009 Xilinx, Inc. All Rights Reserved
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