FPGA and ASIC Technology Comparison - 1 © 2009 Xilinx, Inc. All Rights Reserved FPGA and ASIC Technology Comparison, Part 2.

FPGA and ASIC Technology Comparison - 1

© 2009 Xilinx, Inc. All Rights Reserved

FPGA and ASIC Technology Comparison, Part 2

Fundamentals of FPGA Design

Fundamentals of FPGA Design

1day

Designing forPerformance

Designing forPerformance

2days

Advanced FPGAImplementation

Advanced FPGAImplementation

2days

Intro to VHDL or Intro to Verilog

Intro to VHDL or Intro to Verilog

3days

FPGA and ASIC Technology Comparison

FPGA vs. ASIC Design FlowASIC to FPGA

Coding Conversion

Virtex-5 Coding Techniques Spartan-3 Coding Techniques

Curriculum Curriculum PathPath

forforASIC DesignASIC Design

FPGA and ASIC Technology Comparison

If you are an experienced ASIC designer transitioning to FPGAs, this course will help you reduce your learning curve by leveraging your ASIC experienceCareful attention to how FPGAs are different than ASICs will help you create a fast and reliable FPGA design

Welcome

Describe how a simple logic implementation can differ between ASIC and FPGAsRecognize gate counts as an estimation of design sizeExplain some of the FPGA design practices you must follow to get peak performance in your FPGA

After completing this module, you will able to:

© 2007 Xilinx, Inc. All Rights ReservedFPGA and ASIC Technology Comparison - 5



Gate Comparison

In retargeting HDL code for an ASIC design to an FPGA, gate conversion is rarely one to one

A 0.13-µ standard cell can have up to 100K gates per mm2

A Virtex®-5 FPGA has about 20K usable gates per mm2

Why the difference?

Xilinx has programmable logic in addition to the functional logicRoutingMultiplexersConfiguration memory registers

This means built-in design flexibility!




Gate Translation

Separate out logic, flip-flops, RAM, cores, and I/OPartition cores into logic and RAM

Assume6 to 24 gates per LUT (depending on the number of inputs used)RAM bits are equivalentUp to 100 ASIC gates per I/O; translate to IOBs7 gates per register

So what design strategy do you think you need to use?To get the most out of the FPGA try to use as many features as possible, especially the FPGA’s dedicated hardware




Example

ASIC 250K logic gates

Four 32-kb blocks of RAM

243 pads, includingpower and ground

FPGA 20,800 to 41,600 LUTs

Equivalent

Equivalent number of pins

Depending on the number of LUTs needed, this design could use a

Virtex-5 LX30, LX50, or LX85 FPGA

Depending on the number of LUTs needed, this design could use a

Virtex-5 LX30, LX50, or LX85 FPGA




Any ASIC-to-FPGA gate counting method is only a rough estimate.

Taking ASIC code directly to an FPGA will not utilize the dedicated resources of the FPGA.

Gate Counts

Gate counts are influenced byCoding styleMetal layersProcess geometryLibrary qualityPlacement and routing algorithmsCore contents (RAM versus gates)I/O requirementsSpecial features

CONCLUSION




8-input AND gate

AND Gate Example

For vec(7.0)

assign and_out = & vec;

Verilo

gV

erilog

For vec(7 downto 0)

and_out <= vec(0) AND vec(1) AND vec(2) AND vec(3) AND vec(4) AND vec(5) AND vec(6) AND vec(7);

VH

DL

VH

DL




ASIC Implementation

8-input AND gateTwo four-input NAND gates feeding a two-input NOR gate

Approximate delay in a standard-cell ASIC with 0.13-µ process = 0.47 ns

Approximate gate count = 14

Beware of ASIC libraries with very wide gate types!




Xilinx Implementation

Approximate max delay in a Virtex-5 FPGA = 0.435 ns

Approximate gate count = 18 gates

8-input AND gate implemented in three 4-input LUTs and two logic levels

Approximate max delay in a Spartan®-3 FPGA = 0.678 ns

Approximate gate count = 18 gates




QuestionHow many 4-input LUTs would be required to implement a 32-input OR gate?

How many Logic Levels would they generate?




AnswerHow many 4-input LUTs would be required to implement a 32-input OR gate? 11

How many Logic Levels would they generate? 3

If net delays ~ .3 ns and LUT delays ~.2 ns then total delay would be 2(.3) + 3(.2) ~ 1.2 ns

…in a Spartan®-3 FPGA

How do you think this would be implemented in Virtex-5 with a 6-input LUT? (Answer: 7 LUTs and 2 Logic Levels)

LUTLUT

LUTLUT

LUTLUT

LUTLUT

LUTLUT

LUTLUT

LUTLUT

LUTLUT

LUTLUT

LUTLUT

LUTLUT




Tri-State Busses

Some ASIC designs have large tri-state bussesThere are no tri-state buffers associated with each slice in the newest FPGAsThese will have to be re-synthesized and be mapped to LUTs and the F7 and F8 dedicated muxesYou may need to code these with a CASE statement and a high-Z outputThe F7 can implement an 8-to-1 mux The F8 can implement a 16-to-1 mux




Registered AND gate

process (clk)beginif rising_edge(clk) then

vec_q <= vec;and_out <= vec_q(0) AND vec_q(1) AND vec_q(2) AND vec_q(3) AND vec_q(4) AND vec_q(5) AND vec_q(6) AND vec_q(7);

end if;end process;

VH

DL

VH

DL

always @ (posedge clk)begin

vec_q <= vec;and_out <= & vec_q;

end

Verilo

g




Performance Comparison

A comparison of the achieved performance for the registered 8-input AND gate

Virtex-5 FPGA• ~550 MHz• ~88 gates

0.13-µ standard cell ASIC• ~850 MHz• ~77 gates

Typical high-performance frequencies (no optimization for the FPGA)Virtex-5 FPGA

• ~275 MHz for four-levels of LUT (combinatorial) logic0.13-µ standard cell ASIC

• ~550 MHz for equivalent logic

Don’t forget to optimize your HDL code!




ASIC versus FPGA

Combinatorial logic implemented in an ASIC is typically faster than in an FPGA implementation

The fine-grain architecture of an ASIC allows wider input functions to be implemented with significantly less delayASICs have a dedicated routing structure rather than a programmable routing structure

Don’t forget to include Xilinx-dedicated resources in your design!

Critical paths typically include I/O, RAM, PCI™ technology, EMAC, and DSP resources

Xilinx has dedicated FPGA resources to implement these functions, making these paths equivalent to an ASIC implementation

• Remember: Xilinx Virtex-5 devices are cutting-edge ASICs




Pipelining

fMAX = n MHz

D QTwo Logic Levels D Q

fMAX 2n MHz

One Level

One Level

D Q D Q D Q




Sequential Design

How do you get high performance from an FPGA?

PipeliningFor large combinatorial paths, additional registers may need to be inferred to break up combinatorial paths to increase performanceThis technique increases the size of the designThis is not as likely to be needed for Virtex-5 FPGA designs because the Virtex-5 FPGA has a 6-input LUTEvaluate the number of logic levels your design has by generating a timing report from the ISE® Design Suite or your synthesis toolUsually the registers are added at a hierarchical boundary

Don’t forget to evaluate the number of logic levels for your timing-critical paths!




Timing Constraints

How do you get high performance from an FPGA?

Timing constraintsTiming constraints communicate the performance goals to the implementation toolsGlobal timing constraints constrain virtually all the paths in your design based on your system frequency, input, and output times (PERIOD, OFFSET IN, OFFSET OUT)Path-specific timing constraints need to be added to constrain multi-cycle paths and false paths

Adding timing constraints is essential if you want good system speed!




Coding Style

How do you get high performance out of an FPGA?

Coding style has a large impact on the performanceBecause FPGA combinatorial and routing resources are inherently slower, the HDL coding style needs to be improved Write your code to limit the number of logic levels inferredLearn about proper HDL coding styles by listening to the REL modules

Don’t waste time! Evaluate your HDL!




Synchronous Design

How do you get reliability out of an FPGA?

Always build a synchronous designAsynchronous circuits are less reliableLot variations exist for all FPGAs, which means that your design has to be able to work for faster devices

Timing constraintsCannot fix asynchronous design problems—only you can




Synchronous Design Methodology

One clock (or at least as few as possible)Use one edge (all flip-flops use rising or falling edge)Use D-type flip-flopsRegister the outputs of each behavioral blockIn place of multiple clocks, use clock enablesSynchronize asynchronous signals to the “single” clock (synchronization circuits)Do NOT create

Gated, derived, or divided clocksLocal asynchronous set/resetAvoid global asynchronous set/reset

Get it right the first time!




Summary

Don’t worry too much about gate counting methodologies. They are only rough estimates, anywayOptimize your HDL coding styleInstantiate Xilinx-dedicated hardware resources into your design to improve your system speed and maximize what you get from your FPGAPipeline your timing-critical pathsTiming constraints are a primary means for improving system speedGet your design to work properly the first time by designing synchronously




Where Can I Learn More?

Xilinx Answers Browser www.support.xilinx.com Answers Browser window

• Enter keywords like “pipelining” or “period constraint”

Xilinx Trainingwww.xilinx.com/training

• Xilinx tools and architecture courses– Fundamentals of FPGA Design

» Learn about synchronous design, global timing constraints, the Architecture Wizard, and the CORE Generator™ tool

– Designing for Performance» Learn about avoiding metastability, path-specific timing constraints,

and the Timing Analyzer • Free training videos

» Learn about proper HDL coding techniques




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