EE25266 – ASIC/FPGA Chip Design Mahdi Shabany Electrical Engineering Department Sharif University of Technology Assignment #7 Getting started with Atlys board and ISE design environment Part I ) In pervious assignments you got familiar with Quartus software and how to use it to Synthesis a Verilog code , set some constraint and pin assignments , do place and route and map it to one of Altera’s FPGAs , generate bit-stream and finally load it to the target FPGA (Most of these steps take place sequentially when you press run -a purple triangle- on Quartus) . ISE is Quartus counterpart for Xilinx’s (one other famous FPGA developer company) FPGAs. Xilinx ISE also is an integrated software which makes it possible for user to implement a digital design on a Xilinx’s FPGA from A to Z. In this part we are getting started with ISE through making a simple project. To run ISE, click on icon on your Lab computer’s desktop. To make a new project, select: File>New Project…, then New Project Wizard will open and help you to create a new project.
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EE25266 – ASIC/FPGA Chip Design
Mahdi Shabany Electrical Engineering Department
Sharif University of Technology
Assignment #7
Getting started with Atlys board and ISE design environment
Part I ) In pervious assignments you got familiar with Quartus software and how to use it to
Synthesis a Verilog code , set some constraint and pin assignments , do place and route and
map it to one of Altera’s FPGAs , generate bit-stream and finally load it to the target FPGA
(Most of these steps take place sequentially when you press run -a purple triangle- on
Quartus) . ISE is Quartus counterpart for Xilinx’s (one other famous FPGA developer company)
FPGAs. Xilinx ISE also is an integrated software which makes it possible for user to implement a
digital design on a Xilinx’s FPGA from A to Z. In this part we are getting started with ISE through
making a simple project.
To run ISE, click on icon on your Lab computer’s desktop. To make a new project, select:
File>New Project…, then New Project Wizard will open and help you to create a new project.
In the first page you specify your project name and its saving path and also the method you
want to use for you Top-level source type such as HDL , Schematic ,… . Use fpga_test for project
name and HDL as Top-level source e and go to the next step.
In the next page you should specify details about: your target FPGA, HDL language you choose
to use, synthesis and simulator tool and etc. Since we use Atlys board for this assignment you
can find details about FPGA which is used in this board via: