FOR andy.pang@ miuix.com.cn USE ONLY · 1.2 28 August 2020 Update hapter 4.2.2 Power-on/off sequence about REGEN time Update hapter 6.3 attery charger 1.3 22 September 2020 Update

AB1561/AB1562 Datasheet

Version: 1.3 Release date: 22 September 2020

© 2020 Airoha Technology Corp.

This document contains information that is proprietary to Airoha Technology Corp. (“Airoha”) and/or its licensor(s). Airoha cannot grant you permission for any material that is owned by third parties. You may only use or reproduce this document if you have agreed to and been bound by the applicable license agreement with Airoha (“License Agreement”) and been granted explicit permission within the License Agreement (“Permitted User”). If you are not a Permitted User, please cease any access or use of this document immediately. Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited. THIS DOCUMENT IS PROVIDED ON AN “AS-IS” BASIS ONLY. AIROHA EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES OF ANY KIND AND SHALL IN NO EVENT BE LIABLE FOR ANY CLAIMS RELATING TO OR ARISING OUT OF THIS DOCUMENT OR ANY USE OR INABILITY TO USE THEREOF. Specifications contained herein are subject to change without notice.

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© 2020 Airoha Technology Corp Page 2 of 117 This document contains information that is proprietary to Airoha Technology Corp. (“Airoha”) and/or its licensor(s).

Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.

Document Revision History

Revision Date Description

1.0 22 July 2020 Formal release version 1.0

1.1 3 August 2020 Update Figure 2.3-1. Clock source architecture

Not support DCC mode

1.2 28 August 2020 Update Chapter 4.2.2 Power-on/off sequence about REGEN time

Update Chapter 6.3 Battery charger

1.3 22 September 2020 Update Table 6.1-1. Absolute maximum ratings for power supply and Table 6.3-1. Battery Charger about VBUS_UART information

Update Table 2.8-2. Touch Control Specifications about scan clock rate

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Features

DSP Host processor

Cadence® HiFi Mini®Audio Engine DSP coprocessor with HiFi EP® extension

Maximum speed: 208MHz

32kB instruction cache and 8kB data cache with high hit rate and zero wait state

160kB instruction RAM with zero wait state

384kB data RAM with zero wait state

Memory

System in Package (SiP) 16Mb low-power flash memory with 0.1µA deep-down current (typical condition) and maximum speed 104MHz (AB1562U, AB1562A and AB1562F)

System in Package (SiP) 32Mb low-power flash memory with 0.1µA deep-down current (typical condition) and maximum speed 104MHz (AB1562M and AB1561M)

Low latency 8kB system RAM (SYSRAM) with maximum speed 104MHz

Platform

Dynamic Frequency Scaling (DFS)

17 DMA channels

RTC timer

Seven general purpose timers (GPTs)

Watchdog timer (WDT)

Capacitive Touch Control

True random number generator

Ambient temperature from -40°C to 85°C

Peripheral

Two I2C interfaces up to 3.4Mhz

Two UART interfaces up to 3Mbps

SPI master interfaces up to 52MHz

PWM channels

12-bit AUXADC channels

Bluetooth

Fully compliant with Bluetooth core specification 5.2

Low-IF arc1hitecture with high degree of linearity and high order channel filter

Integrated T/R switch and balun

Fully integrated PA provides 10dBm output power

-96dBm sensitivity with interference rejection performance

Baseband support dual mode (Bluetooth and Bluetooth LE) and isochronous channel

Up to four simultaneous active ACL links

Up to four simultaneous active Bluetooth LE links

Support single SCO or eSCO link with CVSD/mSBC coding

Support BLE1M/2M

Audio

Three uplink paths with analog/digital microphone input mode. The maximum sample rate is 192 KHz and data precision is 24-bit.

One downlink path with maximum 192 KHz sample rate and 24-bit data precision.

Class D amplifier

Side-tone filter

Two channel asynchronous sample rate converter

o Anti-alias filter

o 16/32-bit input/output data formats

o frequency auto-tracking

Hardware Active Noise Cancellation(ANC)

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o Feedforward ANC (only AB1562A and AB1562F support)

o Hybrid ANC (only AB1562A supports)

I2S master or slave modes

o 16/24-bit data addressing format

o mono or stereo data transactions

o maximum sample rate 192KHz

hardware gain control

Power management

Two Buck regulators

Three LDO regulators

Li-ion battery charger for internal charging

Package

SQFN of 4mm*6.5mm, 44-lead, 0.4mm pitch

package

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Table of Contents

Document Revision History .............................................................................................................................. 2

Features ........................................................................................................................................................... 3

Table of Contents ............................................................................................................................................. 5

List of Figures and Tables ................................................................................................................................. 8

System Overview .................................................................................................................................. 12

Product series ................................................................................................................................... 12 System architecture .......................................................................................................................... 13 Platform features overview .............................................................................................................. 13

Host processor DSP subsystem ....................................................................................... 13 Memory summary .......................................................................................................... 14 Peripheral interfaces summary....................................................................................... 14 Security ........................................................................................................................... 14 Others ............................................................................................................................. 14

Audio features overview................................................................................................................... 15 Audio codec feature overview ........................................................................................ 15 Audio other functions feature overview ........................................................................ 15

Connectivity (Bluetooth) features overview..................................................................................... 16 Bluetooth RF ................................................................................................................... 16 Bluetooth baseband ....................................................................................................... 16

Power management unit (PMU) features overview ......................................................................... 17 Package ............................................................................................................................................. 17

Functional Description .......................................................................................................................... 18

DSP Host Processor ........................................................................................................................... 18 Cadence® HiFi Mini®Audio Engine DSP coprocessor with HiFi EP® extension................ 18 Cache controller .............................................................................................................. 19 Local Memory ................................................................................................................. 19 Memory Management .................................................................................................... 20 Interrupt ......................................................................................................................... 20

Platform description ......................................................................................................................... 20 Boot mode ...................................................................................................................... 20 Trapping and mode selection ......................................................................................... 20 Bus Architecture ............................................................................................................. 21

Clock source and structure ............................................................................................................... 23 Clock architecture ........................................................................................................... 23 Digitally controlled crystal oscillator............................................................................... 24 32kHz low-speed internal RC (EOSC32) .......................................................................... 25 Low-power oscillator (LPOSC) ......................................................................................... 25 Phase locked loop ........................................................................................................... 26

Peripheral description ...................................................................................................................... 27 General purpose input/output (GPIO) ............................................................................ 27 Direct memory access (DMA) ......................................................................................... 27 General purpose timer (GPT) .......................................................................................... 29 True random number generator (TRNG) ........................................................................ 29 Real time clock (RTC) ...................................................................................................... 29 Pulse width modulation (PWM) ..................................................................................... 30 Inter-integrated circuit controller (I2C) ........................................................................... 30 Universal asynchronous receiver/transmitter (UART) .................................................... 30 Serial peripheral interface (SPI) ...................................................................................... 31

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Serial flash controller (SFC) ............................................................................................. 35 Audio system .................................................................................................................................... 36

General descriptions ....................................................................................................... 36 Audio codec .................................................................................................................... 37 Asynchronous sample rate converter ............................................................................. 48 Audio frontend memory interface .................................................................................. 52 Audio inter connection ................................................................................................... 52 Audio hardware gain ...................................................................................................... 52 Audio Up-sampler ........................................................................................................... 53 Audio Down-sampler ...................................................................................................... 53 Audio PLL frequency tuner ............................................................................................. 53

I2S .................................................................................................................................... 54 Active noise cancellation (ANC) ...................................................................................... 59 Audio system miscellaneous blocks ................................................................................ 60

Connectivity System ......................................................................................................................... 60 Connectivity features overview ...................................................................................... 60 Connectivity system ........................................................................................................ 61 Modem ........................................................................................................................... 62

Analog Baseband .............................................................................................................................. 62 Low-power oscillator (LPOSC) ......................................................................................... 62 Phase locked loop ........................................................................................................... 63 Auxiliary ADC (AUXADC) ................................................................................................. 64 VAD (Voice amplitude detect) ........................................................................................ 66

Capacitive Touch Control .................................................................................................................. 67 Block description ............................................................................................................ 67 Functional specifications ................................................................................................ 67

Bluetooth RF Subsystem ....................................................................................................................... 69

Bluetooth description ....................................................................................................................... 69 Functional specifications .................................................................................................................. 69

Basic data rate – receiver specifications ......................................................................... 70 Basic data rate – transmitter specifications ................................................................... 70 Enhanced data rate – receiver specifications ................................................................. 71 Enhanced data rate – transmitter specifications ............................................................ 72 Bluetooth LE – receiver specifications ............................................................................ 73 Bluetooth LE – transmitter specifications ....................................................................... 74

Power Management Unit and Low-Power Control System ................................................................... 75

Low-power control system ............................................................................................................... 75 General descriptions ....................................................................................................... 75 PMU architecture for low-power operating mode ......................................................... 75

Power Management / Regulation .................................................................................................... 78 Introduction .................................................................................................................... 78 Power-on/off sequence .................................................................................................. 78 BUCK regulator ............................................................................................................... 80 LDO regulator ................................................................................................................. 81 Power management unit (PMU) ..................................................................................... 81 Li-ion battery charger ..................................................................................................... 81 1-Wire UART for charger case application ...................................................................... 84

Pin Description ..................................................................................................................................... 85

AB1562 series ................................................................................................................................... 85 AB1562 series ball diagram ............................................................................................ 85 AB1562 series pin multiplexing ...................................................................................... 89

AB1561 series ................................................................................................................................... 93 AB1561 series ball diagram ............................................................................................ 93

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AB1561 series pin multiplexing ...................................................................................... 97

Electrical Characteristics ..................................................................................................................... 102

Absolute maximum ratings ............................................................................................................. 102 AB1562/AB1561 series ................................................................................................. 102

Power .............................................................................................................................................. 102 VDD33 LDO ................................................................................................................... 102 VRF11 LDO .................................................................................................................... 103 VDIG18 LDO .................................................................................................................. 103

Battery charger ............................................................................................................................... 103 Electrostatic discharge (ESD) ratings .............................................................................................. 104 Operating conditions ...................................................................................................................... 104

AB1562/AB1561 series ................................................................................................. 104 Peripheral interface ........................................................................................................................ 111

SPI master interface characteristics ............................................................................. 111

Package Information ........................................................................................................................... 113

AB1562 and AB1561 series mechanical data of the package ......................................................... 113

Ordering Information .......................................................................................................................... 116

AB1562A top marking ..................................................................................................................... 116 AB1562F top marking ..................................................................................................................... 116 AB1562M top marking .................................................................................................................... 116 AB1561M top marking .................................................................................................................... 117 AB1562U top marking .................................................................................................................... 117

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List of Figures and Tables

Figure 1.2-1. System Architecture ......................................................................................................................... 13

Figure 2.2-1. Block diagram .................................................................................................................................. 21

Figure 2.3-1. Clock source architecture ................................................................................................................ 24

Figure 2.3-2. Block diagram of APLL1 clock sources ............................................................................................. 26

Figure 2.4-1. Variety data paths of DMA transfers ............................................................................................... 28

Figure 2.4-2. DMA block diagram .......................................................................................................................... 29

Figure 2.4-3. PWM waveform ............................................................................................................................... 30

Figure 2.4-4. Pin connection between SPI master and SPI slave .......................................................................... 32

Figure 2.4-5. SPI transmission formats ................................................................................................................. 33

Figure 2.4-6. Operation flow with and without PAUSE mode ............................................................................... 33

Figure 2.4-7. CS de-assert mode ........................................................................................................................... 34

Figure 2.4-8. SPI master controller critical path sampling .................................................................................... 34

Figure 2.4-9. SPI master controller SCK and data delay ........................................................................................ 35

Figure 2.5-1. Audio System Block Diagram ........................................................................................................... 36

Figure 2.5-2. Block Diagram of Audio Uplink ........................................................................................................ 38

Figure 2.5-3. Audio Uplink Block Diagram............................................................................................................. 40

Figure 2.5-4. Block Diagram of Audio Downlink ................................................................................................... 43

Figure 2.5-5. Audio Downlink Block Diagram ........................................................................................................ 45

Figure 2.5-6. ASRC Block Diagram ......................................................................................................................... 48

Figure 2.5-7. 192 kHz to 96 kHz down-sample simulation result (FSO/FSI=0.500) ............................................... 50

Figure 2.5-8. 44.1 kHz to 192 kHz up-sample simulation result (FSO/FSI=4.354) ................................................. 51

Figure 2.5-9. I2S Timing Requirement Waveform ................................................................................................. 56

Figure 2.5-10. I2S Bus Protocol: I2S Format .......................................................................................................... 57

Figure 2.5-11. I2S Bus Protocol: EIAJ Format ......................................................................................................... 57

Figure 2.5-12. I2S Bus Protocol: LJ Format ............................................................................................................ 58

Figure 2.5-13. I2S Bus Protocol: RJ Format ............................................................................................................ 58

Figure 2.5-14. ANC Concept .................................................................................................................................. 59

Figure 2.5-15. Feed-forward ANC system ............................................................................................................. 59

Figure 2.5-16. Hybrid ANC system ........................................................................................................................ 60

Figure 2.6-1. Link manager .................................................................................................................................... 62

Figure 2.7-1. Block diagram of APLL1 clock sources ............................................................................................. 63




Figure 3.1-1. Bluetooth RF transceiver system ..................................................................................................... 69

Figure 4.1-1. PMU power grid ............................................................................................................................... 75

Figure 4.1-2. System power state ......................................................................................................................... 76

Figure 4.2-1. Power blocks .................................................................................................................................... 78

Figure 4.2-2. Power-on/off control sequence by REGEN or charger plug in (OFF-mode) ..................................... 79

Figure 4.2-3. Power-on/off control sequence by REGEN or charger plug in (RTC mode) ..................................... 80

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Figure 4.2-4. Buck regulators circuit ..................................................................................................................... 81

Figure 4.2-5. Voltage regulators circuit ................................................................................................................. 81

Figure 4.2-6. Battery charger circuit ..................................................................................................................... 82

Figure 4.2-7. Charging profile ................................................................................................................................ 83

Figure 4.2-8. 1-wire UART function block ............................................................................................................. 84

Figure 5.1-1. AB1562 series lead diagram and top view ....................................................................................... 85

Figure 5.1-2. AB1562 series GPIO block diagram .................................................................................................. 89

Figure 5.2-1. AB1561 series lead diagram and top view ....................................................................................... 93

Figure 5.2-2. AB1561 series GPIO block diagram .................................................................................................. 98

Figure 6.6-1. SPI master interface timing diagram (CPHA=0) ............................................................................. 111

Figure 6.6-2. SPI master interface timing diagram (CPHA=1) ............................................................................. 112

Figure 7.1-1. Outlines and dimensions of AB1562 series SQFN of 4mm*6.5mm, 44-lead, 0.4mm pitch package115

Table 1.1-1. AB1562 product family ...................................................................................................................... 12

Table 1.3-1. Peripherals ........................................................................................................................................ 14

Table 2.1-1. Instruction RAM and Data Ram ......................................................................................................... 20

Table 2.2-1. Trapping pin list ................................................................................................................................. 21

Table 2.2-2. Trap pin electric characteristics ........................................................................................................ 21

Table 2.2-3. Bus connection .................................................................................................................................. 22

Table 2.3-1. DCXO Characteristics (TA = 25 oC, VDD = 1.1V unless otherwise stated) (1) .................................... 24

Table 2.3-2. Functional specifications of EOSC32 ................................................................................................. 25

Table 2.3-3. LPOSC specifications ......................................................................................................................... 25

Table 2.3-4. APLL specifications ............................................................................................................................ 26

Table 2.4-1. SPI master interface .......................................................................................................................... 32

Table 2.5-1. Audio uplink Specifications ............................................................................................................... 38

Table 2.5-2. MICBIAS specifications ...................................................................................................................... 38

Table 2.5-3. Audio Uplink Digital Filter Specifications in 8 KHz............................................................................. 41

Table 2.5-4. Audio Uplink Digital Filter Specifications in 16 KHz........................................................................... 41




Table 2.5-8. Audio Uplink Digital Filter Specifications in 192 KHz......................................................................... 41

Table 2.5-9. Audio Downlink Specifications .......................................................................................................... 43

Table 2.5-10. Audio Downlink Digital Filter Specifications in Voice Mode ........................................................... 45

Table 2.5-11. Audio Downlink Digital Filter Specifications in Audio Mode ........................................................... 46

Table 2.5-12. ASRC Digital Filter Specifications ..................................................................................................... 49

Table 2.5-13. Comparison with Audio Codec, I2S Master and I2S Slave mode ...................................................... 54

Table 2.5-14. I2S Protocol Specifications ............................................................................................................... 54

Table 2.5-15. I2S Bit Clock Jitter Percentage that generated from APLL ............................................................... 55

Table 2.5-16. I2S Word Select Clock Jitter Percentage that generated from APLL ................................................ 55

Table 2.5-17. I2S Bit Clock Jitter Percentage that generated from XO .................................................................. 55

Table 2.5-18. I2S Word Select Clock Jitter Percentage that generated from XO ................................................... 55

Table 2.5-19. I2S Timing Requirements ................................................................................................................. 56

Table 2.7-1. LPOSC specifications ......................................................................................................................... 62

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Table 2.7-2. APLL specifications ............................................................................................................................ 63

Table 2.7-3. Auxiliary ADC input channels ............................................................................................................ 64

Table 2.7-4. Auxiliary ADC Specifications .............................................................................................................. 65

Table 2.7-5. VAD input channels ........................................................................................................................... 66

Table 2.7-6. VAD Specifications ............................................................................................................................ 66

Table 2.8-1. Capacitive touch input channels ....................................................................................................... 67

Table 2.8-2. Touch Control Specifications ............................................................................................................. 68

Table 3.2-1. Basic Data Rate – receiver specifications .......................................................................................... 70

Table 3.2-2. Basic Data Rate – transmitter specification ...................................................................................... 70

Table 3.2-3. Enhanced Data Rate –Receiver Specifications .................................................................................. 71

Table 3.2-4. Enhanced Data Rate – transmitter specifications ............................................................................. 72

Table 3.2-5. Bluetooth LE 1M – receiver specifications ........................................................................................ 73

Table 3.2-6. Bluetooth LE 2M – receiver specifications ........................................................................................ 73

Table 3.2-7. Bluetooth LE 1M – transmitter specification .................................................................................... 74

Table 3.2-8. Bluetooth LE 2M – transmitter specification .................................................................................... 74

Table 4.1-1. Off, RTC, and sleep scenarios ............................................................................................................ 76

Table 4.1-2. Active scenarios ................................................................................................................................ 77

Table 4.1-3. System Wakeup Source ..................................................................................................................... 77

Table 4.2-1. VBUS_UART PSW .............................................................................................................................. 84

Table 5.1-1. AB1562 series pin coordinates .......................................................................................................... 86

Table 5.1-2. Acronym for pin types and I/O structure .......................................................................................... 86

Table 5.1-3. AB1562 series pin function description and power domain ............................................................. 87

Table 5.1-4. PinMux description ........................................................................................................................... 90

Table 5.1-5. RTC PinMux description .................................................................................................................... 90

Table 5.1-6. Peripheral functions and signals ....................................................................................................... 91

Table 5.2-1. AB1561 series pin coordinates .......................................................................................................... 94

Table 5.2-2. Acronym for pin types and I/O structure .......................................................................................... 94

Table 5.2-3. AB1561 series pin function description and power domain ............................................................. 95

Table 5.2-4. PinMux description ........................................................................................................................... 99

Table 5.2-5. RTC PinMux description .................................................................................................................... 99

Table 5.2-6. Peripheral functions and signals ..................................................................................................... 100

Table 6.1-1. Absolute maximum ratings for power supply ................................................................................. 102

Table 6.1-2. Absolute maximum ratings for I/O power supply ........................................................................... 102

Table 6.1-3. Absolute maximum ratings for voltage input ................................................................................. 102

Table 6.1-4. Absolute maximum ratings for storage temperature ..................................................................... 102

Table 6.2-1. VDD33 LDO ...................................................................................................................................... 103

Table 6.2-2. VRF11 LDO ....................................................................................................................................... 103

Table 6.2-3. VDIG18 LDO ..................................................................................................................................... 103

Table 6.3-1. Battery Charger ............................................................................................................................... 103

Table 6.4-1. ESD electrical characteristic of AB1562/AB1561 series .................................................................. 104

Table 6.5-1. AB1562/AB1561 series general operating conditions .................................................................... 104

Table 6.5-2. Recommended operating conditions for power supply.................................................................. 104

Table 6.5-3. Recommended operating conditions for voltage input .................................................................. 105

Table 6.5-4. Recommended operating conditions for operating temperature .................................................. 105

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Table 6.5-5. Electrical characteristics .................................................................................................................. 105

Table 6.6-1. SPI master interface characteristics ................................................................................................ 112

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System Overview

Product series

The AB1562 product family provides different packages for different market purposes. Table 1.1-1 shows the comparison of the AB1562 series chipsets.

Table 1.1-1. AB1562 product family

Item AB1562M AB1562A AB1562F AB1561M AB1562U

Feed-forward ANC

– Yes Yes – –

Hybrid ANC – Yes – – –

Audio Mono Mono Mono Stereo Mono

VBUS_UART Yes Yes Yes – Yes

SiP flash size 32Mb 16Mb 16Mb 32Mb 16Mb

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System architecture

Clock Management

Audio Subsystem

I2C x 2

PWM x 2Sy

stem

Bu

s SPMSYS

SFCSIP FLASH

Power Management IC

DMAAUXADC

(4 channels)

SPI master x 1

PIN

MU

X

VBAT

XTAL26 MHz

Tensilica DSP208 Mhz

I-Cache32 KB

SYSRAM8KB

TRNG

D-Cache8 KB

I-RAM160 KB

D-RAM384 KB

I2S Master x 2

DMIC interface x 2 from GPIO

I2S Slave x 1

Cap Touch(3 channels)

Hig

h P

erform

an

ceA

ud

io A

DC

x 2

Audio SRAM

UART x 2

EINT x 9(incl. 2 RTC EINT)

DM

IC in

terface x 2

RGU

Timer

Syst

em B

us

Blue Tooth RF

Blue Tooth Baseband

MIC

BIA

S x 2RTC PLL

BR

BT 5.XEDR

GPIO x 9(incl. 2 RTC GPIO)

*Support up to 4 DMIC interfaces, among them, 2 share pins with audio ADC and 2 share GPIO.

AUDIO PIN MUX

Hig

h P

erform

an

ceA

ud

io D

AC

x 1

BLE

DCXO OSC

Vo

ice activ

ity d

ete

ction

ROM 16KB

Figure 1.2-1. System Architecture

Platform features overview

Host processor DSP subsystem


7-stage pipeline

Maximum speed: 208MHz

32 maskable interrupts with 4 priority levels and a NMI (non-maskable Interrupt)

32kB instruction cache and 8kB data cache with high hit rate and zero wait state

160kB instruction RAM with zero wait state

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384kB data RAM with zero wait state and four memory banks to increase co-access performance.

Memory summary

System in Package (SiP) 16Mb low-power flash memory with 0.1µA deep-down current (typical condition) and maximum speed 104MHz (AB1562U, AB1562A and AB1562F)

System in Package (SiP) 32Mb low-power flash memory with 0.1µA deep-down current (typical condition) and maximum speed 104MHz (AB1562M and AB1561M)

Low latency 8kB system RAM (SYSRAM) with maximum speed 104MHz

Peripheral interfaces summary

The following interfaces are multiplex with GPIO.

Table 1.3-1. Peripherals

Peripheral Counts Description

GPIO 9 include 2 RTC GPIOs: 1 dedicated + 1 (shared with Cap-touch wakeup)

PWM 2 Maximum toggle rate 24MHz

I2C 2 Master mode, 400kbps, Up to 3.4Mbps

UART 2 Up to 3Mbps, Both UART0 and UART1 can support the flow control feature (RTS/CTS)

SPI master 1 Clock up to 52MHz

AUXADC 4-channel 12-bit ADC, pin mux by AGPIO

I2S 2 Each I2S can be set as either master or slave mode.

SFC

(code + data)

1 master

(for internal flash)

Serial Flash Controller (SFC) interface, clock up to 104MHz

Security

True random number generator

Security JTAG

Others

System dynamic frequency scaling (DFS), detail please check Table 6.5-1. AB1562/AB1561 series general operating conditions

17 DMA channels

Single RTC timer

Seven 32-bit general purpose timers (GPTs)

Watchdog timer (WDT)

Capacitive Touch Control

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Audio features overview

The features of the audio system are listed as below sections. The audio codec part includes the uplink path, downlink path, side-tone filter, and digital controller for Class D amplifier. The other audio functions include the asynchronous sample rate converter, audio front-end memory interface, inter-connection, hardware gain, audio PLL frequency tuner, I2S, and IRQ counters.

Audio codec feature overview

Support for three uplink paths with analog/digital MIC input modes. The maximum supported sample rate is 192 KHz. The uplink paths are 24-bit width data precision.

Support for 1 downlink path. The maximum supported sample rate is 192 KHz. The downlink path is 24-bit width data precision.

Class D amplifier is used in playback scenario.

The proposed side-tone filter is designed for reducing the noise effect from the echo path.

Audio other functions feature overview

Asynchronous Sample Rate Converter is a two-channel asynchronous sample rate converter designed for high

quality digital audio applications with the following features:

o Use the input buffer pointer and output buffer pointer to control memory-based processing

o Support for one stereo channel-set per asynchronous sample rate converter.

o Each channel set has its own anti-alias filter.

o Support for 16/32-bit input and output data formats.

o Support for the frequency auto-tracking mechanism.

o Input interface is memory output interface can be memory or audio inter connection.

Audio front-end memory interface is designed for accessing the audio internal SRAM by agents which manage

the data alignment and FIFO controls with the following features:

o Support for four downlink and five uplink agents which can operate at the same time.

o Support for a 16/24-bit data format.

The audio inter-connection manages the internal routing of input sources to output destinations with the

following features:

o Include 44 inputs and 38 outputs where any inputs can be connected to any outputs.

o Support for 24-bit input and 16/24-bit output data formats.

The audio hardware gain is applied to change the volume smoothly with the following features:

o Support for the adjustable gain ranged from 0 to 1 with a 20-bit configurable unsigned register.

o Hardware chases the target gain by configuring the registers.

o The gain step and sample per step can be set by the control registers.

The proposed audio PLL frequency tuner is to compare and provide feedback about the difference to fine tune

APLL.

The proposed I2S interface is designed to be compactible to the standard I2S protocol with the following

features:

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o Support for I2S master and slave modes.

o Support for the 16/24-bit data addressing format.

o Support for mono or stereo data transactions.

o Support for maximum sample rate 192KHz.

The proposed audio IRQ counters are configured to control the IRQ asserted timing to DSP. The features are

shown as below:

o 10 IRQ counters are usable.

o Support for counting rates up to 192KHz.

o The maximum number of the counters are up to 218 – 1.

o Configurable IRQ destinations to DSP for all IRQ counters

Support the following uplink sample rate

o 8k, 16k, 32k, 48, 96, 192kHz

Support the following downlink sample rate

o 8k, 11.025k, 12k, 16k, 22.05k, 24k, 32k, 44.1k, 48k, 96k, 192kHz

Connectivity (Bluetooth) features overview

This chip offers a highly integrated Bluetooth radio and baseband processor. Only a minimum of external components is required. This chip is fully compliant with Bluetooth version 5.2. It is upgradable to later versions, including BR/EDR and Bluetooth LE1M/2M and offers enhanced data rates of up to 3Mbps. It also provides the coexistence protocol with IEEE 802.11 protocol.

Bluetooth RF

Fully compliant with Bluetooth core specification 5.2.

Low-IF architecture with high degree of linearity and high order channel filter.

Integrated T/R switch and balun.

Fully integrated PA provides 10dBm output power.

-96dBm sensitivity with interference rejection performance.

Hardware AGC dynamically adjusts the receiver performance in changing environments.

Bluetooth baseband

Bluetooth specification V5.2 + dual mode + isochronous channel

Up to four simultaneous active ACL links.

Up to four simultaneous active Bluetooth LE links.

Support for single SCO or eSCO link with CVSD/mSBC coding.

Support for BLE1M/2M

Up to simultaneous active ICO/ICL links (ICO+ICL links=4)

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Support for AWS (Advanced Wireless Stereo) for two headsets (Speaker1 and Speaker2) sync with phone and

play audio at the same time.

AFH and PTA collaborative support for WLAN/Bluetooth coexistence.

Supports PCM interface and built-in programmable transcoders for linear voice with re-transmission.

Built-in hardware modem engine for access code correlation, header error correction, forward error correction,

CRC, whitening and encryption.

Channel quality driven data rate adaptation.

Channel assessment for AFH.

Power management unit (PMU) features overview

Two Buck regulators

Three LDO regulators

Li-ion battery charger for internal charging

Package

For AB1562/AB1561 series, a SQFN 4mm*6.5mm, 44-lead, 0.4mm pitch package is offered

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Functional Description

DSP Host Processor


The DSP host processor uses Cadence Hifi Mini DSP audio processor as the CPU core. The Cadence HiFi Mini DSP is a highly optimized audio processor geared for efficient execution of audio and voice codecs and pre- and post-processing modules. The HiFi Mini DSP is included in Xtensa LX processor family. HiFi Mini is an enhanced version of the HiFi 2 architecture especially well-suited for extremely low power voice recognition and voice processing. The use of a 40-bit VLIW instruction word (compared to the 64-bits of HiFi 2) as well as support for additional 16-bit instructions and bidirectional shifts result in significantly smaller code size. Additional instructions have been added for voice recognition applications. HiFi Mini is a SIMD (single-instruction/multiple-data) processor, it has the ability to work in parallel on two data items at the same time. For example, it allows for one operation to perform two 24-bit additions in parallel, with each addition occupying half of a 48-bit AE_PR register. The favored data size of the architecture is 24 bits for operands and 56 bits for accumulators, providing eight extra guard bits. HiFi Mini also supports 16-bit loads and stores and 8-bit loads that expand into the 24-bits available in the AE_PR registers. HiFi Mini supports dual 32x16-bit multipliers, in addition to the dual 24x24-bit, but because the 32-bit operand must come from the accumulator register, 32x16-bit multipliers are often less efficient than the 24x24-bit. Support for a single 16x16-bit multiplier using a 32-bit accumulator enables better support for voice algorithms. HiFi Mini is a VLIW architecture, supporting the execution of two operations in parallel. DSP loads and stores, bitstream and Huffman operations and core operations are available in slot 0 of a VLIW instruction. DSP MAC and ALU operations are available in slot 1.


DSP host processor includes the HiFi EP Audio Engine DSP extension configuration option which extends the HiFi 2 Audio Engine ISA with 32x24-bit multiply/accumulate operations, circular buffer loads and stores, a slot 0 select unit and bidirectional shifts.

Pipeline stages

The DSP host processor has a 7-stage pipeline. The 7-stage pipeline has a 2-cycle latency for both the instruction-memory fetch and for the data-memory fetch. Pipeline length 7

Instruction Memory Fetch Latency 2

Cycle of Execute stage 1

Cycle of Modify stage 3

Cycle of Write-back stage 4

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Cache controller

The DSP host processor includes a cache controller with 32kB Instruction Cache + 8KB Data Cache implemented to improve the code/data fetch performance when CPU accesses a non-zero wait-state memory through the on-chip bus. The CPU has separate data and instruction caches to significantly improve processor performance.

Write-back is supported on the data cache to improve performance. The data cache can be programmatically toggled between write-back and write-through.

Dynamic way disable is supported on both instruction cache & data cache. The dynamic cache way disable capability gives the ability to disable and re-enable the use of cache ways in both Instruction- Cache and Data-Cache independently to facilitate power savings. New and modified instructions enable the user to clean cache ways before disabling them and to initialize cache ways while enabling them. When a Cache Way is disabled, it removes that cache memory block from service. Therefore it reduces total cache capacity by 1/(number of ways in service).

Instruction Cache Details

Instruction Cache size in bytes 32768

Instruction Cache ways 4

Instruction Cache line size bytes 64

Dynamic Way Disable Supported

Instruction Cache Details

Data Cache size in bytes 8192

Data Cache ways 2

Data Cache line size bytes 32

Data Cache write-back Supported

Dynamic Way Disable Supported

Local Memory

Local RAM provides instructions or data to the Xtensa processor core in the shortest time possible. Local RAM has an advantage over cache because cache misses trigger AHB accesses, which are much slower in servicing memory requests than local memory ports.

Local RAMs are designed for applications requiring high speed, low latency and low power consumption. Local RAMs have three power state; active, retention or power-down. Local RAMs must be in active state for normal read and write access. Retention state saves the RAM content and consumes the minimum leakage current with no access. Power-down state loses the content and consumes almost zero power.

The Local RAMs can also be accessed by other internal AHB masters like DMA or multimedia subsystem.

Both Instruction RAM and Data RAM are available in DSP. A synchronous instruction or data RAM with 2-cycle latency is connected to a RAM interface port and is mapped to a contiguous address range. The instructions or data are accessed when the fetch or load/store address calculated by the processor core falls within the configured address range of the RAM.

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Table 2.1-1. Instruction RAM and Data Ram

Memory Size Address Banks AHB Slave Access

Instruction RAM Port 0

160KB 0x04580000 1 Yes

Instruction RAM Port 1

16KB 0x04600000 1 Yes

Data RAM Port 0 256KB 0x04500000 4 Yes

Data RAM Port 1 128KB 0x04540000 4 Yes

Memory Management

Region protection with translation is used to manage the CPU access to memory. It provides full support for:

Protection regions up to eight regions.

Provides a protection field for each of the eight 512 MB regions in the address space.

The field can allow access to the region and it can set caching characteristics for the region, such as whether or not the cache is used and if it is write-through or write-back.

Virtual-to-physical translation on Each of the eight 512 MB regions

Interrupt

The CPU supports 32 maskable interrupts with four priority levels and a NMI (non-maskable Interrupt).

Platform description

Boot mode

Flash download mode or normal boot mode:

Flash download mode. The bootloader is part of the flash and can be reprogrammed through the UART interface.

The flash is embedded in the package.

Normal boot up mode. In this mode, boot ROM copies the bootloader from the flash to the internal memory, without entering flash download mode. When the system finishes boot ROM execution, it will jump to bootloader and execute it.

Trapping and mode selection

Mode selection:

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Table 2.2-1. Trapping pin list

Mode selection Trapping pin

Description Trapping condition

Mode for testing

GPIO0 Airoha in-house testing purpose

DVDD_IO_0 : Normal mode (default)

GND : Testing mode

Power-on reset

Trapping pin characteristics

Trapping pin characteristic:

Table 2.2-2. Trap pin electric characteristics

Trapping pins

default pull direction Internal pull resistor value

GPIO0 Internal pull up 75kΩ

Trapping timing diagram

The GPIO value is latched into trapping mode when the power-on reset de-assert (goes from low to high).

VDIG18(VRTC)

VDDK

Other power domain

…...

Power on sequence

> 20ms

Latch GPIO0 value (high): enter normal mode

Power-on reset

Example1: GPIO0

Example2: GPIO0

Latch GPIO0 value (GND): enter in-house testing mode

…...Latch GPIO value for trapping

Figure 2.2-1. Block diagram

The mode trapping pin is for Airoha in-house testing purpose. Please make sure not to pull down GPIO0, or boot up system will fail.

Bus Architecture

The main system consists of a 32-bit multilayer AHB bus matrix that interconnects:

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Masters:

- Cadence HiFi Mini Audio Engine DSP master bus

- Direct Memory Access (DMA) bus

- Sleep Process Manager (SPM)

- Serial Peripheral Interface (SPI) DMA bus

- Connectivity System (CONNSYS) master bus

- Audio System (AUDIOSYS) master bus

- Test Interface Unit (TIU)

Slaves:

- AHB peripheral including AHB to APB bridges and APB peripherals

- Embedded flash

- Main System SRAM (SYSRAM)

- Cadence HiFi Mini Audio Engine DSP slave bus

- Connectivity system slave bus

- Audio system slave bus

The bus matrix provides access from a master to a slave, enabling concurrent access and efficient operation, even when several high-speed peripherals are working simultaneously. The architecture for this matrix is shown in Table 2.2-3.

Table 2.2-3. Bus connection

Master

Slave

DSP Master

DMA SPM SPI Master

CONNSYS Master

AUDIOSYS Master

TIU

AO APB

Peripherals

● ● ● ● ● ● ●

PD APB

Peripherals

● ● ● ● ● ● ●

Flash ● ● ● ● ● ● ●

SYSRAM ● ● ● ● ● ● ●

DSP Slave ● ● ● ● ● ●

CONNSYS

Slave

● ● ● ● ● ●

AUDIOSYS

Slave

● ● ● ● ● ●

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Clock source and structure

Clock architecture

The clock controller (see Figure 2.3-1) distributes the clocks from different oscillators to the core circuit and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. The clock controller features:

Clock prescaler — provides the best trade-off between speed and current consumption. A programmable prescaler can adjust the clock frequency to the CPU and peripherals.

Safe clock switching — clock sources can be adjusted during runtime through a configuration register.

Clock management —the clock controller can stop the clock of the core circuit, individual peripherals or memory to reduce the power consumption. The AHB and APB clocks support dynamic clock slow down or gating when bus fabric is idle.

System clock source — three different clock sources can be used to drive the system clock (FSYS):

o 26MHz Digitally Controlled Crystal Oscillator (DCXO) that can supply reference clock for PLLs.

o Low-power RC oscillator (LPOSC) — low-power consumption with large frequency variation, maximum frequency at 416MHz.

Auxiliary clock source — There are two low-power clock sources to drive the real-time clock, DCXO32K and EOSC32K.

o 32.768 kHz low-speed internal clock fed by DCXO (DCXO32K).

o 32.768 kHz low-speed internal RC (EOSC32K) with larger frequency variation compared to DCXO32K.

Peripheral clock sources — Three types of peripheral clock source options are used. Each peripheral has its own gating register:

Peripherals, such as SFC and SPI have their own independent clock sources, LPOSC and divided clock, each having independent outputs enabling high flexibility.

The clock source of peripherals, such as DMA is the same as AHB/APB bus clock (FBUS).

The clock source of low-speed peripherals, including I2C, SLOW_DMA and AUXADC is from general 26MHz MUX.

Clock-out capability:

CLKOUT. Outputs 32.768 kHz clock from DCXO or EOSC. Outputs 26 MHz/any frequency divided from 2~4096 from DCXO. Outputs 41.6/26/10.4 MHz from LPOSC.

DCXO 26MHz is selected as a default system clock when powering up or resetting the chip. LPOSC provide clock to increase the CPU frequency (FSYS) up to 208MHz when VCORE is 0.8V.

Several prescalers can be used to configure the CPU and bus. The maximum frequency of the AHB1 and APB1 buses (FBUS) is 104 MHz when VCORE is 0.8V. The low-speed APB2 bus domain is 26 MHz.

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26MHz DCXO

OSC_XOUT

OSC_XIN

CLKO

DCXO32K

32.768KHzEOSC32K

To 26M bus and peripheral clocks

OSC_CLK416MHzLPOSC

APLL

/F

Divider

Prescaler

/1, 2,…, 64

Prescaler

/1, 2,…, 64

DCM

To DSP

To bus, SYSRAM

To peripheral clocks

To Watchdog

/2

To general

purpose timer

To RTC

To Audio intbus

To Audio Uplink

To Audio GPSRC

To SFC

APLL_CK To SPIMST

To Audio Dwlink

To Audio INTF

To Audio Engine

/2~4096

Figure 2.3-1. Clock source architecture

Digitally controlled crystal oscillator

The Digitally Controlled Crystal Oscillator (DCXO) uses a two-pin 26MHz crystal resonator. The DCXO supports 1612 crystal footprint. Refer to Table 2.3-1 for the crystal load capacitance and the tuning sensitivity range. On-chip programmable capacitor array supports DCXO fine frequency tuning, ranging from - 30ppm to + 30 ppm.

Table 2.3-1. DCXO Characteristics (TA = 25 oC, VDD = 1.1V unless otherwise stated) (1)

Parameter Symbol Conditions Min. Typ. Max. Unit

Operating frequency Fref 26 MHz

Crystal C load CL 7 pF

Frequency Tolerance - 1. Calibrated at room temperature

2. Valid for temperature -40 to 85C.

-15 0 +15 ppm

Crystal tuning sensitivity

TS 9.5 11.0 ppm/pF

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Parameter Symbol Conditions Min. Typ. Max. Unit

Static range SR CDAC from 0 to 511 -30 +30 ppm

Start-up time DCXO Frequency error < 20ppm

Amplitude > 90 %

0.6

2.5

ms

Pushing figure 0.2 ppm/V

Fref buffer output level

VFref Max. loading = 10pF 0.70 0.75 Vp-p

Fref buffer output phase noise

10kHz offset Jitter noise -138 dBc/Hz

(1) Guaranteed by design, not tested in production.

32kHz low-speed internal RC (EOSC32)

The low-power 32.768 kHz embedded oscillator EOSC32 is designed to support function without a 32.768 kHz crystal. The key performance is shown below.

Table 2.3-2. Functional specifications of EOSC32

Symbol Parameter Min. Typical Max. Unit

VDIG18 RTC module power

1.8

V

Fout Output clock frequency 32.768 kHz

Dcyc Duty cycle 30 50 70 %

Current consumption 3 μA

T Operating temperature -40 85 °C

Low-power oscillator (LPOSC)

Functional description

There is a low-power RC oscillator (LPOSC) generating 416 MHz clock output with ± 4% frequency variation. The benefit of a RC oscillator is that reference clock is not necessary. Moreover, this oscillator has a very low-power feature (< 0.15mA) and fast settling (< 20us). To overcome the process variation, the software calibrates this OSC by frequency meter before using them.

Functional specifications

Table 2.3-3. LPOSC specifications

Symbol Parameter Min. Typ. Max. Unit

Fout Output clock frequency - 416 - MHz

Settling time - 20 - μs

Output clock duty cycle 40 50 60 %

Output clock jitter (period jitter) - ±150 - ps

DVDD Digital power supply 0.675 0.7/0.8/0.9 0.99 V

AVDD Analog power supply 1.62 1.8 1.98 V

T Operating temperature -40 - 125 °C

Current consumption 0.15 mA

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Power-down current consumption - 1 - μA

Phase locked loop

Block description

PRE-DIV APLL

DIV-N

DDS

POST-DIV26MHz CLK

FOUT

0

1

DIV16

DDS Enable

Figure 2.3-2. Block diagram of APLL1 clock sources

A fractional-N APLL with an 8-bit integer and 24-bit fractional divisor is programmable to generate clocks ranging from 0.5GHz to 1.5GHz.

Figure 2.3-2 shows the block diagram of the APLL clock source, which is composed of typical PLL components such as phase-frequency detector, charge pump, low pass filter, voltage-controlled oscillator and frequency dividers.

The feedback divider of PLL is implemented by an 8-bit multi-modulus divider (MMD), which can operate at very high speed with wide divisor range. The divisor of MMD is controlled by the DDS to implement fractional-N frequency multiplication. The period-controlled word (PCW) of the DDS is a 32-bit binary number, which consists of an 8-bit integer part and a 24-bit fractional part. The pre-divider and the post-divider are both simple binary dividers, which are added to facilitate the frequency configuration of the PLL.

These PLLs do not require off-chip components to operate, and can be turned off to save power.

After powering up, the PLLs are all off according to the default control register setting. The source clock signal for the PLLs is selected through multiplexers from 26MHz XTAL. The software maintains the PLL lock time while the clock selection is changing.

For power management, the MCU software configuration may stop MCU Clock by setting up the Sleep Control Register. Any interrupt requests to MCU can pause the sleep mode and return the MCU to the running mode.

Function specifications

The function specifications of APLL are shown in the Tables below.

Table 2.3-4. APLL specifications


Fin Input clock frequency - 26 - MHz

Fout Output clock frequency - 45.1584 (VCO: 722.5344)

49.1526 (VCO: 786.432)

- MHz

Settling time - 50 - us

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Output clock duty cycle 44 50 56 %

Output clock jitter (rms period jitter) - ±75 - ps

Frequency Tuning -1 - 0 %

DVDD Digital power supply 0.675 0.7/0.8/0.9 0.99 V

AVDD Analog power supply 1.62 1.8 1.98 V

T Operating temperature -40 - 85 °C

Current consumption - 2 - mA

Power-down current consumption - 0.1 - µA

Peripheral description

General purpose input/output (GPIO)

The pin multiplexing and general purpose input/output (GPIO) controls the connections and functions of I/O pads. Each pad can function as GPIO to implement a variety of external function. Each pad can also work as an external interrupt (EINT) source to trigger interrupt when a transition is detected on the input. In addition, each pad is connected to up to six additional functions, with the selection controlled by the pin multiplexing module.

There are totally twelve modes for each I/O pad, including one GPIO mode and one EINT mode. In GPIO mode, the MCU can control the direction and output value of each pad, as well as read the input value. In EINT mode, an interrupt can be triggered when a transition is detected on the input.

The characteristics of I/O pad are configurable, including driving strength, pull-up/pull-down resistance, Schmitt trigger, and slew rate.

There are four clock-out ports and each of them can be programmed to output the appropriate clock.

Direct memory access (DMA)

Two DMA controllers are placed on AHB bus to support fast data transfers and off-load the processor. With the controllers, specific devices on AHB or APB buses benefit greatly from quick completion of data movement from or to memory modules. The DMA controllers can also be used to connect two devices other than memory modules, as long as they can be addressed in memory space. Figure 2.4-1 illustrates the system connections.

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Memory Arbiter

MCU_DMASLOW_DMA

I2S_DMA

Peripheral

MCU-DSPInterface

APBBridge

Peripheral

AHB Bus

APB Bus

Figure 2.4-1. Variety data paths of DMA transfers

There is a round-robin arbitration mechanism that supports up to 1 channel in MCU_DMA, 8 channels in SLOW_DMA and 8 channels in I2S_DMA working simultaneously. Each channel has similar set of registers to be configured to different schemes as desired. Both interrupt and polling-based schemes are supported to manage the completion events.

The operating block diagram of the DMAs is shown in Figure 2.4-2.

PDMA

VDMA

GDMA

Global Controller

APBInterface

AHBInterface

Configuration

Configuration Transaction

Transaction

Transaction

Configuration

Configuration

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Figure 2.4-2. DMA block diagram

General purpose timer (GPT)

The general purpose timer (GPT) includes seven 32-bit timers. Each timer has four operation modes, ONE-SHOT, REPEAT, freerun with interrupt (FREERUN_I), and FREERUN. The GPT can operate on either system clock (13MHz) or real-time clock (RTC, 32.768KHz). The GPT is an always-on IP, which means it retains the previous configuration and runs even if the system goes into sleep mode. Note, in sleep mode, the clock source must be set to RTC because there is no system clock.

Timer mode

Each GPT has four modes: ONE-SHOT; REPEAT; FREERUN_I; and FREERUN.

1) ONE-SHOT mode – An interrupt occurs and the timer stops once GPT is timed out.

2) REPEAT mode – An interrupt occurs and the timer resets once GPT is timed out.

3) FREERUN_I mode – An interrupt occurs and the timer continues once the GPT is timed out.

4) FREERUN mode – The GPT continues counting with no limit.

Timer clock source

Each GPT can operate on either system clock or RTC. There is also a 4-bit clock divider, which divides the clock by 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16, 32, or 64. Note, only RTC is available in sleep mode.

Timer interrupt source

All GPTs share a single interrupt source. The user can get the interrupt status by reading GPT_IRQSTA[7:0] and GPTx_IRQ_STA. To clear the interrupt, write 1 to GPTx_IRQ_ACK.

System wakeup source

The interrupt signal is also connected to System Power Management (SPM) as a wakeup source.

True random number generator (TRNG)

The true random number generator (TRNG) is a device in power-down domain that generates random numbers from the ring oscillator (RO) outputs. Various types of ROs are adopted, including hybrid Fibonacci ring oscillator (H-FIRO), hybrid ring oscillator (H-RO) and hybrid Galois ring oscillator (H-GARO). Interrupt request (IRQ) is issued when the random data is successfully generated.

Normal mode – turns on ROs and samples their output to generate random numbers. When the random

data is valid, IRQ is issued.

Freerun mode – continuously activates ROs to create interference on the power source. This can be used

to help prevent side-channel attacks. IRQ should be masked at this mode.

Real time clock (RTC)

The Real Time Clock (RTC) module provides time and data information and a 32.768kHz clock. The clock is selected between two internal clock sources: one is from the embedded oscillator (EOSC) and the other is from the digitally controlled crystal oscillator (DCXO).

When the chip is in RTC mode, a dedicated regulator supplies power to the RTC block. Because RTC is one of the designs powered on in RTC mode, a low power solution is provided to gate the 32.768kHz clock. To maintain RTC

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FOR andy.pang@ miuix.com.cn USE ONLY · 1.2 28 August 2020 Update hapter 4.2.2 Power-on/off sequence about REGEN time Update hapter 6.3 attery charger 1.3 22 September 2020 Update

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