FinFET: a mature multigate MOS technology? A wideband transistor simulation and characterization approach J.-P. Raskin 1 , T.M. Chung 1 , D. Lederer 1 , A. Dixit 2 , N. Collaert 2 , T. Rudenko 3 , V. Kilchytska 3 , D. Flandre 3 Université catholique de Louvain, 1 Microwave and 4 Microelectronics Laboratories Place du Levant, 3, B-1348 Louvain-la-Neuve, Belgium [email protected]2 IMEC, Kapeldreef, 75, B-3001 Leuven, Belgium 3 ISP, Kiev
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FinFET: a mature multigate MOS technology? A wideband transistor simulation and characterization approach J.-P. Raskin 1, T.M. Chung 1, D. Lederer 1, A.
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FinFET: a mature multigate MOS technology?A wideband transistor simulation and
characterization approach
J.-P. Raskin1, T.M. Chung1, D. Lederer1, A. Dixit2, N. Collaert2,
T. Rudenko3, V. Kilchytska3, D. Flandre3
Université catholique de Louvain,1Microwave and 4Microelectronics Laboratories
• Strong limitations - Short Channel Effects - appearing for Single Gate MOS below 50 nm
• Many technological difficulties to satisfy the ITRS predictions, in terms of leakage current (IOFF), supply voltage, Early voltage, DIBL, cutoff frequency, etc.
• Multiple-gate MOSFETs (MuG) are considered as serious potential candidates
Higher parasitic capacitances: TG > DG > SG due to more complex 3-D interconnection Main part of the parasitic capacitance is related to fringing field between
FinFET: very promising technological solution at short term
Advantages: - higher technological maturity than planar DG- parasitic capacitances related to the 3-D FinFET structure are only slightly higher than for SG
Disadvantages: - reduced mobility for electrons (<110> cristalline orientation)- control of Wfin by etching + gate interface quality
- higher source/drain resistances
Conclusions – Maturity of FinFETs?
Rs, Rd → reduced gm → lower fT and fmax
Rg → reduced fmax
Short term technological challenges: gate interface quality, silicidation S/D orLow Schottky Barrier S/D contacts, integration density