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Abstract— FinFETs have been made successfully for massmanufacturing on bulk and silicon-on-insulator wafers. Whenchoosing the bulk option, additional process steps are needed forsubstrate leakage suppression. Typically, heavy substrate dopingfor punchthrough stopping between the source and drain isused, but precise control of the doping profile to prevent its up-diffusion into the channel has been a challenging task, especiallyfor continuously shrinking device dimension. In this paper,we propose a stack gate structure with doping-free substratewhile punchthrough leakage can be suppressed. The proposedtechnique can be integrated in conventional gate-last high-kmetal gate process. Both polysilicon and metal gates are shownto be feasible in the proposed stack gate based on 3-D TCADsimulation. In addition, the stack gate structure without substratedoping is immune to its random dopant fluctuations.
Index Terms— Bulk FinFET, stack gate, substrate doping.
I. INTRODUCTION
AMONG emerging technologies, nonplanar transistors
such as double-gate FinFETs and trigate transistors have
stepped further into manufacturing [1], [2]. Because of reduced
short-channel effects in the multigate transistors, Moore’s law
continues to be extended from conventional device scaling
without the need of new substrate material. Typically, non-
planar structures are expected to be fabricated on silicon-on-
insulator (SOI) wafers for perfect isolation from substrate [3].
Alternatively, FinFET technology on bulk silicon wafer hasbeen shown to be feasible for volume production [1] though
requiring additional process steps.
Due to the issue of substrate leakage (similar to
punchthrough) in bulk-Si FinFETs, additional substrate doping
(punchthrough stopping, PTS) and thick isolation oxide (about
twice fin height) as in STI are needed [4]–[7]. However,
substrate doping implantation and thick isolation oxide growth
increase technology complexity, and usually require additional
thermal budget. Furthermore, the upward doping diffusion into
Manuscript received February 28, 2013; revised December 2, 2013 andJanuary 27, 2014; accepted February 10, 2014. Date of publication March 4,2014; date of current version March 20, 2014. This work was supported by theNational Science Council of Taiwan. The review of this paper was arrangedby Editor J. C. S. Woo.
Y.-B. Liao and W.-C. Hsu are with the Institute of Microelectronics, Depart-ment of Electrical Engineering, National Cheng Kung University, Tainan 701,Taiwan.
M.-H. Chiang is with the MS Degree Program on Nano-Integrated-CircuitEngineering, Department of Electrical Engineering, National Cheng KungUniversity, Tainan 701, Taiwan (e-mail: [email protected]).
Y.-S. Lai is with the National Nano Device Laboratories, Hsinchu 300,Taiwan.
Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2014.2306012
Fig. 1. Conventional bulk-Si FinFET structure with (a) 3-D view and (b) 2-Dcross section.
the fin degrades undoped (or lightly doped) channel mobility
and the isolation oxide reduces the effective fin height at a
given aspect ratio (AR). In this paper, we propose an alterna-
tive and yet feasible approach for leakage suppression using
a stack gate structure without the need of additional substrate
doping and excessive oxide growth. We also investigate the
impact of the proposed technique on device performance
and provide an optimal design window using 3-D numerical
simulation.
I I . CONVENTIONAL B UL K-SI F INFE TS
A. Device Structure and Simulation Methodology
The 3-D n-channel bulk-Si FinFET structure and cross
section are shown in Fig. 1(a) and (b), respectively. In our
simulation, the nominal SOI device with undoped (or lightly
doped) channel is based on the 11.9 nm node in ITRS [8] as
follows: L g = 10 nm, W Si = L g /2 = 5 nm, H Si = 12.5 nm
AR = 2.5), fin pitch = 16 nm (1.6 L g), equivalent oxide thick-
964 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 4, APRIL 2014
Fig. 2. Predicted I DS–V GS characteristics with PTS doping in differentdoping depths with inset showing different PTS doping depths extracted fromtheir Gaussian profiles, respectively.
Fig. 3. Electron distribution in bottom channel ( Z = 0) across the fin atV DS = 0.68 V and V GS = 0 V.
diffusion of PTS doping. Our work investigated the leak-
age issue associated with the bulk substrate and assess the
leakage suppression technique via the 3-D TCAD simulation
with Fermi–Dirac statistics, drift-diffusion transport using the
Philips unified mobility model, and the density-gradient quan-
tization model [9].
B. Leakage Current Issue and Suppression Approaches
When the buried oxide in SOI wafer is replaced with
bulk silicon, the leakage current increases due to excessive
carriers underneath the channel in bulk substrate. Previouswork showed that a leakage current suppression approach
in optimizing isolation oxide and PTS doping under the
channel [6]. Excessive carriers and punchthrough current
can be effectively suppressed by PTS doping. Fig. 2 shows
I DS–V GS characteristics with PTS doping in different doping
depths (T doping ≡ distance for the graded S/D doping profile
to distribute from its peak level to 1018 cm−3) with inset
showing different PTS doping depths extracted from their
Gaussian profiles. Leakage current is significantly suppressed
when doping depth is longer than 17 nm. However, threshold
voltage also changes when PTS doping diffuses into channel.
Fig. 4. Predicted I DS–V GS characteristics for SOI and bulk-Si FinFETs.Inset: predicted I OFF versus T ISO.
Fig. 3 shows the electron distribution in bottom channel
across the fin. The highest electron density occurs in the case
without any PTS. The electron density decreases as the PTSdoping depth increases. Fig. 4 shows I DS–V GS characteristics
for SOI and bulk-Si FinFETs with thick isolation oxide with-
out PTS. The predicted I OFF is still too high though it seems
to be limited when isolation oxide is thicker than 30 nm, as
shown in inset. The substrate PTS doping is most effective for
limiting equivalent I OFF to that of SOI. However, PTS requires
complicate and precise control of substrate doping profile
and additional thermal budget such that the universal process
for different applications on a chip could not be used [10].
The deep substrate implementation is usually not practical for
advanced nanometer-scale devices. A simplified and effective
process for leakage current suppression technique is needed.
III. PROPOSED S TACK G ATE T ECHNIQUE
In this section, we propose a stack gate structure with a
bottom layer of polysilicon gate while leaving the substrate
undoped. Such technique is shown to effectively suppress
the excessive carriers and hence reduces leakage current in
substrate.
A. Stack Gate Structure and Conceptual Process
Based on the previous discussion, the excessive carriers
underneath the channel in the substrate are the main source
causing the leakage current. If we can find some way to
reduce the electron density underneath the channel, I OFF is thengreatly lowered. To achieve this, two types or gate material
are adopted in a stack structure [Fig. 5(f)]. The additional
bottom gate can be made of p-type polysilicon (or equivalent
metal gate) for nFETs with finite T BG. Using this structure, the
substrate region close to the fin can be in a near-accumulation
condition simply by adjusting gate work function.
Based on high-k metal-gate process (HKMG) [1], [11], the
stack gate process is compatible with gate-last approach
(Fig. 5). In etching process for silicon fins, requirements of
actual fin height ( H Si), isolation oxide (T ISO), and bottom gate
thickness (T BG) must be considered as they are all related in
LIAO et al.: STACK GATE TECHNIQUE FOR DOPINGLESS BULK FinFETs 965
Fig. 5. Conceptual process flow of the stack gate bulk FinFET.
Fig. 6. Predicted I DS–V GS characteristics with different T BG’s at(a) V DS = V DD and (b) V DS = 50 mV. Inset: electron distribution withstack gate structure.
technology. Following the fin formation, isolation oxide and
dummy poly-Si gate are formed and patterned. After S/D for-
mation, the dummy poly-Si gate should be removed. To avoid
potential damage on the high-k dielectric, one shall use high-
k last process (as used in gate-last HKMG process) such that
the high-k dielectric is formed after removal of dummy poly-Sigate. Finally, dual-metal gate is formed, resulting in two layers
of gate. An interfacial cap layer [12], [13] could be employed
after high-k dielectric deposition to prevent the damage during
the etch back step.
B. Stack Gate With Polysilicon Gate
Using our proposed stack gate (or gate engineering) with
thick isolation oxide (T ISO = 30 nm), Fig. 6(a) and (b) show
I DS–V GS characteristics with different T BG’s, as compared
with conventional bulk-Si and SOI counterparts. The stack gate
is advantageous in leakage current suppression because the
Fig. 7. Leakage current versus bottom gate thickness (T BG) in differentisolation oxides (T ISO) with labeled SOI for reference.
968 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 4, APRIL 2014
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Yi-Bo Liao (S’12) received the B.S. and M.S.degrees in electronics engineering from the NationalIlan University, I-Lan, Taiwan, in 2006 and 2008,respectively. He is currently pursuing the Ph.D.degree with the Department of Electrical Engineer-ing, Institute of Microelectronics, National ChengKung University, Tainan, Taiwan.
Meng-Hsueh Chiang (S’97–M’01–SM’07)received the B.S. degree in electrical engineeringfrom the National Cheng Kung University, Tainan,Taiwan, and the M.S. and Ph.D. degrees in electricaland computer engineering from the University of Florida, Gainesville, FL, USA, in 1992, 1995, and2001, respectively.
He is a Faculty Member with the Departmentof Electrical Engineering, National Cheng KungUniversity.
Yu-Sheng Lai received the B.S. degree in electricalengineering from Fun Chia University, Taichung,Taiwan, and the M.S. and Ph.D. degrees from theInstitute of Electronics Engineering, National TsingHua University, Hsinchu, Taiwan, in 1995, 1997, and2007, respectively.
He is with the National Nano Device Laboratories,National Applied Research Laboratories, Hsinchu.
Wei-Chou Hsu (M’87) received the Ph.D. degreefrom the National Cheng Kung University, Tainan,Taiwan.
He is with the Department of Electrical Engi-neering, Institute of Microelectronics, AdvancedOptoelectronic Technology Center, and the Collegeof Electrical Engineering and Computer Science,National Cheng Kung University.