Final od college

Presented By:Rajeev Kumar MishraRajeev Kumar Mishra

M.Tech Part-II (Communication Systems) M.Tech Part-II (Communication Systems) 10305EN06910305EN069

External Supervisor Internal SupervisorMr. Akhilesh Chandra Mishra Mr. Amritanshu PandeyMr. Akhilesh Chandra Mishra Mr. Amritanshu Pandey

Senior Manager(TRnD, IOS Grp) Assistant ProfessorSenior Manager(TRnD, IOS Grp) Assistant Professor

ST Microelectronics IT-BHUST Microelectronics IT-BHU

Greater Noida (U.P) Varanasi (U.P)Greater Noida (U.P) Varanasi (U.P)

Department of Electronics Engineering

Institute of Technology BHU (IT-BHU), Varanasi

Overview of NBTI. Mechanism involved in NBTI (Reaction Diffusion Model). Effect on Various Technologies. Scaling Impact on NBTI. Temperature impact on NBTI. Possible impacts on Circuits. Concept of NBTI Stress. NBTI minimization. Age Analysis of a Buffer Comparison of Results for 45nm and 28nm Technologies.

Analysis & Simulation of NBTI Effects in Various Technologies IT BHU Varanasi2

Study of Negative Bias Temperature Instability (NBTI) and its impact on Circuit.

Temperature, Scaling and frequency impact on NBTI. Familiarity with the circuit simulation tools like ELDO, ALTO Familiarity with Input Output Library (I/O’s). Characterization of a Input Output cell (Bidirectional Buffer). (Finding the delay of a buffer, between IO and Core Side). Stress (Reliability) Analysis of a simple buffer and CMOS inverter. Stress (Reliability) Analysis across the 45nm & 28nm technologies. Finding worst operating conditions of NBTI for any technology.

3Analysis & Simulation of NBTI Effects in Various Technologies IT BHU Varanasi

• NBTI – Negative Bias Temperature Instability.• PMOS parameters degradation in presence of holes close to the

interface(Si/Si02) at high temperature (>80˚C).

• NBTI is in general attributed to reaction-diffusion (R-D) model involving interfacial bond breaking(Si-H) followed by a diffusion process of hydrogen species.

Vdd

G

S

0

-Vdd

Stress StressRelaxation

VG = 0 VG = Vdd

June 15, 2012 4


RD (Reaction Diffusion) model explains physics of NBTI degradation in terms of different sub-processes.

Hole Tunneling Hole Capture Dissociation.

NBTI degradation originates from Silicon Hydrogen bonds (Si-H) breaking at Silicon-Silicon dioxide (Si-SiO2) interface during negative stress (Vgs=-Vdd).

The broken Silicon bonds (Si-) Dangling Silicon, act as interface traps that are responsible for higher Vth and lower drain current.

The number of interface traps (Nit) depends on Si-H bond breaking rate (kf) and Si- bond recovery rate (kr).

June 15, 2012 5


6

Dangling Si- trivalent silicon atoms with one unpaired valence electronSi3 Si•, or Si2O Si• ,≡ ≡

Mostly Temp. driven

Mostly Field driven

Where is strongly Temp. Dependent


Fig. 2

Relation between Threshold Voltage and Interface trapped charges

Where Qf is the fixed charge density and Qit is interface trap density.

The MOS drain current (sat) and transconductance is related with threshold voltage as,

June 15, 2012 7

Where is given by (modified by carrier velocity saturation effect)


,/2 OXBFFBT CQVV −−= φ

OX

Sit

OX

FMSFB C

Q

C

QV

)(φφ −−=

( ) ( )( ) ( ).2

22

TGOXeffm

TGOXeffD

VVCLWg

VVCLWI

−=

−=

µ

µ

C

DS

PP

C

DS

nn

LE

V

LE

V−

=+

=11

00 µµµµeffµ

Ì Non Recoverable NBTI (Permanent) It is due to the interface traps generation. The electric field is able to break Si-H bonds located at the Silicon-

oxide interface.Recoverable NBTI (Temporary) It is due to some pre-existing traps present in the gate oxide. The pre-existing traps get filled with holes coming from the

channel of PMOS. These traps can be emptied when the stress voltage is removed.

June 15, 2012


Fig. 3

Interface Traps:Interface Traps:

It is due to the Si-Si02 interface properties anddependent on the chemical composition of thisInterface. The interface trap density is crystal orientation

dependent. Can be +ve or –ve depend on type of substrate.(n-Type or p-Type substrate).

Oxide Charges:Oxide Charges:

the fixed-oxide charge is located within approximately 3 nm of the SiO2-Si interface .this charge is fixed and cannot be charged or discharged over a wide variation of surface potential.Generally, Qf is positive and dependson oxidation and annealing conditions and on siliconOrientation.

June 15, 2012 9


Fig. 4

As technology shrinks the Vth shift become worse (E.g., the Vth shift for 90nm is 34% while this rises with about 4% for each new technology

generation (i.e., 38% for 65nm and 42% for 45nm) ). The NIT growth under given conditions results from Eox increment with

technology scaling. Temperature increment moderately reduces the drain current, and this

reduction becomes more severe with technology scaling. E.g., the current

reduction is about 5% for 90nm while this is 8% for 45nm.

June 15, 2012 10

10

Ref: Temperature Impact on NBTI Modeling in the Framework of Technology Scaling

Analysis & Simulation of NBTI Effects in Various Technologies IT BHU Varanasi

Fig. 5

The PMOS negative gate stress breaks Si-H bonds at Si-SiO2 interface resulting in Si- broken bonds and H atoms by the reaction:

Most of the H atoms released converted to H2 molecules

Where, kH is the rate constant of H to H2 conversion. The temperature impact on conversion can be understood by inspecting the rate constant kH, as:For atomic Hydrogen diffusion the parameter is equal to 10^-4 at higher temperature the Si-H bonds vibrate that bring H atoms and Si-H at rH < 1.0nm,

and hence accelerate kH sub process. The diffusion variation with temperature increment from Tref , to T(t) is given by diffusion

ratio:

NOTE: The equation shows that the temperature increment accelerate DH. The DH acceleration towards gate attenuate the Si- broken bond recovery sub-process at Si-SiO2 interface and hence increases the NIT.


Propagation delays - increaseRise/fall time - changeDuty cycle of signals - changeSetup and hold times for latch/flip-flop - changeCurrent consumption - decreaseLeakage - changeSwitching threshold - changeDrive currents - decreaseOperating points in an analog circuit – change

June 15, 2012 12


ˆ Stress: Extent of damage each transistor suffers depends on the bias conditions applied on this specific transistor and the time duration through which this bias was applied.

a For every cycle Accumulated Stress is calculated by Where Ttransient = Tstop-Tstart

NBTI Stress is given by (as a function of Vgs) : where H=Tech parameter and m=model parameter

The incremental change in the parameter is given by,

P = P0 (1 + dP)

Where dP(dVth) for NBTI follows power law pattern given by, NBTI_S = NBTI Stress Integral A=degradation constant, n=degradation rate, T= Temp Ea=Thermal activation energy, K= Boltzmann constant

Then the new value of Vth after some stress time is,

Vth=Vth0(1+dP_NBTI) June 15, 2012 13


transient

iiT

TegralStressStressStress ×+= int_

( ) HtVgsmtStressNBTI )()(_ =

0

0

P

PPdP

−=

Where P is the parameter value at time t, and P0 is the parameter value extracted at t=0s.

××= KT

E

na

eSNBTIANBTIdP __

Characterization

Functional Timing

Selection of Opoint Selection of corner

e.g. ff32_1.15V_1.95V_125C

e.g. ff32_1.15V_1.95V_125C_2ey

Generation of Stress file(reliability.lib)

Inclusion of Stress file(for NBTI Delay Cal.)

Delay Calculation

Mapping to various corners

NBTI (_2eY) NON NBTI


Device Definition

Source Definition

Age Analysis


NBTI STRESS


17

18

Output at t=27’C Output at t=125’C

At T=27’C V(OUT)_1 is 1.17359V and V(OUT)_2 is 1.11157

At T=125’C V(OUT)_1 is 1.07925V and V(OUT)_2 is 0.94825V.

At room temperature the degradation of output is about 5% which is increased to about 11% at a temperature of 125’C

Analysis & Simulation of NBTI Effects in Various Technologies IT BHU Varanasi 19

Delay in ns

OPOINT - PssaV1260V1320T125Y2_OP

PffaV1260V1320Tm40

Cload=2pf, slope=0.8

ARCS NON NBTI NBTI % Change

A_R_IO_R_1 1.2988 1.3066 0.60055

A_R_IO_R_0 1.1047 1.1071 0.21725

A_F_IO_F_0 1.0754 1.0721 0.306863

A_F_IO_F_1 1.2024 1.2049 0.20792

IO_R_ZI_R_0 0.24327 0.24557 0.9562

IO_R_ZI_R_1 0.35978 0.36386 1.134

IO_F_ZI_F_1 0.40162 0.40778 1.53379

IO_F_ZI_F_0 0.35215 0.35669 1.28922

20

Non-NBTI / NBTI delay change : max on IO_F_ZI_F (1.2% to 1.5%)A to IO (0.2% to 0.6%)

A, ZI : CORE Side Signal

IO : IO Side Signal

Delay in nsOPOINT - PssaV1260V1320T125Y2_OP

PffaV1150V1950T125Cload=2pf, slope=0.8

ARCS NON NBTI NBTI % Change

IO_R_ZI_R_0 1.5938 1.5981 0.2698

IO_F_ZI_F_0 1.39 1.4118 1.56835

A_R_IO_R_01 6.707 6.7535 0.69331

A_F_IO_F_01 7.0584 7.0826 0.34285

A_R_IO_R_00 4.6319 4.661 0.62825

A_F_IO_F_00 4.7386 4.7596 0.44317

A_F_IO_F_10 5.7391 5.7659 0.46697

A_R_IO_R_10 5.7225 5.759 0.63783

A_F_IO_F_11 7.8279 7.8568 0.36919

A_R_IO_R_11 7.5926 7.6473 0.72044

21

A, ZI : CORE Side Signal

IO : IO Side Signal

Non-NBTI / NBTI delay change : max on IO_F_ZI_F (1.56%)A to IO (0.34% to 0.72%)

Delay of ss28_1.00V_1.65V_125C considering stress of various corners(nS)

ss28_1.00V_1.65V_125C

ARC With Same Stress

With Stress of ss28_0.85V_1.95V_125

C


C


C


C_2eY

With Stress of

ss28_0.85V_1.65V_m4

0C

IO_R_ZI_R_0 1.3303 1.3414 1.3288 1.3421 1.3447 1.327

IO_F_ZI_F_0 3.3462 3.3671 3.346 3.3673 3.3683 3.3348

A_R_IO_R_01 9.2288 9.2702 9.2243 9.2735 9.2816 9.1844

A_F_IO_F_01 7.34 7.357 7.3374 7.3597 7.3708 7.3239

A_R_IO_R_00 6.7376 6.7648 6.7381 6.7654 6.7786 6.719

A_F_IO_F_00 5.5845 5.5992 5.5811 5.6018 5.613 5.5677

A_F_IO_F_10 7.1011 7.1255 7.0978 7.1282 7.1393 7.0791

A_R_IO_R_10 8.5146 8.5521 8.5124 8.5526 8.5632 8.4907

A_F_IO_F_11 8.5125 8.5367 8.5087 8.5394 8.551 8.4915

A_R_IO_R_11 10.514 10.563 10.511 10.567 10.576 10.479

22

As can be seen from the above figures that in this case worst corner is ss28_1.15V_1.95V_125C_2eY i.e. the worst corner should be having maximum GO1 voltage, maximum GO2 voltage, Maximum temperature(125’C in this case) and the maximum stress duration (2 years in this case).

The absolute delay of the Driver side (i.e. A to IO, Core to IO Side) is more as compared to the receiver side signals (i.e. IO to ZI).

The impact of process (Slow or Fast) and temperature is much significant for NBTI delay as can be seen from the results. For the corners in which the Slow process and temperature of 125’C is used they are much degraded due to NBTI as compared to Fast process and a temperature of -40 ‘C.

For the most of the cases the worst corner (PVT) should be one having maximum GO1 voltage, maximum GO2 voltage, Maximum temperature (125’C in this case) and the maximum stress duration.

23Analysis & Simulation of NBTI Effects in Various Technologies IIT BHU Varanasi

Based on the simulation results with an industrial 45nm technology, it is observed that the degradation of threshold voltage due to NBTI can be as high as 9% for a stress period of two years.

As far as temperature variation is concerned, at room temperature the degradation of output is about 5% which is increased to about 11% at a temperature of 125’C.So Lower temperature is also desirable for robust nanoscale design.

The transistor reliability will be a severe problem in future technology nodes which makes the device life time shorter than predicted.

That ‘s why new technology nodes (from 22nm onwards) are using FDSOI technique to reduce NBTI.

Analysis & Simulation of NBTI Effects in Various Technologies IIT BHU Varanasi 24

Over time, NBTI degrade device currents and will cause

failures in integrated circuits. Circuit designers need to

consider these reliability effects in the early stages of design to

make sure there are enough margins for circuits to function

correctly over their entire lifetime. As technology is shrinking

the scope will increase for stress analysis, as this is a major

challenge for designers to overcome.

25

Seyab, Said Hamdioui (Delft University of Technology) “Temperature Impact on NBTI Modeling in the Framework of Technology Scaling”.

Chittoor Parthasarathy(ST), Philippe Raynaud(Mentor Graphics) “Reliability simulation in CMOS design using Eldo”.

http://www.iue.tuwien.ac.at/phd/wittmann/node10.html “NBTI Reliability Analysis”.

Rakesh Vattikonda, Wenping Wang, Yu Cao “Modeling and Minimization of PMOS NBTI Effect for Robust Nanometer Design”.

M.A. Alam, S. Mahapatra “A comprehensive model of PMOS NBTI degradation” (online @ www.sciencedirect.com).

R. Wittmann, H. Puchner, A. Gehring, and S. Selberherr “Impact of NBTI-Driven Parameter Degradation on Lifetime of a 90nm p-MOSFET”.

Robert Entner (Dissertation) “Modeling and Simulation of Negative Bias Temperature Instability”.

Sanjay Kumar, Chris Kim, Sachin Sapatnekar University of Minnesota “An Analytical Model for Negative Bias Temperature Instability (NBTI)”.

26Analysis & Simulation of NBTI Effects in Various Technologies IIT BHU Varanasi

http://www.iue.tuwien.ac.at/phd/wittmann/node10.html

http://www.sciencedirect.com/

Rajeev Kumar Mishra, S.Alam, Amritanshu Pandey “Analysis and

impacts of Negative Bias Temperature Instability (NBTI)” ,

IEEE Xplore Digital Library, SCEECS IEEE Conference, March

2012, MANIT Bhopal.

(link: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6184739)

27

http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6184739

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