Fall 2006, Sep. 26, Fall 2006, Sep. 26, Oct. 3 Oct. 3 ELEC 5270-001/6270-001 Lect ELEC 5270-001/6270-001 Lect ure 7 ure 7 1 ELEC 5270-001/6270-001(Fall ELEC 5270-001/6270-001(Fall 2006) 2006) Low-Power Design of Electronic Circuits Low-Power Design of Electronic Circuits Dynamic Power: Glitch Elimination Dynamic Power: Glitch Elimination Vishwani D. Agrawal Vishwani D. Agrawal James J. Danaher Professor James J. Danaher Professor Department of Electrical and Computer Department of Electrical and Computer Engineering Engineering Auburn University, Auburn, AL 36849 Auburn University, Auburn, AL 36849 http://www.eng.auburn.edu/~vagrawal http://www.eng.auburn.edu/~vagrawal [email protected][email protected]
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Theorem 1Theorem 1 For correct operation with For correct operation with
minimum energy consumption, a minimum energy consumption, a Boolean gate must produce no Boolean gate must produce no more than more than oneone event per transition. event per transition.
Output logic state changesOne transition is necessary
Output logic state unchangedNo transition is necessary
Given that events occur at the input of a gate with Given that events occur at the input of a gate with inertial delay inertial delay dd at times, at times, tt11 ≤ . . . ≤ ≤ . . . ≤ ttnn , the number , the number of events at the gate output cannot exceedof events at the gate output cannot exceed
Balanced Delay MethodBalanced Delay Method All input events arrive simultaneouslyAll input events arrive simultaneously Overall circuit delay not increasedOverall circuit delay not increased Delay buffers may have to be insertedDelay buffers may have to be inserted
Variables: gate and buffer delaysVariables: gate and buffer delays Objective: minimize number of buffersObjective: minimize number of buffers Subject to: overall circuit delay Subject to: overall circuit delay
constraint for all input-output pathsconstraint for all input-output paths Subject to: minimum transient Subject to: minimum transient
condition for all multi-input gatescondition for all multi-input gates
Objective FunctionObjective Function Ideal: minimize the number of non-zero Ideal: minimize the number of non-zero
delay buffers (non-linear ILP):delay buffers (non-linear ILP): Delay of ith buffer = Delay of ith buffer = xxi i ddi i , , where where xxi i = [0, 1]= [0, 1]
Minimize Minimize ΣΣ xxi i buffersbuffers
An approximated LP:An approximated LP: Delay of ith buffer = Delay of ith buffer = ddii
Sum of delays on critical path ≤ Sum of delays on critical path ≤ maxdelmaxdel maxdel = specified critical path delaymaxdel = specified critical path delay
ReferencesReferences E. Jacobs and M. Berkelaar, “Using Gate Sizing to Reduce E. Jacobs and M. Berkelaar, “Using Gate Sizing to Reduce
Glitch Power,” Glitch Power,” Proc. ProRISC/IEEE Workshop on Circuits, Proc. ProRISC/IEEE Workshop on Circuits, Systems and Signal ProcessingSystems and Signal Processing, Nov. 1996, pp. 183-188; , Nov. 1996, pp. 183-188; also also Int. Workshop on Logic SynthesisInt. Workshop on Logic Synthesis, May 1997., May 1997.
V. D. Agrawal, “Low-Power Design by Hazard Filtering,” V. D. Agrawal, “Low-Power Design by Hazard Filtering,” Proc. 10th Int. Conf. VLSI DesignProc. 10th Int. Conf. VLSI Design, Jan. 1997, pp. 193-197., Jan. 1997, pp. 193-197.
V. D. Agrawal, M. L. Bushnell, G. Parthasarathy, and R. V. D. Agrawal, M. L. Bushnell, G. Parthasarathy, and R. Ramadoss, “Digital Circuit Design for Minimum Transient Ramadoss, “Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method,” Energy and a Linear Programming Method,” Proc. 12th Proc. 12th Int. Conf. VLSI DesignInt. Conf. VLSI Design, Jan. 1999, pp. 434-439., Jan. 1999, pp. 434-439.
Last two papers are available at website Last two papers are available at website http://www.eng.auburn.edu/~vagrawalhttp://www.eng.auburn.edu/~vagrawal
Constraints are written by Constraints are written by path path
enumeration.enumeration. Since number of paths in a circuit can be Since number of paths in a circuit can be
exponential in circuit size, the exponential in circuit size, the
formulation is infeasible for large circuits.formulation is infeasible for large circuits. Example: c880 has 6.96M constraints.Example: c880 has 6.96M constraints.
Estimation of PowerEstimation of Power Circuit is simulated by an event-Circuit is simulated by an event-
driven simulator for both optimized driven simulator for both optimized and un-optimized gate delays.and un-optimized gate delays.
All transitions at a gate are counted All transitions at a gate are counted as Events[gate].as Events[gate].
Power consumed Power consumed Events[gate] x Events[gate] x # of fanouts.# of fanouts.
Ref: “Effects of delay model on peak Ref: “Effects of delay model on peak power estimation of VLSI circuits,” power estimation of VLSI circuits,” Hsiao, Hsiao, et alet al. (. (ICCAD`97 ICCAD`97 ).).
ReferencesReferences R. Fourer, D. M. Gay and B. W. Kernighan, R. Fourer, D. M. Gay and B. W. Kernighan, AMPL: A Modeling AMPL: A Modeling
Language for Mathematical ProgrammingLanguage for Mathematical Programming, South San Francisco: The , South San Francisco: The Scientific Press, 1993.Scientific Press, 1993.
M. Berkelaar and E. Jacobs, “Using Gate Sizing to Reduce Glitch M. Berkelaar and E. Jacobs, “Using Gate Sizing to Reduce Glitch Power,” Power,” Proc. ProRISC WorkshopProc. ProRISC Workshop, Mierlo, The Netherlands, Nov. , Mierlo, The Netherlands, Nov. 1996, pp. 183-188.1996, pp. 183-188.
V. D. Agrawal, “Low Power Design by Hazard Filtering,” V. D. Agrawal, “Low Power Design by Hazard Filtering,” Proc. 10Proc. 10thth Int’l Conf. VLSI DesignInt’l Conf. VLSI Design, Jan. 1997, pp. 193-197., Jan. 1997, pp. 193-197.
V. D. Agrawal, M. L. Bushnell, G. Parthasarathy and R. Ramadoss, V. D. Agrawal, M. L. Bushnell, G. Parthasarathy and R. Ramadoss, “Digital Circuit Design for Minimum Transient Energy and Linear “Digital Circuit Design for Minimum Transient Energy and Linear Programming Method,” Programming Method,” Proc. 12Proc. 12thth Int’l Conf. VLSI Design Int’l Conf. VLSI Design, Jan. 1999, , Jan. 1999, pp. 434-439.pp. 434-439.
M. Hsiao, E. M. Rudnick and J. H. Patel, “Effects of Delay Model in M. Hsiao, E. M. Rudnick and J. H. Patel, “Effects of Delay Model in Peak Power Estimation of VLSI Circuits,” Proc. ICCAD, Nov. 1997, pp. Peak Power Estimation of VLSI Circuits,” Proc. ICCAD, Nov. 1997, pp. 45-51.45-51.
T. Raja, T. Raja, A Reduced Constraint Set Linear Program for Low Power A Reduced Constraint Set Linear Program for Low Power Design of Digital CircuitsDesign of Digital Circuits, Master’s Thesis, Rutgers Univ., New , Master’s Thesis, Rutgers Univ., New Jersey, 2002.Jersey, 2002.
ConclusionConclusion Glitch-free design through LP: constraint-set is linear in the size of Glitch-free design through LP: constraint-set is linear in the size of
the circuit.the circuit.
LP solution:LP solution:
Eliminates glitches at all gate outputs,Eliminates glitches at all gate outputs,
Holds I/O delay within specification, andHolds I/O delay within specification, and
Combines path-balancing and hazard-filtering to minimize the Combines path-balancing and hazard-filtering to minimize the
number of delay buffers.number of delay buffers.
Linear constraint set LP produces results exactly identical to the LP Linear constraint set LP produces results exactly identical to the LP