Copyright Agrawal, 2011 Copyright Agrawal, 2011 ELEC5270/6270 Spr 15, Lecture 7 ELEC5270/6270 Spr 15, Lecture 7 1 ELEC 5270/6270 Spring 2015 ELEC 5270/6270 Spring 2015 Low-Power Design of Electronic Low-Power Design of Electronic Circuits Circuits Energy Source Design Energy Source Design Vishwani D. Agrawal Vishwani D. Agrawal James J. Danaher Professor James J. Danaher Professor Dept. of Electrical and Computer Engineering Dept. of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 Auburn University, Auburn, AL 36849 [email protected]http://www.eng.auburn.edu/~vagrawal/COURSE/E6270_Spr15/course.html
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Copyright Agrawal, 2011ELEC5270/6270 Spr 15, Lecture 71 ELEC 5270/6270 Spring 2015 Low-Power Design of Electronic Circuits Energy Source Design Vishwani.
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ELEC 5270/6270 Spring 2015ELEC 5270/6270 Spring 2015Low-Power Design of Electronic CircuitsLow-Power Design of Electronic Circuits
Energy Source DesignEnergy Source Design
Vishwani D. AgrawalVishwani D. AgrawalJames J. Danaher ProfessorJames J. Danaher Professor
Dept. of Electrical and Computer EngineeringDept. of Electrical and Computer EngineeringAuburn University, Auburn, AL 36849Auburn University, Auburn, AL 36849
OutlineOutline Energy source optimization methodsEnergy source optimization methods
Voltage and Clock Management Voltage and Clock Management Functional ManagementFunctional Management
Voltage and Clock Management (DVFS)Voltage and Clock Management (DVFS) BackgroundBackground
A typical system powered with batteryA typical system powered with battery Battery Simulation ModelBattery Simulation Model DC to DC converterDC to DC converter
Problem statementProblem statement Case I : System is Performance boundCase I : System is Performance bound Case II : A higher battery lifetime is requiredCase II : A higher battery lifetime is required Case III : Battery weight or size is constrainedCase III : Battery weight or size is constrained
Battery Simulation ModelBattery Simulation ModelLithium-ion battery, unit cell capacity: N = 1 (400mAHr)Battery sizes, N = 2 (800mAHr), N = 3 (1.2AHr), etc.
Ref: M. Chen and G. A. Rincón-Mora, “Accurate Electrical Battery Model Capable of Predicting Runtime and I-V Performance,” IEEE Transactions on Energy Conversion, vol. 21, no. 2, pp. 504–511, June 2006.
RRSeriesSeries = 0.07446 + 0.1562 e = 0.07446 + 0.1562 e – – 24.3724.37××SOCSOC Other resistance and capacitance are also Other resistance and capacitance are also
non-linear functions of SOC and represent non-linear functions of SOC and represent short-term (S) and long-term (L) transient short-term (S) and long-term (L) transient effects.effects.
A meaningful measure of the work done by the battery is its lifetime in terms of clock cycles.
For each VDD in the range of valid operation, i.e., VDD = 0.1V to 1.0V, calculate lifetime using circuit delay and battery efficiency obtained from HSPICE simulation.
Minimum energy operation maximizes the lifetime in clock cycles.
1. Battery size should match the current need and satisfythe lifetime requirement of the system:(a) Undersize battery has poor efficiency.(b) Oversize battery is bulky and expensive.
2 Minimum energy mode can significantly increase battery lifetime.
ReferencesReferences1. M. Pedram and Q. Wu, “Design Considerations for Battery-Powered
Electronics,” Proc. 36th Design Automation Conference, June 1999, pp. 861– 866.
2. L. Benini, G. Castelli, A. Macii, E. Macii, M. Poncino, and R. Scarsi, “A Discrete-Time Battery Model for High-Level Power Estimation,” Proc. Conference on Design, Automation and Test in Europe, Mar. 2000, pp. 35 – 41.
3. M. Chen and G. A. Rincón-Mora, “Accurate Electrical Battery Model Capable of Predicting Runtime and I-V Performance,” IEEE Transactions on Energy Conversion, vol. 21, no. 2, pp. 504 – 511, June 2006.
6. M. Kulkarni and V. D. Agrawal, “Matching Power Source to Electronic System: A Tutorial on Battery Simulation”, Proc. VLSI Design and Test Symposium, July 2010.
7. M. Kulkarni and V. D. Agrawal, “Energy Source Lifetime Optimization Energy Source Lifetime Optimization for a Digital System through Power Management,” for a Digital System through Power Management,” Proc. Proc. IEEE Proc. Proc. IEEE International Conf. Industrial Technology and 43rd IEEE Southeastern International Conf. Industrial Technology and 43rd IEEE Southeastern Symp. System TheorySymp. System Theory, March 2011., March 2011.
8. M. Kulkarni, S. Sheth and V. D. Agrawal, “Architectural Power Architectural Power Management for High Leakage Technologies,” Management for High Leakage Technologies,” Proc. Proc. IEEE Proc. Proc. IEEE International Conf. Industrial Technology and 43rd IEEE Southeastern International Conf. Industrial Technology and 43rd IEEE Southeastern Symp. System TheorySymp. System Theory, March 2011., March 2011.
9. M. Kulkarni, “Energy Source Lifetime Optimization for a Digital System Energy Source Lifetime Optimization for a Digital System through Power Management,” through Power Management,” Master’s ThesisMaster’s Thesis, ECE Dept., Auburn , ECE Dept., Auburn University, December 2010.University, December 2010.
10.10. K. Sheth, “A Hardware-Software Processor Architecture using Pipeline K. Sheth, “A Hardware-Software Processor Architecture using Pipeline Stalls for Leakage Power Management,” Stalls for Leakage Power Management,” Master’s ThesisMaster’s Thesis, ECE Dept., , ECE Dept., Auburn University, December 2008.Auburn University, December 2008.