Fall 2006 1 EE 333 Lillevik 333f06-l13 University of Portland School of Engineering Computer Organization Lecture 13 Controller implementations Register.

Fall 2006

Lillevik 333f06-l13 1University of Portland School of Engineering

EE 333

Computer OrganizationLecture 13

Controller implementationsRegister file designMDP16 overview

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Controller and datapath

InputsIR(31:25)

Outputs

Outputs

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Full FSM state diagram

Inputs:Op

Outputs: 13 signals

States: 10

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FSM architecture

Present

State

NS

Decoder

Output

Decoder

Inputs Outputs

Combo logic

ROM

MUX

Combo logic

ROM

MUX

Decoder

Flip Flops

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FSM controllerState register (D-

type FF) holds present state (PS)

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PLA implementationState (PS) bits and

Op determine outputs and next state

Alternately, use a ROM

IN

OUT

NS

PS

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Project 4: Register File

• Two, 16-bit registers ($0, $1)

• Two read ports

• One write port

• Equal output

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InputsInput Function

Reset Forces the output to all zeros.

CLK Synchronous clock for entire MDP16 design.

Din Port with 16-bit number to load into register file.

REGrd Defines read port contents00 R1 = $0, R0 = $001 R1 = $0, R0 = $110 R1 = $1, R0 = $011 R1 = $1, R0 = $1

REGwr Defines destination register for writes00 Disable write port01 Write to register $010 Write to register $111 Write to register $1, $0 (both registers)

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Outputs

Output Function

R0out Read port zero (R0), 16-bits

R1out Read port one (R1), 16-bits

EQ Status bit that indicates R0 and R1 contain identical numbers

$0 Register $0 output for debugging, 16-bits

$1 Register $1 output for debugging, 16-bits

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Register design

Read portsWrite port

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MDP16 overview

• Architecture similar to MIPS

• Sixteen-bit machine

• Two registers: $0, $1

• Word addressing (0x0000 – 0xffff)

• Memory: 0xffff = 216 = 65,536 words

• Formats: R, I, J-types

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MDP16 schematic

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MDP16 schematic

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Instruction format

op adr

0111215

op rs rt adr/imm1215 11 10 9 0

I

J

R op rs rt funcrd

1215 11 10 9 03

08 4

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Basic questions

• Why do we have just two registers?

• What is the most positive and negative address offset?

• What is the range of the jump address?

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InstructionsName Op Format Func Example Meaningadd

sub

addi

subi

and

or

andi

ori

sll

srl

1

1

A

B

1

1

C

D

2

3

R

R

I

I

R

R

I

I

I

I

0

1

na

na

2

3

na

na

na

na

add $0, $0, $1

sub $0, $0, $1

addi $0, $1, 20

subi $0, $1, 20

and $0, $0, $1

or $0, $0, $1

andi $0, $1, 1f

ori $0, $1, 1f

sll $0, $1

srl $0, $1

$0 = $0 + $1

$0 = $0 - $1

$0 = $1 + 20

$0 = $1 - 20

$0 = $0 & $1

$0 = $0 || $1

$0 = $1 & 1f

$0 = $1 || 1f

$0 = $1 << 1 bit

$0 = $1 >> 1 bit

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Instructions, continued.

Name Op Format Example Meaningnop

lw

sw

beq

j

resv

resv

0

4

5

6

7

8,9

E,F

J

I

I

I

J

NA

NA

nop

lw $0, c3 ($1)

sw $0, c3 ($1)

beq $0, $1, 2a

j 23

NA

NA

No operation

$0 = mem [$1 + c3]

mem [$1 + c3] = $0

If ($0 == $1) go to (PC + 1) + 2a

PC = PC [15- 12] || 23

NA

NA

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Find machine instruction?Instruction Type Op rs rt rd immed

/adrfunct Machine

(hex)add $0, $0, $1 r 0001 0 1 0 na 0000 0x1400

andi $0, $1, 10f I 1100 0 1 10f 0xc50f

sll $0, $1 i 0010 0 1 0x2400

lw $0, 323 ($1) I 0100 1 0 143ten 0x4a11

beq $0, $1, 17a

j a64

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MDP16 programming

• We do not have an assembler– Must “hand” assemble– Limited to small programs– Senior design project anyone?

• Assume the MIPS syntax, addressing, directives, labels

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Simple program

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Assemble the simple program?

Address Machine Instruction

Assembly Instruction

Comment

000 0x1001 sub $0, $0, $0 # $0 = 0

001 0x1e01 sub $1, $1, $1 # $1 = 0

002 0xa002 addi $0,$0,0x2 # $0 = 2

003 addi $1,$1,0x3 # $1 = 3

004 add $0,$0,$1 # $0 = 5

All numbers in hex

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Basic questions

• Why do we have just two registers?Need only one bit to define

• What is the most positive and negative address offset?

• What is the range of the jump address?0x000 to 0xfff = 0000 to 4095

511)12( 9

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Find machine instruction?Instruction Type Op rs rt rd immed

/adrfunct Machine

(hex)add $0, $0, $1 R 0x1 0 1 0 na 0x0 0x1400

andi $0, $1, 10f I 0xc 1 0 na 0x10f na 0xa90f

sll $0, $1 I 0x2 1 0 na na na 0x2400

lw $0, 323 ($1) I 0x4 1 0 na 0x323 na 0x4b23

beq $0, $1, 17a I 0x6 1 0 na 0x17a na 0x657a

j a64 J 0x7 na na na 0xa64 na 0x7a64

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Assemble the simple program?

Address Machine Instruction

Assembly Instruction

Comment

000 1001 sub $0, $0, $0 # $0 = 0

001 1e01 sub $1, $1, $1 # $1 = 0

002 a002 addi $0,$0,0x2 # $0 = 2

003 ac03 addi $1,$1,0x3 # $1 = 3

004 1400 add $0,$0,$1 # $0 = 5

All numbers in hex

Fall 2006 1 EE 333 Lillevik 333f06-l13 University of Portland School of Engineering Computer Organization Lecture 13 Controller implementations Register.

Documents

port slide

port equal output slide

ns ps slide

register file

present state ps slide

op outputs

bits r1outread port

fsm state diagram inputs