2-9 Exercise 2-1 The Central Arithmetic Logic Unit EXERCISE OBJECTIVES Upon completion of this exercise, you will be familiar with the role that the CALU plays within a DSP. DISCUSSION Note: Some 'C50 assembler CALU instructions are briefly covered in this exercise. It will be left up to you, the student, to cover the rest of the related material. The material can be found in the following file: C:\LV91027\DOC\TMS320C5x_UsersGuide.pdf. The Central Arithmetic Logic Unit (CALU) is where the most important signal processing manipulations take place. The CALU, also known as the data path, is the principle arithmetic and logic processing path for a DSP. It lies along the data (operand) bus and is an integral part of the execution of nearly every instructions.
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Exercise The Central Arithmetic Logic Unit - Lab-Volt · The Central Arithmetic Logic Unit 2-14 The last arithmetic or logical operation executed by the ALU is stored in the ACCumulator
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2-9
Exercise 2-1
The Central Arithmetic Logic Unit
EXERCISE OBJECTIVES
Upon completion of this exercise, you will be familiar with the role that the CALU
plays within a DSP.
DISCUSSION
Note: Some 'C50 assembler CALU instructions are briefly covered in this
exercise. It will be left up to you, the student, to cover the rest of the related
material. The material can be found in the following file:
C:\LV91027\DOC\TMS320C5x_UsersGuide.pdf.
The Central Arithmetic Logic Unit (CALU) is where the most important signal
processing manipulations take place.
The CALU, also known as the data path, is the principle arithmetic and logic
processing path for a DSP.
It lies along the data (operand) bus and is an integral part of the execution of nearly
every instructions.
The Central Arithmetic Logic Unit
2-10
A fixed-point CALU contains:
– Multiplier(s)
– Accumulator(s)
– Operand registers
– Shifters
– At least one Arithmetic Logic Unit (ALU)
Signal processing algorithms are almost entirely devoted to arithmetic and logic
operations. The CALU is designed to execute these types of operations extremely
rapidly.
A DSP is differentiated from a general-purpose processor by:
1. Its memory architecture (a DSP usually has a Harvard architecture).
2. The rapid execution time of the CALU (or data path).
The Central Arithmetic Logic Unit
2-11
Both the Multiplier and the ALU are simultaneously used during a MAC instruction.
The CALU is said to be using its entire computational bandwidth.
For most DSPs, when the entire computational bandwidth of the CALU is
repetitively used, a result is produced every clock cycle.
The operand registers play an important role within the CALU.
The registers are used to temporarily store operands, before they are supplied for
arithmetic operations to the ALU or Multiplier.
The CALU of the TMS320C50 ('C50) has 3 operand registers.
Memory-mapped Temporary REGister 0 (TREG0) is an operand register used by
the Multiplier.
It holds one of the multiplication operands for the Multiplier.
The Product REGister (PREG) is a 32-bit operand register which stores the
Multiplier result.
The value held in the PREG can be sent to the ALU for an arithmetic operation, or
it can be passed on to the Data Bus (DB) for the another stage of processing.
ACCB (the ACCumulator Buffer) provides a temporary storage place for the value
held by in the ACCumulator register (ACC).
The ACC register is designed to hold the last arithmetic result produced by the
ALU.
The ALU is designed to implement a wide range of arithmetic and logical
operations.
The Central Arithmetic Logic Unit
2-12
EXAMPLE OPERAND 1 OPERAND 2 OPERATION OUTPUT
1 1011 0100 0001 1101 ADD 1101 0001
2 1011 0100 0001 1010 SUBTRACT 1001 1010
3 0010 1001 1011 1101 AND 0010 1001
4 0010 1001 1011 1101 OR 1011 1101
5 0111 0101 – NEGATE 10001011
Some operations that are commonly executed by the ALU include: addition,
subtraction, negation, and logical and, or, xor, and not.
The majority of ALU instructions execute within a single clock cycle.
Most of the ALU instructions that take more than one clock cycle rely on other units
for pre- or post-processing of data.
E.g., add a data value to the ACC and then execute a binary shift. The TMS320C50
requires 2 clock cycles to execute the operation. The binary shift is an example of
the type of processing that takes place after addition.
The ALUs of fixed-point DSPs execute 2s-complement arithmetic.
The ALU executes operations using twice the precision of the native word width of
the processor.
For example the ALU of the 'C50, a 16-bit fixed-point DSP, inputs, outputs, and
executes with a 32-bit word width.
The Central Arithmetic Logic Unit
2-13
Most DSP have an ALU mode of operation called sign-extension mode.
When enabled all ALU outputs are sign-extended.
Sign extension prevents a negative number from being mistaken for a positive one.
When the number of bits used to represent a word (e.g., 16 bits) is less than the
number of bits required to represent the same word inside of the CALU (32 bits)
then sign-extension extends the sign-bit into the added MSBs.
If the following 16-bit 2s-format number:
1011 0111 0010 0001 b
was loaded using the ALU into a 32-bit Accumulator when sign-extension mode
was enabled what would be the contents of the Accumulator register?
a. 0000 0000 0000 0000 1011 0111 0010 0001 b
b. 1011 0111 0010 0001 b
c. 1111 1111 1111 1111 1011 0111 0010 0001 b
d. None of the above.
The Central Arithmetic Logic Unit
2-14
The last arithmetic or logical operation executed by the ALU is stored in the
ACCumulator (ACC).
The result held in the ACC can either be stored in the ACC Buffer register (ACCB),
passed on to the ALU, or to another stage of processing using the Data Bus (DB).
In the case of the 'C50 DSP, two operands need to be input into the ALU to execute
any of its arithmetic or logical operations.
One of the operands is supplied by the ACCumulator register (ACC).
One of three other locations provide the other data operand for an ALU operation:
– Data path (e.g., to fetch an operand from memory)
– Multiplier Product REGister (PREG)
– ACCumulator Buffer (ACCB) register
Multiplication is an essential operation used in virtually all digital signal processing
applications.
In many of the applications where multiplication is used half or more of the
instructions executed by the processor are multiplication operations.
Central to nearly all programmable digital signal processors is the single-cycle
Multiplier.
The Multiplier refers to the circuit within the DSP that executes the multiplication of
binary numbers.
Depending on operand size(8-bit or 16-bit for the C50), nearly all Multiplier
instructions can be executed within one clock cycle.
The Central Arithmetic Logic Unit
2-15
Multiplication in fixed-point DSPs is executed with 2s-complement arithmetic.
A Multiplier requires a minimum two operands to execute a multiplication.
These operands are treated as 2s-complement numbers.
In the TMS320C50, register TREG0 is always used as one of the operand sources
for the Multiplier.
In certain cases, such as when the square root instructions (SQRA and SQRS) are
executed, there are no other operands than TREGO used by the Multiplier.
When another multiplication operand is required it is fetched from one of two other
locations:
– Data memory using the Data Bus (DB)
– Program memory using the Program Bus (PB)
The Central Arithmetic Logic Unit
2-16
As previously stated, the Multiplier result is stored in a Product REGister (PREG).
The product register is twice as wide as the word width of the multiplication
operands (native data word width of the DSP).
OPERAND 1 OPERAND 2 OPERATION RESULT PREG (AFTER SIGN EXT.)
0111 0111
(+ 119)
0011 0111
(+ 55)
MULTIPLIER 0001 1001 1001 0001
(+ 6545)
0001 1001 1001 0001
(+ 6545)
0110 0110
(+ 102)
1011 0111
(- 73)
MULTIPLIER 0010 0010 1110 1010
(+ 8938)
FALSE
1110 0010 1110 1010
(- 7446)
All Multiplier results are sign-extended before they are stored in the Product
REGister (PREG).
This combined with the fact that the PREG has twice the operand word width
means that, by itself, the Multiplier does not introduce any errors into computations.
To keep the level of arithmetic precision constant, the number of bits that are used
to represent multiplication, accumulation and other arithmetic operation results,
need to be increased.
That is why that in DSPs the Multiplier Product Register and the ALU ACCcum-
ulator (ACC) have a width twice that of the native data word width.