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REV. Pr T
Information furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third partieswhich may result from its use. No license is granted by implication orotherwise under any patent or patent rights of Analog Devices.
aEVAL-AD765XCB/AD766XCB/AD767XCB
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
The evaluation software described in this document is alsocompatible with the following previous generation of highresolution ADCs.
Evaluation Board AD765X/AD766X/AD767X
FEATURES
Versatile Analog Signal Conditioning Circuitry
On-Board Reference, Crystal Oscillator and Buffers
16-Bit Parallel Buffered Outputs
Ideal For DSP and Data Acquisition Card Interfaces
Analog and Digital Prototyping Area
EVAL-CONTROL BOARD Compatibility
PC Software for Control and Data Analysis
GENERAL DESCRIPTIONThe EVAL-AD765XCB/AD766XCB/AD767XCB is an evalu-ation board for the AD765X/AD766X/AD767X 16-bit A/Dconverter family. The AD765X/AD766X/AD767X family (see ordering guide for product list ) is a high speed, succes-sive approximation based architecture with very highperformance, low power family of 16-Bit and 18-Bit ADCswhich operate from a single +5V supply with a 100kSPS to1MSPS throughput rate range, and a flexible parallel or serialinterface. The AD765X/AD766X/AD767X evaluation boardis designed to demonstrate the ADC's performance and toprovide an easy to understand interface for a variety of systemapplications. A full description of the AD765X/AD766X/AD767X is available in the Analog Devices AD765X/AD766X/AD767X data sheets and should be consulted whenutilizing this evaluation board.The EVAL-AD765XCB/AD766XCB/AD767XCB is ideal foruse with either the Analog Devices EVAL-CONTROL BRD2,or as a stand-alone evaluation board. The design offers theflexibility of applying external control signals and is capable ofgenerating conversion results on a parallel 16-Bit wide buff-ered outputs.
On-board components include an AD780, a +2.5V ultrahighprecision bandgap reference, a signal conditioning circuitwith two op-amps and digital logic. The board interfaces witha 96-way connector for the EVAL-CONTROL BRD2, a 26-pin IDC connector for serial output interface, and a 40-pinIDC connector for parallel output data. SMB connectors areprovided for the low noise analog signal source, an externalmaster clock and an external start/convert input.
The term AD76XX is used in this document to represent allthe ADCs listed in the ordering guide.
P3. Additionally, BD data is updated on the falling/rising edgeof DBUSY and BBUSY on P3. When either parallel or serialreading mode of the ADC is used, the data is available on thisparallel bus. When serial reading mode of the ADC is used, theserial interface signals of the ADC are buffered and available onthe 26-pin connector P1. When slave serial reading mode of theAD765X/AD766X/AD767X is used, the external serial clockSCLK applied to the ADC is the MCLK frequency.
Power Supplies and Grounding
The evaluation board ground plane is separated into two sec-tions: a plane for the digital interface circuitry and an analogplane for the analog input and external reference circuitry. Toattain high resolution performance, the board was designed toensure that all digital ground return paths do not cross the ana-log ground return paths.
The EVAL-AD765XCB/AD766XCB/AD767XCB is supplied bythe EVAL-CONTROL BRD2 or through the two power supplyblocks SJ1 and SJ2 in stand-alone operation.
Analog Input RangesThe analog front-end amplifier circuitry U6 and U7 allows flex-ible configuration changes such as positive or negative gain,input range scaling, filtering, addition of a DC component, useof different op-amp and supplies.Table VII shows the front end op-amp configuration used withthe AD76XX. In some applications, it is desired to use a bipolaror wider analog input range like, for instance, ± 10V, ± 5V, ±2.5V, or 0 to +5V. For the AD76XX parts which do not havedirectly those input ranges like the AD7650-3/7660-1/7664/7666-7, by simple modifications of the input driver circuitry ofthe EVAL-AD765XCB/AD766XCB/AD767XCB, bipolar andwider input ranges can be used without any performance degra-dation. Components values required and resulting full-scaleranges are shown in table IV and table V.In factory, the analog input of U6 is set at mid-scale(R6=R7=590�) for the AD7650/7660/7664/7675/7676/7677.For AD7663/7665/7671, R7 is not connected to maintain the
OPERATING THE EVAL-AD765XCB/AD766XCB/AD767XCBThe EVAL-AD765XCB/AD766XCB/AD767XCB is a four-layer board carefully laid out and tested to demonstrate thespecific high accuracy performance of the AD765X/AD766X/AD767X. Figure 1 shows the schematics of theevaluation board. The layouts of the board are given in :Top side silk-screen - Figure 2Top side layer - Figure 3Ground layer - Figure 4Shield layer - Figure 5Bottom side layer - Figure 6Bottom side silk-screen - Figure 7.The EVAL-AD765XCB/AD766XCB/AD767XCB is a flex-ible design that enables the user to choose among manydifferent board configurations. A description of each select-able jumper/switch is listed in Table II and the available testpoints are listed in Table III. Note that the button of aswitch in position A ( U10 side ) defines a low level. Theswitches are active only in stand-alone mode.
The EVAL-AD765XCB/AD766XCB/AD767XCB is config-ured in factory for the range shown in Table I. Thefront-end amplifiers U6 and U7 are set with a gain of +1.The board is set to be powered through the EVAL-CON-TROL BRD2, and the on-board CNVST generation isused.
On-board or external CNVST could be used. When anexternal CNVST signal is applied, this signal should havevery low jitter and sharp edges to get the best noise perfor-mance of the part. Meanwhile, it is recommended to use theon-board CNVST generation which is done by dividingMCLK signal (40MHZ) by the numbers shown in Table I,which are entered in the software. MCLK can come eitherfrom the local oscillator or the EVAL-CONTROL BRD2’sDSP. Activity on BUSY pin of the ADC turns on the LED.
Conversion data is available at the output bus BD on U10,on the 40-pin connector P2, and on the 96-pin connector
FUNCTIONAL BLOCK DIAGRAM
40 PINCONN
26 PINCONN
+/-12 V
+/-5 V
VL
96 PINCONN
+5 V
AIN-
SIGNALCONDITIONING
REF 2.5V AD780
AD765X orAD766x orAD767x
REF
DATA
CNVST
AIN+
IN
Clock
DIGITAL LOGIC
Configuration switches
MCLK
BUSY
CNVST
MCLK
REV Pr T –3–
EVAL-AD765XCB/AD766XCB/AD767XCB
PRELIMINARY TECHNICAL DATA
input at 0V (mid-scale). This allows a transition noise testwithout any other equipment. An FFT test can be done byapplying a very low distortion AC source.
Table I. CNVST GENERATION
Part Division Throughput RangeRatio kSPS
AD7650 70 571KSPS 0 to 2.5VAD7651 400 100KSPS 0 to 2.5VAD7652 80 500KSPS 0 to 2.5VAD7653 40 1MSPS 0 to 2.5VAD7654 80 500KSPS 0 to 5VAD7655 80 500KSPS 0 to 5VAD7660 400 100KSPS 0 to 2.5VAD7661 400 100KSPS 0 to 2.5VAD7663 160 250KSPS +/-5VAD7664 70 571KSPS 0 to 2.5VAD7665 70 571KSPS +/-5VAD7666 80 500KSPS 0 to 2.5VAD7667 40 1MSPS 0 to 2.5VAD7671 40 1MSPS +/-5VAD7674 50 800KSPS +/-5VAD7675 400 100KSPS +/-2.5VAD7676 70 500KSPS +/-2.5VAD7677 40 1MSPS +/-2.5VAD7678 400 100KSPS +/-5VAD7679 70 571KSPS +/-5V
EVAL-CONTROL BOARD INTERFACE
The EVAL-AD765XCB/AD766XCB/AD767XCB interfacesto the EVAL-CONTROL BRD2 through the 96-way connec-tor. The EVAL-CONTROL BRD2 provides all necessarysupplies to the EVAL-AD765XCB/AD766XCB/AD767XCB.
RUNNING THE EVAL-AD765X/AD766X/AD767XCBSOFTWARE
Software Description
The EVAL-AD765XCB/AD766XCB/AD767XCB comes withsoftware for analyzing the AD765X/AD766X/AD767X, theAD67X and AD97x family. Through the EVAL-CONTROLBRD2 one can perform a histogram to determine code transi-tion noise, and Fast Fourier Transforms (FFT's) to determinethe Signal-to-Noise Ratio (SNR), Signal-to-Noise-plus-Distor-tion (SNRD) and Total-Harmonic-Distortion (THD). The ACperformances can also been evaluated after digital filtering (averaging ) with enhanced resolution ( up to 32 bits ). Thefront-end PC software has four screens as shown in Figure8,9,10 and 11. Figure 8 is the Setup Screen where input volt-age range, sample rate, number of samples are selected. Figure9 is the Histogram Screen, which allows the code distributionfor DC input and computes the mean and standard deviation.Figure 10 is the FFT Screen, which performs an FFT on thecaptured data, computes the Signal-to-Noise Ratio (SNR),Signal-to-Noise-plus-Distortion (SINAD) and total-Harmonic-Distortion (THD). Figure 11 is the time domainrepresentation of the output. When the on-board CNVSTgeneration is used, a synchronous FFT could be achieved bysynchronizing the external AC generator with the Fsync signal(J5) which is an exact division by 2 of MCLK. Figure 12 is theFFT Screen when averaging is used.
Software Installation
- Double-Click on Setup.exe from the CD-ROM and follow theinstallation instructions.
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EVAL-AD765XCB/AD766XCB/AD767XCB
–4–
PRELIMINARY TECHNICAL DATA
TABLE II. JUMPER DESCRIPTION
Jumper Default position FunctionDesignation with the control
board ( Factorysettings)*
JP6* A, U10 side Selection of RDC ( Read during convert ). When the button of the switch is close toJ4 connector ( not A position ) and when the serial reading mode is selected, the dataare read during conversion otherwise the data are read after conversion.
JP7* A, U10 side Selection of PD ( Powerdown ). When the button of the switch is close to J4 connec-tor ( not A position ), the ADC is in power-down mode.
JP8* A, U10 side BYTESWAP. Outputs MSB on D[15:8] and LSB on D[7:0]. When in not A position, outputs LSB on D[15:8] and MSB on D[7:0].
JP9* A, U10 side Selection of RESET. When the button of the switch is close to J4 connector ( not Aposition ), the ADC is reset.
JP10* A, U10 side Selection of SER/PAR ( serial/parallel reading mode ). When the button of the switchis close to J4 connector ( not A position ), the data are read in serial mode otherwisethe data are read in parallel mode.
JP11* not A, J4 side Selection of OB/2C ( coding ). When the button of the switch is close to J4 connector( not A position ), the ADC uses a straight binary coding otherwise the twos comple-ment coding is used.
JP12* A, U10 side Selection of WARP. When the button of the switch is close to J4 connector ( not Aposition ), the ADC uses the WARP mode which is the fastest one.
JP13* A, U10 side Selection of IMPULSE. When the button of the switch is close to J4 connector( not A position ), the ADC uses the IMPULSE mode which is the mode with thelowest power dissipation.
JP14* A, U10 side TEST1. For factory use only and it is pull down.
JP15* A, U10 side TEST0. For factory use only and it is pull down. Should be in A position instandalone
JP16* A, U10 side Selection of EXT/INT ( use of external or internal serial clock ). When the button ofthe switch is close to J4 connector ( not A position ) and when the serial readingmode is selected, the data are read with an external serial clock SCLK generated fromthe master clock MCLK otherwise the data are read with the ADC serial clock. Whenexternal serial clock reading mode is selected, MCLK has to be fast enough to be ablethe read the data properly as explained in the AD766X data sheet. JP16 has no use inparallel reading mode.
JP17* A, U10 side Selection of INVSYNC ( SYNC active level ). When the button of the switch is closeto J4 connector ( not A position ) and when the master serial reading mode is selected, the SYNC signal is active Low. JP17 has no use in parallel reading mode orslave serial reading mode.
JP18* A, U10 side Selection of INVSCLK ( SCLK active edge ). When the button of the switch is closeto J4 connector ( not A position ) and when the serial reading mode is selected,INVSCLK is high. JP18 has no use in parallel reading mode.
JP20 NO BUF Selection of REF signal. When JP20 is in BUF position, the REF is buffered. WhenJP20 is NO BUF position, the REF is the AD780 output.
JP22 not A Selection of CNVST signal. When JP22 is in position A, the signal on J3 is usedotherwise the on-board CNVST generation is used. MCLK signal is used to generatethe on-board CNVST signal.
*JP6-JP18 are used only in stand-alone mode.
REV Pr T –5–
EVAL-AD765XCB/AD766XCB/AD767XCB
PRELIMINARY TECHNICAL DATA
Table III. EVAL-AD765XCB/AD766XCB/AD767XCB TestPoints
Test Point Available Signal
TP1 BUSY ADC BUSY signalTP2 A0TP3 SIG+ ADC Analog inputTP4 AGND Analog ground close to SIG+TP5 REF ADC Reference inputTP7 DGND Digital groundTP8 CNVST ADC CNVST signalTP9 AGND Analog ground close to REFTP10 C S ADC CS signalTP11 R D ADC RD signalTP12 OVDD ADC digital output supplyTP13 DVDD ADC digital core supplyTP14 AVDD ADC analog supplyTP15 AGND Analog groundTP16 SIG- ADC Analog inputTP17 DGND Digital ground
Table IV. Component values Vs. Input ranges ( AD7660 )
Input range R1 R3 R6 R7
± 10V 8k� 1k� 8k� 10k�± 5V 8k� 2k� 6.67k� 10k�
0 to -5V 8k� 8k� 0� none
Table V. Component values Vs. Input ranges ( AD7650AD7664 )
Input range R1 R3 R6 R7
± 10V 2k� 250� 8k� 10k�± 5V 2k� 500� 6.67k� 10k�
0 to -5V 1k� 1k� 0� none
Jumper Default position FunctionDesignation with the control
board ( Factorysettings)
JP23 not A Selection of the master clock MCLK signal. When JP5 is in position A, the J4signal is used otherwise the on-board 40 MHz clock is used as a MCLK signal.MCLK signal is used to generate the on-board CNVST signal and the external serialclock SCLK.
TABLE II. JUMPER DESCRIPTION
REV. Pr T
EVAL-AD765XCB/AD766XCB/AD767XCB
–6–
PRELIMINARY TECHNICAL DATA
TESTING METHODS
Histogram
To perform a histogram test, apply a DC signal to the input. Itis advised to filter the signal to make the DC Source noise com-patible with that of the ADC. C26 provides this filtering.
AC Testing
To perform an AC test, apply a sinusoidal signal to theevaluation board. Low distortion, better than 100dB, is requiredto allow true evaluation of the part. One possibility is to filter theinput signal from the AC source. There is no suggestedbandpass filter but consideration should be taken in the choice.Furthermore, when the full-scale input range is more than a fewVpp, it is recommended that you use the on board amplifier toamplify the signal, thus preventing the filter from distorting theinput signal.
Decimated Testing ( Averaging )This test can be run as the AC test.
Please refer to Figures 8,9,10,11 and 12 to see the screens ofthe software.
Software DescriptionThe AD16bit.exe is the software which allows you to analyzedifferent performance characteristics of the AD765X,AD766X, AD767X, AD97X and AD67X 16-bit ADC family.The software allows you to test the histogram as well as per-form different AC tests.
Setup Requirements
- Evaluation Control Board 2 (ADSP2189)
- Evaluation Board
- Power Supply (AC 15V/1A source could be bought fromADI)
- Parallel Port Cable (provided with the evaluation controlboard)
- AC Source (low distortion)
- DC Source (low noise)
- Bandpass Filter (value based on your signal frequency, lowdistortion)
USE OF EVAL-AD765XCB/AD766XCB/AD767XCB ASSTAND-ALONE EVALUATION BOARD
You have the option of using theEVAL-AD765XCB/AD766XCB/AD767XCB as a stand-aloneevaluation board. This method does not require theEVAL-CONTROL BRD2, nor does it require use of the ac-companied software. The digital output will now be availableon P1 (26-pin connector, for use in master serial mode) or P2(40-pin connector, for use in both serial and parallel mode).When in stand-alone, CNVST could be externally applied or isgenerated internally according to Table I.
Please refer to Figure 1 to obtain the data output pins on theconnectors.
Data is updated on the falling edge of BUSY. When BCS andCONTROL are low, which is the default value defined by theon-board pull-down resistors, the data bus BD available on theP2 connector is enabled.
SUPPLYING THE BOARD FOR STAND-ALONE USE
SJ1 is the analog supply. Apply +/-12V on +12V and -12Vpins and +5V on +5V pin. SJ2 is the digital supply. Apply 5Von VDIG pin.
REV. Pr T –7–
PRELIMINARY TECHNICAL DATA
EVAL-BOARD SETTING FOR INPUTCONFIGURATIONSThe AD7663/AD7665 and AD7671 have the ability to oper-ate both unipolar and bipolar range. The available options are+/- 10V, +/- 5V, +/- 2.5V, 0 to 10V, 0 to 5V and 0 to 2.5V. (See application note AN594 on the product web page forother ranges )
Table VI shows the required configurations for each inputrange. (REF = 2.5V). Table VII lists the default settings ofthe board for all parts.
Table VI. AD7663/7665/7671 Analog Input Configuration
Input Voltage IND(4R) INC(4R) INB(2R) INA(R) Range
±4 REF VIN INGND INGND REF ±2 REF VIN VIN INGND REF ±REF VIN VIN VIN REF 0 V to 4REF VIN VIN INGND INGND 0 V to 2REF VIN VIN VIN INGND 0 V to REF VIN VIN VIN VIN
Table VII. Default Settings
Component/Part R7 S9 S10 R48 C40 R47 C39
AD7650 590� None 0� 15� 2.7nF N/A N/A
AD7651 590� None 0� 0� None N/A N/A
AD7652 590� None 0� 15� 2.7nF N/A N/A
AD7653 590� None 0� 15� 2.7nF N/A N/A
AD7654 590� None 0� 0� None N/A N/A
AD7655 590� None 0� 0� None N/A N/A
AD7660 590� None 0� 0� None N/A N/A
AD7661 590� None 0� 0� None N/A N/A
AD7663 None None 0� 0� None N/A N/A
AD7664 590� None 0� 15� 2.7nF N/A N/A
AD7665 None None 0� 0� None N/A N/A
AD7666 590� None 0� 15� 2.7nF N/A N/A
AD7667 590� None 0� 15� 2.7nF N/A N/A
AD7671 None None 0� 0� None N/A N/A
AD7674 590� 0� None 15� 2.7nF 15� 2.7nF
AD7675 590� 0� None 15� 2.7nF 15� 2.7nF
AD7676 590� 0� None 15� 2.7nF 15� 2.7nF
AD7677 590� 0� None 15� 2.7nF 15� 2.7nF
AD7678 590� 0� None 15� 2.7nF 15� 2.7nF
AD7679 590� 0� None 15� 2.7nF 15� 2.7nF
REV. Pr T
EVAL-AD765XCB/AD766XCB/AD767XCB
–8–
PRELIMINARY TECHNICAL DATA
12
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ABCD
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R44
R43
TP7
AG
ND
R61
0.0
R29
590
R60
590
C42
.1uF
C35
10pF
C37
.1uF
C41
TP4
AG
ND
GN
D
R59
C34
10pF
R6 590
R7 590
R42
0.0
C26
C36
C22
.1uF
TP3
SIG
+
S1S2
S4S6
R48 15
R46 0.0
VD
RV
-
C40
2.7n
F N
PO
C38
VD
RV+
R45 0.
0
+VA
GN
D
GN
D
GN
D
S3S5
GN
D
S7
R47
15
C39
2.7n
F N
POTP
16SI
G-
C20
.1uF
C19
R2 R1
R3
0.0
2 3
4
56
7
U7
AD
8021
TP5
REF
C32B
47uF
C31B
1uF
C9B
.1uF
TP9 A
GN
D
TP14
AV
DD
TP13
DV
DD
C9T
GN
D
2 3
4
56
7
U6
AD
8021
GN
D
GN
DGN
D
GN
D
VD
RV+
VD
RV
-
VD
RV+
VD
RV
-
DC+
DC-
DV
DD
GN
D
J1 AIN
+
J2 AIN
-
SIG
+
SIG
-
S12
GN
D
DVDD19
OVDD18
AVDD2
REF
37
REFG
ND
38
DGND17
DGND20
AGND1
D3/
DIV
SCLK
(1)
12D
2/D
IVSC
LK(0
)11
D1
10D
09
D4/
EXT/
INT
13
D5/
INV
SYN
C14
D6/
INV
SCLK
15
D7/
RDC/
SDIN
16
RESET33
IMPULSE7
PD34
BYTESWAP4
A0
3
IN_A
40IN
_B41
IN_C
42IN
_D/IN
+43
ING
ND
/IN-
39
REFI
N46
PDRE
F/T0
47
INA
144
INA
N/T
EMP
45PD
BUF/
T148
D10
/SY
NC
23D
9/SC
LK22
D8/
SDO
UT
21
CS32
CNV
ST35
BUSY
29
D11
/RD
ERRO
R24
D12
25
D13
26
D14
27
D15
28
RD
31
T0/P
DRE
F36
T1/E
OC
30
OB/2C5
WARP6
SER/PAR8
U1
AD
76X
XCN
VST
CSRDBU
SY
RESE
T PDD0
BYTED1
IMPU
LSE
D2
WA
RPD3
OB/
2CD4
SER/
PAR
D5
T1/E
OC
D6
PDRT
0
D7
D8
D9
D10
D11
D12
D13
D14
D15
PDRESE
T
IMPU
LSE
SER/
PAR
RD
OV
DD
CSCNVS
T
D[0
..15]
BUSY
DC-
A0
A0
TP12
OV
DD
D[0
..15]
ING
ND
IN_A
IN_B
IN_C
IN_D
T0PD
R
PDBT
1
S10
S9
S15
S14
S13
S11
S20
S8
C31T
C13
GN
D
TEM
P
S19
-6
+5
7
U9B
AD
8032
AR
-2
+3
48
1
U9AV
REF+
GN
D
C1 .1uF
C14
10uF
GN
D
C2 .1uF
C15
10uF
GN
D
C3 .1uF
GN
D
DC+
DC-
S30
S31
R26
590
VRE
F2.5
VRE
F2.5
R23
0.0
R10
GN
D
R5
D5
IN1
S14
S26 U
3A
DG
719B
RT
S16
S17
R24
49.9
TEM
P
C47
0.1u
F
AIN
-IMD
AIN
-IMD
R18
AV
DD
S18
VRE
F2.5
-2
+3
48
1U
2A
GN
D
C29
.1uF
C27
1uF
C28
.1uF
R8 1 M
eg
VR1
50K
CC25
.1uF
VRE
F+
GN
D
GN
D
GN
D
C9 1uF
IN3
GND2
OU
T1
U5B
AD
158X
R9 10K
R4
C6 1uF
VRE
F+
VRE
F2.5
S21
JP20
VO
UT
6
TRIM
5
GND4
TEM
P3
+VIN2
2.5/3v8
U5A
AD
R42X
/AD
780
NOTE
:EI
THER
U5A
OR
U5B
IS U
SED
AT
ATI
ME
R37
10K
R69
GN
D
A
C5B
.1uF
C5T
C7B
.1uF
C7T
AV
DD
AV
DD
DV
DD
OV
DD
R25
49.9
S2/S
1S2
/S1
REF
GN
D
VRE
F+
+VA
C4
GN
D
AD
76X
X-A
NA
LOG
Figure 1. Schematic
REV Pr T –9–
EVAL-AD765XCB/AD766XCB/AD767XCB
PRELIMINARY TECHNICAL DATA
Figure 1 Schematic
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78
910
1112
1314
1516
1718
1920
2122
2324
2526
2728
2930
3132
3334
3536
3738
3940
P2
GN
D
R28
100
R30
100
JP22
R36
1 M
egTP
8
CN
VO
UT
CNV
ST
VIO
J3CN
VST
IN
BD0
BD1
BD2
BD3
BD4
BD5
BD6
BD7
BD8
BD9
BD10
BD11
BD12
BD13
BD14
BD15
GN
D
VIO
R32
100
R55
10K
R68
49.9
TP1
BUSY
TP11
TP10
PD
T0PD
R
SER/
PAR
OB/
2C
WA
RP
IMPU
LSE
BYTE PD
RESE
T
BUSY R
D CS
CNV
STC
NV
OU
T
BYTE
RESE
T
OB/
2C
SER/
PAR
IMPU
LSE
CNV
ST
D[0
..15]
PDBT
1
D0
D1
D2
D3
D4
D5
D6
D7 D8
D9 D10
D11
D12
D13
D14
D15
D[0
..15]
A0
WA
RP
PDRT
0
T1/E
OC
D9
A0
S26
TP2
A0
S24
S25
S22
S23
S28
S29
S27
GN
D
T1 T2 T3 T4 T5 T6
R50
10K
R49
10K
R54
10K
GN
D
DCL
K12
8
CO
NF_
D10
5
CE4
CON
FIG
53
DA
TA12
5
BCS
111
86
MSE
L33
STA
TUS
56
BD3
120
AD
CO
K49
BD4
117
D11
10
MCL
K13
2
AD
093
AD
196
AD
295
DR0
122
TFS0
118
SCLK
011
6
FSY
NC
131
BBU
SY85
BD15
73
BD13
81BD
1272
BD11
84BD
1087
BWR
114
BD9
94BD
810
9BD
711
0BD
611
2BD
511
5
BD2
123
BD1
124
BD0
129
CON
TRO
L13
0
D12
2
D13
1
BRD
113
BD14
82
DT0
121
RFS0
119
MO
DE0
47
MO
DE1
46
MO
DE2
45
DSP
CLK
71
MO
DE3
44
RESE
TS43
D10
11D
912
D8
14
D14
144
D0
26
CNV
ST13
7
D6
16
D7
15
D15
143
D1
25
D2
24
D3
23
D4
22
D5
21
BUSY
142
RD
141
CS14
0
RESE
T13
9
PD13
8
CNV
STO
UT
136
SER/
PAR
35
IMPU
LSE
36
WA
RP
37
OB/
2C38
BYTE
39
A0
57
PDRE
F58
TEST
059
EOC
60
TEST
1_O
UT
61
PDB
UF
62
SCLK
IN13
S2/S
141
DBU
SY40
U10
EPF6
010A
TC14
4
R66
10K
3.3V
AD
CO
K
SDO
UT
SCLK
BD0
BD1
BD2
BD3
BD4
BD5
BD6
BD7
BD8
BD9
BD10
BD11
BD12
BD13
BD14
BD15
BBU
SY
CON
TRO
L
R52
10K
R51
10K
R31
100
D2
TP15
DG
ND
TP17
DG
ND
VD
IG1
VD
IG4
OU
T3
GN
D2
U12
3.3V
C30
.1uF
3.3V
AD
1
AD
0
CS4
OE
3
DA
TA1
DCL
K2
U11
EPC1
441
R38
1K R39
1K
R40
1KC1
6.1
uF
GN
D
GN
D
BD0
BD1
BD2
BD3
BD4
BD5
BD6
BD7
BD8
BD9
BD10
BD11
BD12
BD13
BD14
BD15
AD
0
DSP
CLK
AD
1
GN
D
CON
TRO
L
BBU
SY
SCLK
TFS0
SDO
UT
TFS0
SDIN
CO
NF_
D
DCL
K
DA
TA
SDIN
C5 C7C19
B18
A18 B1
7
B15
B14
B13
B11
B10
B7 B6 B5 B3 B2 A14 C1
5
B9C18
A19C1
0
C17
A9
C9 B1A17 A
5
A6
C6C14
P3A
DA
TA
DCL
K
SDIN
SDO
UT
STATUS
FSY
NC
SCLK
CO
NF_
D
CONFIG
12
34
56
78
910
1112
1314
1516
1718
1920 22
21 2324
2526
P1
M0
M1
M2
SYN
C
SYN
C
AD
2
GN
D
AD
2
GN
D
3.3V
SYN
C
3.3V
R65
10K
R63
10K
R64
10K
GN
D
M0
M1
M2
DSP
CLK
R58
10K
R57
10K
M3
R56
10K
R62
10K
M3
TP6
BBU
SY
R34
100
R33
100
J4
JP23
GN
D
GN
DFSY
NC
GN
D
T0
T1
T1
T0
+VA
-VA
+12V
VD
IG
-12V
A4
A12
A16
A20
B4 B12
B16
C4 C12
C16
C20
B20
B26
B27
B28
B29
B30
C21
C22
C23
C24
C25
C26
C29
A21
A22
A32
B32
C32
A31
B31
C31
C30
A8
B8 C8 A30
P3B A
23
A24
A25
A26
A29
B21
B22
B23
B24
B25
P3C
+VA
+12V
GN
D
GN
D
-VA
-12V
VD
IG
C23
.1uF
C24
.1uF
C17
.1uF
C18
.1uF
C25
.1uF
C21
.1uF
GN
D
C5 .1uF
C7 .1uF
C8 .1uF
C10
.1uF
C11
.1uF
C12
.1uF
VIO
GN
D
3.3V
S2/S
1S2
/S1
R53
10K
R41
1KR6
710
K
DBU
SY
VIO
3.3V
GN
D
JP6
JP7
JP8
JP9
JP10
JP11
JP12
JP13
JP14
JP15
JP16
JP17
JP18
RDC
INVSCLK
INVSYNC
EXT/INT
TEST0_IN
R1110K
R1210K
R1310K
R1610K
R1410K
R1710K
R1510K
R1910K
R2010K
R2110K
R2210K
R3510K
SER/PAR
OB/2C
WARP
IMPULSE
RESET
BYTE
PD
D4
D5
D6
D7
RESE
TS
DSE
LBWR
BRD
BCS
BCS
BWR
FSY
NC
BCS
BRD
BWR
CONFIG
STATUS
RESE
TS
DSE
LD
SEL
AD
76X
X-D
IGIT
AL
REV. Pr T
EVAL-AD765XCB/AD766XCB/AD767XCB
–10–
PRELIMINARY TECHNICAL DATA
Figure 1 Schematic
12
34
56
ABCD
65
43
21
D C B A
Titl
e
Num
ber
Rev
isio
nSi
ze B
Dat
e:9-
Sep-
2003
Sh
eet
of
File
:D
raw
n B
y:
IN3
GND1
OU
T2 4
U5
AD
P333
8-2.
5V
IN3
GND1
OU
T2 4
U4
AD
P333
8-3.
3V
C32
1uF
C33
1uF
C46
1uF
SJ2
GN
D
GN
DV
DIGV
DIG
2.5V
3.3V
GN
D
+VA
+12V
JP4 12
43
JP5
-VA
JP3
VD
RV
-
GN
D
3.3V
GN
D
VD
RV
+
VR
EF+
JP19
31 2 54 6
SJ1
C54
10uF
C51
10uF
C53
10uF
C50
10uF
+VA
+12V
-VA
GN
D
AV
DD
GN
D+VA
-VA
+12V
GN
D
GN
D
+VA
+12V
-VA
+VA
IN3
GND1
OU
T2 4
U8
AD
P333
8-2.
5V
C43
1uF
C44
1uF
GN
D
C49
10uF
C48
10uF
OV
DD
DV
DD
1 24
3
JP1
2.5V
3.3V
VD
IG
AV
DD
1 23
JP2
2.5V
VD
IGR
2710
VD
DE
-12V
-12V
-12V
OV
DD
VD
IG
DV
DD
VD
RV
+
-12V
C52
10uF
VD
RV
-
OV
DD
DV
DD
VD
RV
+V
DR
V-
3.3V
VR
EF+
VR
EF+
JP21
3.3VO
VD
D D1
VIO
VIO
AV
DD
AV
DD
GN
D
VIO
VIO
GN
D
AD
76X
X-P
OW
ER
C45
1uF
-6
+5
7U
2B
GN
D
H
REV Pr T –11–
EVAL-AD765XCB/AD766XCB/AD767XCB
PRELIMINARY TECHNICAL DATA
Figure 2. Top side silk-screen ( Not to Scale ).
Figure 3. Top side ( Not to Scale ).
REV. Pr T
EVAL-AD765XCB/AD766XCB/AD767XCB
–12–
PRELIMINARY TECHNICAL DATA
Figure 4. Ground Layer ( Not to Scale ).
Figure 5. Shield Layer ( Not to Scale ).
REV Pr T –13–
EVAL-AD765XCB/AD766XCB/AD767XCB
PRELIMINARY TECHNICAL DATA
Figure 6. Bottom side layer ( Not to Scale ).
Figure 7. Bottom side silk-screen ( Not to Scale ).
REV. Pr T
EVAL-AD765XCB/AD766XCB/AD767XCB
–14–
PRELIMINARY TECHNICAL DATA
2) The part under evaluation is chosen from this menu. Theavailable choices are AD765X, AD766X,AD767X AD97xand AD67x.
1) The Run button starts the software. All input configurationsare read by the software after running the software. You willneed to press this button first.
3) Input Configurations are chosen here. For the AD765X/AD766X/AD767X, the available choices are: PwDown, Re-set, Interface, Coding, Byte, and Reading.
Figure 8. Setup Screen
5) You may choose to take one sample (Sample,F3), or per-form continuous sampling (Continuous,F4). You may alsochoose the Help, Save, Print or Quit options. The Help menuwill show you a description of the functionality of the chosencommand.
This is the performance window.
4) The choice of test is madehere. You may choose to per-form either :- an Histogram test- an AC test- an AC test with decimateddigital filtering.
6) (Documentation.F2) gives direct acces to datasheets
And evaluation documentation...
REV Pr T –15–
EVAL-AD765XCB/AD766XCB/AD767XCB
PRELIMINARY TECHNICAL DATA
Figure 9. Histogram Screen
Different measurements are displayed here. The DC value,transition noise, and other values.
This control allows you the choice of display. You have theoption of Time or Histogram. You also have the option ofchanging the X-axis unit
The results are displayed on this chart. You may also use thecursor (yellow) and drag it to your desired location, where theX-axis value and the Y-axis value will be displayed.
REV. Pr T
EVAL-AD765XCB/AD766XCB/AD767XCB
–16–
PRELIMINARY TECHNICAL DATA
Figure 10. FFT Screen
AC test results are shown here. You also have thechoice of viewing the amplitude of a certain FFTcomponent by changing the FFT componentmenu.
You may choose either a Kaiser window or a Blackmann-Har-ris window or a Sync FFT from this menu. . When choosing aSync FFT, you will need to synchronize your analog source tothe sampling frequency. The input frequency should be thevalue Sync Fr, which is to the right of Target frequency. Theprocess for this is as follows:1. You Choose a Target frequency2. The software calculates an integer n based on the targetfrequency you entered and the sampling frequency, Fsamp.
3. The software rounds up the value n to the next primenumber.4. The software then calculates the corresponding input fre-quency (Fin) and displays that as Sync Fr.The equation, (capture window size) is shown below:(1/Fsamp) * (number of samples) = n * (1/Fin)
This is the control that allows youthe choice of either time domainor frequency domain. You mayalso change the X-axis unit here.
The results are displayed on this chart. You may also use thecursor (yellow) and drag it to your desired location, where theX-axis value and the Y-axis value will be displayed.
REV Pr T –17–
EVAL-AD765XCB/AD766XCB/AD767XCB
PRELIMINARY TECHNICAL DATA
To view the Time domain, select Time in this menu.
You can also view the output in the Time domain as shown below.
Figure 11. Time-Domain Screen
REV. Pr T
EVAL-AD765XCB/AD766XCB/AD767XCB
–18–
PRELIMINARY TECHNICAL DATA
AC test results with decimated averaging areshown here. The SNR indicator also represent thedynamic range when no AC signal is applied.
This is the control that allows youthe choice of either time domainor frequency domain. You mayalso change the X-axis unit here.
The results are displayed on this chart. You may also use thecursor (yellow) and drag it to your desired location, where theX-axis value and the Y-axis value will be displayed.
The decimation ratio and theaverage length is defined here.
Figure 10. Decimated ( Averaging ) Screen
The ADC sampling frequency isdefined by the ratio.
The output word rate after deci-mation is shown here. It is theratio between the ADC samplingrate and the decimattion ratio.