Embedded systems, architectures, methodologies, · PDF fileEmbedded systems, architectures, methodologies, outlook Advanced System Technology Andrea Cuomo, Corporate Vice President

Embedded systems, architectures, methodologies, outlook

Advanced System Technology Andrea Cuomo, Corporate Vice President

Parallel Processing ForumParis, March 28, 2002

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A Wide Variety of Terminals

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Defining Convergence

CONVERGENCE

CONNECTIVITY

STORAGE

MULTIMEDIA

MOBILITY

SECURITY

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Storage

Power management

MMIContent elaboration(base band)

Security

Connectivity

Connectivity

Connectivity

Storage

Content elaboration(base band)

MMI

Power management

Security

Connectivity

Convergence & SoCs Go Hand In Hand

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DisplayProcess.

Display dependentprocessing ...

AudioInterface

DDX, IntelliMic...

Embedded Mem

REMPEGMinimized memory usage

Image InputPipeline

CommunicationPeriph.

BluetoothIrDAUSBGPS ...

Ext. MemIF

FlashSDRAM.

ApplicationSpecificFlash

Periph.

Smartcard

Security

uP

STD OS supportMiddleware, JAVAAPI for MMStreaming ...

MEDIAACCELLERATION e MEM

Image Generation PipelineNoise ReductionPre-processingEnhanced Compression ...

MPEG4, MPEG2, JPEGAAC, AC3, MP2, MP3Watermarking, secured content ...

Multimedia Enabled Terminal

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From The SIA Roadmap...

On one chip we shall have

900 M Transistors10 GHz Clock Rate175 Watts power

HOW SHALL WE DO IT ?HOW SHALL WE DO IT ?

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IDENTIFY SYSTEM INVARIANT HARDWIRE INVARIANTS SOFTWARE TO PERSONALIZE THE VARIABLE PART

BRUTE FORCE SMART

GIPS10s GIPS100s GIPS

ALL IN SOFTWARE

Two Paths forward

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Moores Law

1970 1975 1980 1985 1990 1995 2000 2005

100M

10M

1M

100K

10K

1K

1G

10GTransistors/chip

Year

Memory(DRAM)

Microprocessor

16Mb4Mb

256Kb64Kb

16Kb

1Mb

4Kb

Pentium80486,68040

680008086

80804004

80286

8085

68020

64Mb

P6

P8

256Mb1Gb

4Gb0.100.15

0.40.6

0.25

0.81.22.03.0

5.0

Memory CD (m)

80386

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The Algorithmic Driving ForceShannon asks for more than Moore can deliver...

1

10

100

1000

10000

100000

1000000

10000000

1980

1984

1988

1992

1996

2000

2004

2008

2012

2016

2020

Algorithmic Complexity(Shannons Law)

Processor Performance (Moores Law)

Battery Capacity1G

2G

3G

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IC Design Challenges

1990 1994 1997 2000

R&D cost per

device

Growing Cost per IC

Area

Speed

Power

Metal-Migration

SignalIntegrity

EMI

4

4

4

4

4

4

4

4

4 4

4

4

4

4 4

4

4

4

4 4 4

4

4

4

4

4

4

4

4

4

4

4

1.0 0.8 0.7 0.5 0.35 0.25 0.18 0.15 0.13

Process Impact on Design IC Shortage in Europe

100k 1M 10M

100x Gate Count

1M

100M

10B

10,0

00x

mo

re v

ecto

rsre

qu

ired

to v

alid

ate

100x / 6 years

1990

1996

2002100 x 10,000 =1 million times

more simulation load

10x / 6 years

The Verification Challenge

Verification effort growth outpaces design

8,771,5819,465,229

10,420,587

11,205,233

8,312,534 86126559188511

459,046852573

1232076 1389981

300,000

1,200,000

2,100,000

3,000,000

3,900,000

4,800,000

5,700,000

6,600,000

7,500,000

8,400,000

9,300,000

10,200,000

11,100,000

12,000,000

1998 1999 2000 2001

Demand Offer Skill shortage

Exponential growth

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Challenge

Courtesy of Fred Pollack, IntelKeynote speech, MICRO-32

P4 @ 1.4GHz, 75W

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Which computing engines?

DSP RISC

CISC

VLIWMISA

CustomizableRISC

SuperH,ARMMIPS,Motorola PowerPC

Motorola ColdFireInfineon CarmelTI

ARC,Tensilica

ST200TrimediaTI C6Motorola/Lucent StarCore

Intel x86Motorola 68K

ACM

Quick Silver Tech.

Hyper-threading

Intel

SDF

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Parallel Processing (1) Instruction-Level Parallelism

The schedule: 4 pixels processed in 229/4 = 57.25 cycles per pixel.

The schedule: 4 pixels processed in 229/4 = 57.25 cycles per pixel.

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Navigating The Space of Custom Architectures

Each of these is a single architecture choice

Where you go when you cutone parameter in half

KEY TO THE CHOICES INVESTIGATED HERE:

GMEM - Global memory ports (always 1 here)

SMEM - Static memory ports (not currently used)

LMEM - Local memory ports (not currently used)

IALU - Number of integer ALUs

REG - Number of registers

UNR - Optimal number of pixels to consider at once for this architecture choice

TJ - Cycles per pixel (measure of performance)

xCA~ - Factor faster than i960/CA (another measure of performance)

Faster architectures are to the left

The starred architectures were the sweet spots

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Embedded System Design Turned Right-Side-Up

ARCHITECT THE CPU and relatedsystem tools

BUILD HARDWARE for what you know is a good CPU for the application

Right-Side-Up CPU Design

With the user, PORT THE APPLICATION to family toolset

give it to the user to PORT THE USER APPLICATION TO. Hope the match is good

Traditional CPU Design

BUILD A COMPILER and other system tools for that CPU

BUILD HARDWARE for what you think is a good embedded CPU

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A New Design Methodology

Coststruct_reent

*ptr_AND

struct_reent

*ptr_AND

Same HDTV Decoder source code

HDTV on CTV

FULL HDTV

FULL HI-END CONS. BOX

TransportAudio

MPEG, 2D Graphics

Analog processing in digital

Video pre/post processing

Some 3D graphics

ApplicationsOS

Har

dwar

e1996 1999 2002 2005

Scalability Portability

SYSTEM DESIGN 15%

PCBs, CABLES 5%

SILICON 10%

SOFTWARE 70%

Customers SW investment

HDTV + TCP/IP

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The Environment

Simulator

Hard MacroBehavioralFunctional

RTLNetlist C Model

OS CallDriver

Translation Tools

IP

Analog TV ProcessingProcessor Accelerator

Graphics

Video Processing

AC-3

MemoryManagement

MPEG

Network Interface

Transport

DENC

CPU

Hardware Software

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Multimedia PlatformSoftwareSoftware MiddlewareMiddleware

Lx2 SpecsLx2 Specs

PP

Input I/F

Input I/F

HWAccelerator

HWAccelerator

Media Processor

Media Processor

Rendering Unit

Rendering Unit

MPEG4MPEG4

StreamingStreaming

JavaJava

ViewpointViewpoint

VirtualRendering

VirtualRendering

Image Quality Rendering

Image Quality Rendering

Post ProcessingPost Processing

SlimpegSlimpeg

RempegRempeg

Return ChannelReturn Channel

HardwareHardware

Digital IFDigital IF

DDENCDDENC

Turbo CodesTurbo Codes

Image Capture PipelineImage Capture Pipeline

Pre/Post ProcessingPre/Post Processing

MPEG4MPEG4

H263H263

JPEGJPEG

WaveletWavelet

TranscodingTranscoding

MPEG2MPEG2

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HW/SW Plug & Play

P HW 1 HW 2

DCT / iDCT lib

RLC - VLC lib

CBR lib

Functions library

SW API

SW Motion Est.

HW Motion Est.

Function implementation

Motion. Est. lib

STBUS

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HW/SW Plug & Play

TARGET

APPLICA

TION

SWHW &

driver

IMPLEMEN

TED SYST

EM

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Power Conscious Multistandard Terminal Architecture

RF IF

RF

RF

IF

IF

Digital Hardwired Logic # 1

Digital Hardwired Logic # 3

Digital Hardwired Logic # 2

DSP Processor

Control Processor

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Implementation Space

Log P E R F O R M A N C E

Lo

g F

L E

X I

B I

L I

T Y

Lo

g

P O

W E

R

D I

S S

I P

A T

I O

N

103 - 104

105

-10

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ApplicationSpecific Signal

Processors

DigitalSignal

Processors

GeneralPurpose

Processors

FieldProg