Embedded System Day 6

8/13/2019 Embedded System Day 6

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EMBEDDED SYSTEMS

By: Nikhil Parashar

1



Course Contents

• Introduction to HC12 family, Processor Core

Architecture, MC9S12C32 Features, Block

Diagrams, Programming Models, Pin outs and

Signals, System Clock.

• Register Blocks and Memory Mapping, Modes

of Operation

• Addressing Modes and Assembly Language

Programming



Programming Model

• Two index registers (X and Y)

• 16-bit stack pointer (SP)

•

16-bit program counter (PC)• 8-bit condition code résister (CCR)





Data Types

The CPU12 uses these types of data:

• Bits

• 5-bit signed integers

•8-bit signed and unsigned integers

• 8-bit, 2-digit binary-coded decimal numbers

• 9-bit signed integers

• 16-bit signed and unsigned integers

• 16-bit effective addresses

• 32-bit signed and unsigned integers



Addressing Modes

Addressing modes determine how the central

processor unit (CPU) accesses memory locations to

be operated upon.

•Inherent

• Immediate

• Direct

• Extended

• Relative

• Indexed



Inherent AM

• No operands or all operands are in internal

CPU registers.

• Eg.

NOP ;this instruction has no operands

INX ;operand is a CPU register



Immediate AM

• Eg.

LDAA #$55

LDX #$1234LDY #$67



Direct AM

Sometimes called zero-page addressing

Eg.

LDAA $55LDX $20



Extended AM

The full 16-bit address of the memory location

Eg.

•

LDAA $F03B ; The value from address; $F03B is loaded into the

; A accumulator.



Relative AM

• The relative addressing mode is used only by branchinstructions.

• Short conditional branch instructions

• long conditional branch instructions

• Short branch instructions consist ofan 8-bit opcode and a signed 8-bit offset contained in the

byte that follows the opcode.

• Long branch instructions consist of

an 8-bit prebyte, an 8-bit opcode, and a signed 16-bitoffset contained in the two bytes that follow theopcode.







Index AM

Indexed addressing modes use a 16-bit CPU register and

additional information to create an effective address.

• 5-Bit Constant Offset Indexed Addressing

•

9-Bit Constant Offset Indexed Addressing• 16-Bit Constant Offset Indexed Addressing

• 16-Bit Constant Indirect Indexed Addressing

• Auto Pre/Post Decrement/Increment Indexed

Addressing• Accumulator Offset Indexed Addressing

• Accumulator D Indirect Indexed Addressing



Bit Manipulation Instructions

• combination of two or a combination of three

addressing modes.

• BCLR

• BSET

• BRCLR

•

BRSET



Addressing More than 64 Kbytes

• Some M68HC12 devices supports addressing a largermemory space than the standard 64 Kbytes.

• Uses fast on-chip logic to implement a transparentbank-switching scheme.

• HC12 system requires no external glue logic.• Interrupts do not need to be disabled during switching

because switching tasks are incorporated in specialinstructions that greatly simplify program access toextended memory.

• MCUs with expanded memory treat the 16 Kbytes ofmemory space from $8000 to $BFFF as a programmemory window.



• Expanded-memory architecture includes an 8-bitprogram page register (PPAGE), which allows up to 25616-Kbyte program memory pages to be switched intoand out of the program memory window. This provides

for up to 4 Megabytes of paged program memory.• The CPU12 instruction set includes call subroutine in

expanded memory (CALL) and return from call (RTC)instructions, which greatly simplify the use ofexpanded memory space. These instructions also

execute correctly on devices that do not haveexpanded-memory addressing capability, thusproviding for portable code.




• $0000 - $03FF I/O PORTS

• $3800 - $3FFF INTERNAL RAM

•

$4000 - $7FFF INTERNAL EEPROM• $8000 - $9FFF EXTERNAL RAM

• $C000 - $FFFF INTERNAL EEPROM




Instruction Set• Data Transfer Instruction

1. Load & Store Instruction

2. Transfer & Exchange• Arithmetic Instruction

1. Addition & Subtraction

2. BCD Operation

3. Increment/Decrement

4. Multiplication/Division

• Logical Instruction

1. Boolean Logical Instruction

2. Bit Manipulation

3. Shift & Rotate

4. Compare & Test Instructions

• Branch Instruction1. Short conditional branches

2. Long conditional branches

3. Bit-condition branches

4. Loop Primitives

5. Jumps



• Fuzzy Logic Instruction

1. Fuzzy Logic Membership Instruction

2. Fuzzy Logic Rule Evaluation Instructions3. Fuzzy Logic Weighted Average Instruction

• Maximum and Minimum Instructions

• Multiply and Accumulate Instruction

• Table Interpolation Instructions

• Index Manipulation Instructions

• Stacking Instructions

•

Pointer and Index Calculation Instructions• Stop and Wait Instructions

• Background Mode and Null Operations





• Transfer & Exchange Instructions

MOV Instruction

• AM for MOV Instruction are immediate,extended, and indexed addressing modes.

• The operand of an immediate mode instruction

is data, not an address.

• the operand of an immediate mode instruction is

data, not an address



Transfer & Exchange Instructions

• MOVB ; Move a Byte of Data from

;One Memory Location to Another

• MOVW ; Move a Word of Data from

;One Memory Location to Another



Addition & Subtraction

• ABA ; Add Accumulator B to

;Accumulator A

• ABX ; Add Accumulator B to Index

;Register X

• ABY ; Add Accumulator B to Index

;Register Y

• ADCA ; Add with Carry to A

• ADCB ; Add with Carry to B



• ADDA ; Add without Carry to A

• ADDB ; Add without Carry to B

•

ADDD ; Add Double Accumulator• SBA ;Subtract Accumulators

Addition & Subtraction



BCD OPERATION

• To add binary-coded decimal (BCD) operands,

use addition instructions that set the half-

carry bit in the CCR, then adjust the result

with the decimal adjust A (DAA) instruction.



Increment/Decrement

M lti li ti /Di i i



Multiplication/Division

• Signed and Unsigned 8- and 16-bit multiplication

L i l I t ti



Logical Instructions• Boolean Logical Instructions

The Boolean logic instructions perform a logicoperation between an 8-bit accumulator or

the CCR and a memory value.



Bit Manipulation Instructions

• These uses a mask value to test or change the

value of individual bits in A or in M.



Shift & Rotate Instructions





Compare & Test Instructions



Maximum & Minimum Instructions



Branching OperationsBranch instructions cause execution flow to change when specific pre-

conditions exist and the changes are categorized as

• Resets,

• Interrupts,

• Subroutine calls,

• Conditional branches, and

• Jumps.

Branch operations can be of the types• Short conditional branches

• Long conditional branches

• Bit-condition branches

Types

Short BranchLong Branch

Bit Condition Branch

Loop Primitives

Jumps





• BSR and JSR are used to access subroutines in

the normal 64-Kbyte address space.

• The CALL instruction is intended for use in

MCUs with expanded memory capability.

Branching Operations



Short Branch:





Long Branch







Bit Conditional Branch Instructions



Loop primitive





Interrupt Instructions



Condition Code Instructions



Stop & Wait Instructions



Background Mode & Null



• TExaS= Test EXecute & Simulate



Assembler Directives

Group A Group B Group C Meaning

ORG ORG .ORG Origin of Memory

= EQU Define a constant Symbol

SET Define a constant Symbol

DC.B FCB .BYTE Allocate byte of storage with initialized valueFCC Create an ASCII string

DC.W FDB .WORD Allocate word of storage with initialized value

DC.L .LONG Allocate 32-bitlong word of storage with initialized value

DS.B RMB .BLKB Allocate byte of storage without initialization

DS.W .BLKW Allocate word of storage without initialization

DS.L .BLKL Allocate 32-bit word of storage without initialization

END END .END End of the source code

Embedded System Day 6

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