ELEN 468 Advanced Logic Design

ELEN 468 Lecture 27 1

ELEN 468Advanced Logic Design

Lecture 27Gate and Interconnect Optimization

ELEN 468 Lecture 27 2

MOS Transistor Technology

p substraten well

n n p p

source source

drain

gate gate

g

d

s

s

d

g

ELEN 468 Lecture 27 3

I-V Characteristics

Cutoff region Vgs < Vt Ids = 0

Linear region Vgs > Vt, 0 < Vds < Vgs-Vt Ids = B[(Vgs-Vt)Vds – V2

ds/2]Saturation region Vgs > Vt, 0 < Vgs-Vt < Vds Ids = B(Vgs-Vt)2/2

B = a W/L

g

d

s

Vds

Ids

ELEN 468 Lecture 27 4

Switching Characteristics

din ou

t

Vdd

Vds

Ids

tfall tdela

y

t

t

Vin

Vout

ELEN 468 Lecture 27 5

Falling and Rising Procedure

out

Vdd

out

Vdd

out

Vdd

out

Vdd

Input rising Input falling

Saturation

Saturation

Linear Linear

ELEN 468 Lecture 27 6

Falling Time

Falling time = t1 + t2 t1 = Vout drops from 0.9Vdd to Vdd-Vt

t2 = Vout drops from Vdd-Vt to 0.1Vdd

Falling time = rising time ≈ k C / (B Vdd)

Delay ≈ Falling time / 2

ELEN 468 Lecture 27 7

Cascaded Inverters

p: stage ratio sizei+1 = p ● sizei

Ri+1 = Ri / p

Ci+1 = p ● Ci

1 2 3 k

CL

ELEN 468 Lecture 27 8

Delay of Cascaded DriversDelay between stage i and i+1 Ri ● Ci+1 = p ● Ri ● Ci

Total delay from stage 1 to stage k pR1C1 + pR2C2 + … + pRk-1Ck-1 + RkCL

= pR1C1 + pR1C1 +…+ pR1C1 + R1CL / pk-1 = (k-1)pR1C1 + R1CL / pk-1

ELEN 468 Lecture 27 9

Minimum Delay Stage Ratio

A = (k-1)●R1●C1, B = R1●CL

t = A●p + B●p1-k

Let derivative t’ = 0 A + (1-k)●B●p-k = 0 pk = (k-1) ●B/A = CL / C1

p = [CL / C1]1/k

ELEN 468 Lecture 27 10

Optimal Number of Stages

CL = C1 pk

k = ln(CL/C1) / ln p

t = k●p●R1●C1 = (ln (CL/C1) / ln p – 1)●p●R1●C1

Delay t reaches minimum when p ≈ 2.72

ELEN 468 Lecture 27 11

Driver Sizing

ELEN 468 Lecture 27 12

Combine Buffering and Driver Sizing Directly?

Min delay

ELEN 468 Lecture 27 13

Impact To Previous Stage

Current stage

Previous stage

Small load

Large load

Large delay

Small delay

Cd

ELEN 468 Lecture 27 14

Input Load Penalty

Penalty = delay of min delay buffer chain driving Cd

Min buffer Cd

ELEN 468 Lecture 27 15

Driver Sizing Considering Impact to Previous Stage

Current stage

Previous stage

Small load

Large load

Large delay

Small delay

Cd

Large penalty

ELEN 468 Lecture 27 16

Driver Sizing in Van Ginneken’s Algorithm

Treat the buffer chain as a part of the net

Length = 0

Run van Ginneken’s algorithm with fixed driver and min sized buffer

ELEN 468 Lecture 27 17

Dependence on Steiner Tree

Timing critical

Timing critical

ELEN 468 Lecture 27 18

Rectilinear Steiner Minimum Tree

Given a signal net, find the best tree connecting themMinimize wire areaWire area implies Cost Capacitive load delay

Find Steiner minimum tree

Spanning tree

Steiner tree

Steiner node

ELEN 468 Lecture 27 19

Hanan Grid and Hanan Theorem

Hanan grid Draw vertical and

horizontal lines through all pins

Hanan Theorem There is always a

Steiner minimum tree on Hanan grid

ELEN 468 Lecture 27 20

Iterative 1-Steiner Algorithm

In each step, add one Steiner node such that the spanning tree is minimized

ELEN 468 Lecture 27 21

Area or Radius?

•Prim’s minimum spanning tree•Small total wire length•Long path to sinks

•Dijkstra’s shortest path tree•Short path to sinks•Large total wire length

Radius: the longest source-sink path length

ELEN 468 Lecture 27 22

Area Radius Trade-off

Find a solution in middle Not too much area Not too long radius

How to find an ideal point?

ELEN 468 Lecture 27 23

Prim’s and Dijkstra’s Algorithms

d(i,j): length of edge (i, j)p(i): length of path from source to iPrim: min d(i,j) Dijkstra: min d(i,j) + p(i)

d(i,j)

p(i)

i j

ELEN 468 Lecture 27 24

The Prim-Dijkstra Trade-off

Prim: add edge minimizing d(i,j)Dijkstra: add edge minimizing p(i) + d(i,j)Trade-off: c●p(i) + d(i,j) for 0 ≤ c ≤ 1When c=0, trade-off = PrimWhen c=1, trade-off = Dijkstra

ELEN 468 Lecture 27 25

Spanning Tree → Steiner Tree

ELEN 468 Lecture 27 26

Rectilinear Steiner Arborescence (RSA)

Every source-sink path is the shortestMinimum total wire length

ELEN 468 Lecture 27 27

RSA Heuristic

Assume all sinks in first quadrantInitially, each sink is a subtreeIteratively merge or grow subtrees toward the source

ELEN 468 Lecture 27 28

RSA Example

Merge

Grow

ELEN 468 Lecture 27 29

Merging Rule In RSA Heuristic

Iteratively Find subtrees rooted at p and q

maximizing min(xp, xq) + min (yp, yq)

Merge them to a new subtree rooted at r = (min(xp, xq), min (yp, yq))

ELEN 468 Lecture 27 30

RSA Diagonal Line Sweep

5

6

43

12

ELEN 468 Lecture 27 31

Buffered A-Tree