ELEN 468 Lecture 191 ELEN 468 Advanced Logic Design Lecture 19 VHDL.

ELEN 468 Lecture 19 1

ELEN 468Advanced Logic Design

Lecture 19VHDL


Introduction

VHDL VHSIC Hardware Description

Language

VHSIC Very High Speed Integrated Circuit


Example

-- eqcomp4 is a four bit equality comparator-- Entity declarationentity eqcomp4 is port ( a, b: in bit_vector( 3 downto 0 ); equals: out bit ); -- equal is active highend eqcomp4;

-- Architecture bodyarchitecture dataflow of eqcomp4 isbegin equals <= ‘1’ when ( a = b ) else ‘0’;end dataflow;

-- eqcomp4 is a four bit equality comparator-- Entity declarationentity eqcomp4 is port ( a, b: in bit_vector( 3 downto 0 ); equals: out bit ); -- equal is active highend eqcomp4;

-- Architecture bodyarchitecture dataflow of eqcomp4 isbegin equals <= ‘1’ when ( a = b ) else ‘0’;end dataflow;


Entity DeclarationsDescribe I/O and parameterized valuesPort declaration Name Mode

in out buffer: for internal feedback inout

Data type Boolean, bit, bit_vector, integer, std_logic …


Example of Entity Declaration

library ieee;

use ieee.std_logic_1164.all;

entity add4 is port (

a, b: in std_logic_vector( 3 downto 0 );

ci: in std_logic;

sum: out std_logic_vector( 3 downto 0 );

co: out std_logic );end add4;

library ieee;use ieee.std_logic_1164.all;

entity add4 is port (

a, b: in std_logic_vector( 3 downto 0 );

ci: in std_logic; sum: out std_logic_vector( 3 downto 0 );

co: out std_logic );

end add4;


Architecture Bodies

Always associated with an entity declarationDescription styles Behavioral Dataflow Structural


Behavioral Descriptionslibrary ieee;use ieee.std_logic_1164.all;entity eqcomp4 is port (

a, b: in std_logic_vector( 3 downto 0 );equals: out std_logic );

end eqcomp4;

architecture behavioral of eqcomp4 is begin

comp: process ( a, b ) -- sensitivity listbegin if a = b then equals <= ‘1’; else equals <= ‘0’; -- sequential assignment endifend process comp;

end behavioral;


Dataflow Descriptions

library ieee;use ieee.std_logic_1164.all;entity eqcomp4 is port (


end eqcomp4;

architecture dataflow of eqcomp4 isbegin equals <= ‘1’ when ( a = b ) else ‘0’;end dataflow;-- No process-- Concurrent assignment



end eqcomp4;

architecture dataflow of eqcomp4 isbegin equals <= ‘1’ when ( a = b ) else ‘0’;end dataflow;-- No process-- Concurrent assignment


Structural Descriptionslibrary ieee;use ieee.std_logic_1164.all;entity eqcomp4 is port (

a, b: in std_logic_vector( 3 downto 0 ); equals: out std_logic );

end eqcomp4;

use work.gatespkg.all;architecture struct of eqcomp4 is

signal x : std_logic_vector( 0 to 3);begin

u0: xnor2 port map ( a(0), b(0), x(0) ); -- component instantiationu1: xnor2 port map ( a(1), b(1), x(1) );u2: xnor2 port map ( a(2), b(2), x(2) );u3: xnor2 port map ( a(3), b(3), x(3) );u4: and4 port map ( x(0), x(1), x(2), x(3), equals );

end struct;


a, b: in std_logic_vector( 3 downto 0 ); equals: out std_logic );

end eqcomp4;

use work.gatespkg.all;architecture struct of eqcomp4 is

signal x : std_logic_vector( 0 to 3);begin

u0: xnor2 port map ( a(0), b(0), x(0) ); -- component instantiationu1: xnor2 port map ( a(1), b(1), x(1) );u2: xnor2 port map ( a(2), b(2), x(2) );u3: xnor2 port map ( a(3), b(3), x(3) );u4: and4 port map ( x(0), x(1), x(2), x(3), equals );

end struct;


Identifiers

Made up of alphabetic, numeric, and/or underscoreThe first character must be a letterThe last character cannot be an underscoreTwo underscores in succession are not allowedUppercase and lowercase are equivalent


Data Objects

ConstantsSignals Similar to “wire” in Verilog

Variables Only in processes and subprograms Usually applied as loop or tmp variable

Files

constant width: integer := 8;constant width: integer := 8;

signal count: bit_vector( 3 downto 0);

signal count: bit_vector( 3 downto 0);


Data Types

Scalar typesComposite types


Scalar Types

EnumerationIntegerFloatingPhysical


Enumeration Types type states is ( idle, waiting, read, write ); signal current_state: states;

type bit is ( ‘0’, ‘1’ ); type std_ulogic is ( ‘U’, -- Uninitialized

‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, -- Weak unknown ‘L’, -- Weak 0 ‘H’, -- Weak 1 ‘-’, -- Don’t care);

type states is ( idle, waiting, read, write ); signal current_state: states;

type bit is ( ‘0’, ‘1’ ); type std_ulogic is ( ‘U’, -- Uninitialized

‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, -- Weak unknown ‘L’, -- Weak 0 ‘H’, -- Weak 1 ‘-’, -- Don’t care);


Integer and Floating Types

VHDL supports Integers from –(231-1) to (231-1) Floating number from –1E38 to 1E38

variable a: integer range –255 to 255;

variable a: integer range –255 to 255;


Physical Types type time is range –2147483647 to

2147483647 units

fs;ps = 1000 fs;ns = 1000 ps;us = 1000 ns;ms = 1000 ns;sec = 1000 ms;min = 60 sec;hr = 60 min;

end units; -- time is a predefined type -- physical types are mostly for simulations

type time is range –2147483647 to 2147483647

unitsfs;ps = 1000 fs;ns = 1000 ps;us = 1000 ns;ms = 1000 ns;sec = 1000 ms;min = 60 sec;hr = 60 min;

end units; -- time is a predefined type -- physical types are mostly for simulations


Composite Types

ArrayRecord Has multiple elements of different

types

type bit_vector is array ( natural range <> ) of bit);

type bit_vector is array ( natural range <> ) of bit);


Two Dimensional Array

type table8x4 is array ( 0 to 7, 0 to 3 ) of bit;

constant exclusive_or: table8x4 := (“000_0”, “001_1”,“010_1”, “011_0”,“100_1”, “101_0”,“110_0”, “111_1” );

type table8x4 is array ( 0 to 7, 0 to 3 ) of bit;

constant exclusive_or: table8x4 := (“000_0”, “001_1”,“010_1”, “011_0”,“100_1”, “101_0”,“110_0”, “111_1” );


Strongly Typed

VHDL is a strongly typed languageIf a and b are integer variables, following assignment is not alloweda <= b + ‘1’;

since ‘1’ is a bit, unless ‘+’ is overloaded


Concurrent Statements

Lie outside of a processSignal assignment Concurrent Selective (with-select-when) Conditional (when-else) Generate


Concurrent Signal Assignment

entity my_design is port (mem_op, io_op:in bit;read, write: in bit;memr, memw: out bit;io_rd, io_wr: out bit );

end my_design;

architecture control of my_design is begin

memw <= mem_op and write;memr <= mem_op and read;io_wr <= io_op and write;io_rd <= io_op and read;

end control

entity my_design is port (mem_op, io_op:in bit;read, write: in bit;memr, memw: out bit;io_rd, io_wr: out bit );

end my_design;

architecture control of my_design is begin

memw <= mem_op and write;memr <= mem_op and read;io_wr <= io_op and write;io_rd <= io_op and read;

end control


Selective Signal Assignment

entity mux is port (a, b, c, d: in bit_vector( 3 downto 0 );s: in bit_vector( 1 downto 0 );x: out bit_vector( 3 downto 0 ) );

end mux;

architecture archmux of mux is begin with s select

x <= a when “00”,b when “01”,c when “10”,d when others;

end archmux;


end mux;

architecture archmux of mux is begin with s select

x <= a when “00”,b when “01”,c when “10”,d when others;

end archmux;


Conditional Signal Assignment


end mux;

architecture archmux of mux is begin

x <= a when ( s = “00” ) elseb when ( s = “01” ) elsec when ( s = “10” ) elsed;

end archmux;


end mux;

architecture archmux of mux is begin

x <= a when ( s = “00” ) elseb when ( s = “01” ) elsec when ( s = “10” ) elsed;

end archmux;


Component Instantiation and Generate Statement

architecture RTL of SHIFT iscomponent DFF port ( rst, clk, d: in bit; q: out bit );end component;signal T: bit_vector( 8 downto 0 );

beginT(8) <= SI;SO <= T(0);g0: for i in 7 downto 0 generate -- variable i is implicitly declared allbit: DFF port map ( rst=>rst, clk=>clk, d=>T(i+1), q=>T(i));end generate;

end RTL;

architecture RTL of SHIFT iscomponent DFF port ( rst, clk, d: in bit; q: out bit );end component;signal T: bit_vector( 8 downto 0 );

beginT(8) <= SI;SO <= T(0);g0: for i in 7 downto 0 generate -- variable i is implicitly declared allbit: DFF port map ( rst=>rst, clk=>clk, d=>T(i+1), q=>T(i));end generate;

end RTL;


Sequential Statements

In a process, function or procedure if-then-else when-else


if-then-else

… if ( condition1 ) then

x <= value1; elsif ( condition2 ) then

x <= value2; else

x <= value3; end if;

… if ( condition1 ) then

x <= value1; elsif ( condition2 ) then

x <= value2; else

x <= value3; end if;


case-when … architecture design of test_case is begin process ( address )

begin case address is

when “001” => decode <= X”11”; -- X indicates hexadecimal

when “111” => decode <= X”42”;when “010” => decode <= X”44”;when “101” => decode <= X”88”;when others => decode <= X”00”;

end case;end process;

end design;

… architecture design of test_case is begin process ( address )

begin case address is

when “001” => decode <= X”11”; -- X indicates hexadecimal

when “111” => decode <= X”42”;when “010” => decode <= X”44”;when “101” => decode <= X”88”;when others => decode <= X”00”;

end case;end process;

end design;


Loop

… p0: process ( A )

variable sum, i : integer; begin

sum := 0;loop1 : for i in 0 to 9 loop exit loop1 when A(i) > 20; next when A(i) > 10; sum := sum + A(i);end loop loop1

end process

… p0: process ( A )

variable sum, i : integer; begin

sum := 0;loop1 : for i in 0 to 9 loop exit loop1 when A(i) > 20; next when A(i) > 10; sum := sum + A(i);end loop loop1

end process


D Flip-Flop library ieee; use ieee.std_logic_1164.all; entity dff is port (

d, clk, rst: in std_logic;q: out std_logic );

end dff;

architecture behavior of dff is begin

process ( clk, rst ) begin if rst = ‘1’ then q <= ‘0’; elsif ( clk’event and clk = ‘1’ ) then q <= d; -- ‘event is an attribute end if;end process;

end behavior

library ieee; use ieee.std_logic_1164.all; entity dff is port (


end dff;


process ( clk, rst ) begin if rst = ‘1’ then q <= ‘0’; elsif ( clk’event and clk = ‘1’ ) then q <= d; -- ‘event is an attribute end if;end process;

end behavior


wait-until library ieee; use ieee.std_logic_1164.all; entity dff is port (


end dff;


process ( clk, rst ) begin if rst = ‘1’ then q <= ‘0’; else wait until ( clk = ‘1’ ) q <= d; end if;end process;

end behavior

library ieee; use ieee.std_logic_1164.all; entity dff is port (


end dff;


process ( clk, rst ) begin if rst = ‘1’ then q <= ‘0’; else wait until ( clk = ‘1’ ) q <= d; end if;end process;

end behavior


Functions

function bl2bit ( a: BOOLEAN ) return BIT isbegin if a then return ‘1’; else return ‘0’; end ifend bl2bit;

function bl2bit ( a: BOOLEAN ) return BIT isbegin if a then return ‘1’; else return ‘0’; end ifend bl2bit;


Using Functions entity full_add is port (

a, b, carry_in: in bit;sum, carry_out: out bit );

end full_add;

architecture fall_add of full_add isfunction majority( a, b, c: bit ) return bit isbegin return ( ( a and b ) or ( a and c ) or ( b and c ) );end majority;

beginsum <= a xor b xor carry_in;carry_out <= majority( a, b, carry_in );

end;

entity full_add is port (a, b, carry_in: in bit;sum, carry_out: out bit );

end full_add;

architecture fall_add of full_add isfunction majority( a, b, c: bit ) return bit isbegin return ( ( a and b ) or ( a and c ) or ( b and c ) );end majority;

beginsum <= a xor b xor carry_in;carry_out <= majority( a, b, carry_in );

end;


Procedures

procedure dff ( signal d: bit_vector; signal clk, rst: bit; signal q: out bit_vector ) is

beginif rst = ‘1’ then q <= ( others => ‘0’ );elsif clk’event and clk = ‘1’ then q <= d;end if;

end procedure;

procedure dff ( signal d: bit_vector; signal clk, rst: bit; signal q: out bit_vector ) is

beginif rst = ‘1’ then q <= ( others => ‘0’ );elsif clk’event and clk = ‘1’ then q <= d;end if;

end procedure;


PackagesSimilar to libraryA design unit whose type, component, function and other declarations can be visible to outsideConsists of Package declaration Package body (optional)

Made visible through “use”use library_name.package_name.item;use work.std_arith.all;

Some vendors provide a default work library


Declare Types in Package

package STANDARD istype BOOLEAN is ( FALSE, TRUE );type BIT is ( ‘0’, ‘1’ );type INTEGER is range -2147483648 to +2147483647;…

end STANDARD;

package STANDARD istype BOOLEAN is ( FALSE, TRUE );type BIT is ( ‘0’, ‘1’ );type INTEGER is range -2147483648 to +2147483647;…

end STANDARD;


Define Procedure in Package

package myflop is procedure dff ( signal d: bit_vector;

signal clk, rst: bit; signal q: out bit_vector );

end myflop;

package body myflop is procedure dff ( signal d: bit_vector;

signal clk, rst: bit; signal q: out bit_vector )

is begin

if rst = ‘1’ then q <= ( others => ‘0’ ); elsif clk’event and clk = ‘1’ then q <= d; end if;

end procedure; end myflop;

package myflop is procedure dff ( signal d: bit_vector;

signal clk, rst: bit; signal q: out bit_vector );

end myflop;

package body myflop is procedure dff ( signal d: bit_vector;

signal clk, rst: bit; signal q: out bit_vector )

is begin

if rst = ‘1’ then q <= ( others => ‘0’ ); elsif clk’event and clk = ‘1’ then q <= d; end if;

end procedure; end myflop;


Using Procedure

entity flop8 is port (clk, rst: in bit;data_in: in bit_vector( 7 downto 0 );data: out bit_vector( 7 downto 0 ) );

end flop8;

use work.myflop.all; architecture archflop8 of flop8 is begin

dff( data_in, clk, rst, data ); end archflop8;

entity flop8 is port (clk, rst: in bit;data_in: in bit_vector( 7 downto 0 );data: out bit_vector( 7 downto 0 ) );

end flop8;

use work.myflop.all; architecture archflop8 of flop8 is begin

dff( data_in, clk, rst, data ); end archflop8;


Generics entity dff is

generic ( size: integer := 2 ) port ( clk, rst: in bit;

d: in bit_vector( size-1 downto 0 ); q: out bit_vector( size-1 downto 0 ) );

end dff;

architecture behavior of dff is … end behavior

… u1: dff generic map(8) port map( myclk, myrst, data, output ); …

entity dff isgeneric ( size: integer := 2 )

port ( clk, rst: in bit; d: in bit_vector( size-1 downto 0 ); q: out bit_vector( size-1 downto 0 ) );

end dff;

architecture behavior of dff is … end behavior

… u1: dff generic map(8) port map( myclk, myrst, data, output ); …

ELEN 468 Lecture 191 ELEN 468 Advanced Logic Design Lecture 19 VHDL.

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