Elec4602 Notes

ELEC4602 NotesMatthew Davis

Semester 2, 2014The University of New South Wales

Abstract

These summary notes are for Microelectronics Design and Technology (ELEC4602) insemester 2, 2014. If you find any mistakes, email [email protected]. More notescan be found at elsoc.net/notes.php. Note that table numbers, figure numbers, page numbersand the table of contents are all clickable hyperlinks.

Contents1 Manufacturing 4

2 Symbols 4

3 Transistor Equations 43.1 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53.2 Small Signal Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

4 Noise 64.1 Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64.2 MOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

5 Amplifiers 75.1 Common Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75.2 Common Drain Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75.3 Common Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85.4 Differential Pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

6 Op Amps 96.1 Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106.2 Output Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106.3 Input Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

6.3.1 Minimum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106.3.2 Maximum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

6.4 Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116.5 Transistor Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116.6 Compensation Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126.7 Small Signal Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126.8 Compensation Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7 Miller Effect 15

8 Samplers 158.1 Sampling Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168.2 Charge Injection and Dummy Switches . . . . . . . . . . . . . . . . . . . . . . . . . 168.3 Offset Cancellation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

1

9 Comparators 189.1 Multi-Stage comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199.2 Latching comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

10 D/A and A/D Converters 2110.1 Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2110.2 Digital To Analog Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

10.2.1 Multiplexed Resistor String . . . . . . . . . . . . . . . . . . . . . . . . . . . 2110.2.2 Binary Weighted Resistor Ladder . . . . . . . . . . . . . . . . . . . . . . . . 2110.2.3 Binary Weighted Capacitor Ladder . . . . . . . . . . . . . . . . . . . . . . . 22

10.3 Analog To Digital Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2310.3.1 Successive Approximation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2310.3.2 Algorithmic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2410.3.3 Pipelined Algorithmic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

11 Digital Logic 2611.1 Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2611.2 Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2611.3 Static CMOS Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

11.3.1 Propagation Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2811.3.2 Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

11.4 Transmission Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

12 Flip Flops and Latches 3112.1 Transmission Gate Flip Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3112.2 Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3112.3 Dynamic Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

13 Memory Elements 3213.1 Overall Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3213.2 6 Transistor Static Memory Element . . . . . . . . . . . . . . . . . . . . . . . . . . 3313.3 Dynamic Memory Element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

List of Figures1 Capacitances in an NMOS transistor . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Small signal model of a transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 T-model of MOS transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Noise in a MOS transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Common Source Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Common Source Amplifier Small Signal Model . . . . . . . . . . . . . . . . . . . . 87 Common Drain Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Common drain amplifier equivilant circuit . . . . . . . . . . . . . . . . . . . . . . . 99 Common gate amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 910 Differential Pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1011 Operational Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1112 Approximate op amp bode plot (without zero) . . . . . . . . . . . . . . . . . . . . 1313 Small signal model of an op amp (without RC) . . . . . . . . . . . . . . . . . . . . 1314 Op amp bode plot including zero, before adding RC . . . . . . . . . . . . . . . . . 1415 The Miller Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1516 Basic sampling circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1617 Sampling jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1618 Dummy Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1719 Sampling with offset cancellation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1820 Basic comparator with offset cancelling . . . . . . . . . . . . . . . . . . . . . . . . . 18

2

21 A multi-stage comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1922 Simplified latching comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2023 Full latching comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2124 ADC/DAC Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2225 Multiplexed Resistor String DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2326 Resistor binary weighted ladder ADC . . . . . . . . . . . . . . . . . . . . . . . . . 2327 Capacitor binary weighted ladder ADC . . . . . . . . . . . . . . . . . . . . . . . . 2428 Successive Approximation ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2529 Single stage algorithmic ADC Schematic . . . . . . . . . . . . . . . . . . . . . . . . 2530 Single stage algorithmic ADC operation . . . . . . . . . . . . . . . . . . . . . . . . 2631 Pipelined algorithmic ADC (3 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2732 Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2833 Inverter transfer function and crowbar current . . . . . . . . . . . . . . . . . . . . . 2934 String of buffers of increasing size . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2935 Simple NAND gate and its propagation delay . . . . . . . . . . . . . . . . . . . . . 3036 Transmission gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3037 Flip flop implemented using transmission gates . . . . . . . . . . . . . . . . . . . . 3138 Dynamic Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3239 Overall structure for most memory . . . . . . . . . . . . . . . . . . . . . . . . . . . 3240 6 transistor static memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

List of Tables1 The 2 Types of MOS transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3

1 Manufacturing

Annealing: Removes cracks by heating then slowly cooling.

Sputtering: Heat aluminium until it splutters metal onto the chip.

2 Symbols

Type Symbols Normal Location Inside n-well? Select

PMOS G

D

S

G

D

S

BG

S

D

top of circuit yes P-select

NMOS G

D

S

G

D

S

BG

D

S

bottom of circuit no N-select

Table 1: The 2 Types of MOS transistors

The most common symbols are shown in Table 1.

To remember which way around the source and drain are, remember that for NMOS (the normalone), VDD is the top rail, so the drain is at the top. PMOS is less intuitive than NMOS, so theopposite is true, and the drain is connected furthest from VDD.

To remember which way around the arrows go, remember that the arrows always point to a Ndoped region (this is true of BJTs too).

3 Transistor Equations

These equations are all in techpar.pdf.

iD =1

2µCOX

W

L(VGS − Vth)

2

(1 +

kλLvDS

)︸ ︷︷ ︸

Channel length modulation

Saturation drain current

iD = µCOXW

L

((vGS − Vth)vDS −

1

2vDS

2

)(1 +

kλLvDS

)︸ ︷︷ ︸

Channel length modulation

Triode drain current (1)

Vth = Vth0 + γ(√|2φF − vBS | −

√|2φF |

)︸ ︷︷ ︸

Bulk-Source Effect

Threshold voltage

Where:

• VEFF = VGS − Vth is the effective voltage

• µ is electron mobility

• γ is the bulk effect parameter

4

• COX is the gate capacitance per unit area

• Vth is the threshold voltage

• Vth0 is the zero bias threshold voltage (threshold voltage with no bulk-source effect)

• kλ = Lλ

3.1 Modes

Saturation mode means the transistor is being used as an analog amplifier

0 < vDS < VEFF = vGS − Vth

Triode mode means the transistor is being used as digital switch

vDS > VEFF = vGS − Vth

3.2 Small Signal Model

The parasitic capacitances in an NMOS are shown in Figure 1. They look the same in a PMOS.

n+

D

CDB

n+

S

CSB

CGS CGD

B

G

Figure 1: Capacitances in an NMOS transistor

The small signal model is shown in Figure 2.

G

CGS

CSB

CGD

gmb · VBS

S

Gm · Vgs RDS

CDB

B

D

Figure 2: Small signal model of a transistor

5

The values in the small signal model are given by:

gm =∂ID∂VGS

= µCOXW

L(VGS − Vth)

1

rDS=

∂ID∂VDS

=kλIDL

(2)

gmb =∂Id∂VBS

If the bulk terminal is equal to the source terminal, clearly CBS and CDB are shorted, so theyhave no effect, so there is no bulk effect, and the left current source can be ignored.

The T-model is another model for MOS transistors which is exactly equivalent to the normalmodel. It is shown in Figure 3. Note that no current enters the gate, because the current throughthe Is current source is by design equal to the current through the 1

gmresistor.

1gm

Is S

rds

D

Is

G

Figure 3: T-model of MOS transistor

4 Noise

4.1 Resistors

Noise in a resistor is given byV 2nR

= 4kTR (V2Hz−1)

4.2 MOS

Figure 4 shows the sources of noise in a MOS transistor.

D

S

I2nd(f)

V 2ng(f)

G

Figure 4: Noise in a MOS transistor

The noises are given by:

I2nd(f) = 4kT × 2

3

1

gm(White Noise)

V 2ng(f) =

kfWLCOXf

Pink Noise

6

To refer the gate noise to the output, it needs to be multiplied by gm2. To refer the drain noise tothe input, it needs to be divided by gm2.

Therefore the combined output refered noise of a MOS transistor is:

I2ntotal(f) =

kfgm2

WLCOXf+ 4kT × 2

3

1

gm

5 Amplifiers

5.1 Common Source

The most basic common source amplifier has been shown in Figure 5a. Where the output needsbe a voltage (instead of a current), the circuit in Figure 5b can be used instead. Because Vin isfixed, the PMOS is effectively a resistor, so the circuit is the same as 5a.

Note that the sources are tied to VDD and ground, which is why it’s a common source ampli-fier.

The small signal model of the common course amplifier is shown in Figure 6 on the next page. Ithas the following properties:

rin =∞rout = rds ‖ RL

Av =VoutVin

= −gm (rds ‖ RL) = −gmrout

Vin

D

S

RL

(a) Passive Load (current output)

Vin

D

S

Vin

D

S

Vout

VDD

Ibias

(b) Active Load (voltage output)

Figure 5: Common Source Amplifiers

5.2 Common Drain Amplifier

The common drain or source follower amplifier is shown in Figure 7 on the following page.

To analyse this circuit, we will use the T-model shown back in Figure 3 on the previous page,which results in the equivalent circuit shown in Figure 8 on page 9.

7

Vout

RLrdsgmVinVin

Figure 6: Common Source Amplifier Small Signal Model

Vin

D

S

RL

Vout

(a) Passive Load (current output)

Vin

D

SD

S

Vout

Ibias

Vbias

(b) Active Load (voltage output)

Figure 7: Common Drain Amplifiers

The common drain amplifier therefore has the following properties:

Av =rds ‖ rdsb

rds ‖ rdsB + 1gm

rout = rdsB ‖ rds ‖1

gm

rin =∞

5.3 Common Gate

The common gate (cascode) amplifier is shown in Figure 9 on the next page.

The common gate amplifier doesn’t amplify current or voltage. It simply provides a high inputimpedance for the source, and a low output impedance for the load.

The common gate amplifier has the following properties:

A =ioutiin

= 1

rin ≈rds +RLgmrds

rout = rds +Ringmrds

5.4 Differential Pair

A differential pair can be seen in Figure 10 on page 10.

In a small signal context, each NMOS draws a current which is proportional to the respective inputvoltage. The current mirror up top produces a current in the right branch which matches that in

8

1gm

Is Vout

rdsB

Is

Vin

rds

Figure 8: Common drain amplifier equivilant circuit

RL

iout

Vbias

Iin Rin

iin

Figure 9: Common gate amplifier

the left branch. Current addition at the output node then means that the output current is thedifference between the the two drain currents, which is proportional to the difference between theinput voltages.

rin =∞rout = rds1 ‖ rds2iout = io1 − io2 = gm(Vin1 − Vin2)

6 Op Amps

The schematic of a basic 2 stage op amp has been shown in Figure 11 on page 11.

9

Vin1 Vin2

io1

Ibias

io1

io1 − io2io2

Figure 10: Differential Pair

6.1 Gain

rout1 = rds2 ‖ rds5 Stage 1 output resistancerout2 = rds3 ‖ rds8 Stage 2 output resistanceAv1 = −gm5rout1 Stage 1 DC gainAv2 = −gm8rout2 Stage 2 DC gainA0 = Av1Av2 = gm5 · rout1 · gm8 · rout2 Overall DC gain

6.2 Output Voltage Range

In order to operate correctly, each transistor needs to be in saturation. Therefore the outputvoltage can swing to within a threshold voltage of the supply rail.

0 + Vth3 ≤ Vout ≤ VDD − Veff8

Note that Veff6 = Veff7 = Veff8 = VthP+ (VDD − Vbias).

6.3 Input Voltage Range

The op-amp common mode input range is equal to the common mode input range of the differentialpair.

6.3.1 Minimum

If the input voltage is too low VSD4,5� VSG4,5

− VthP, so M4 and M5 move into triode mode. To

avoid that happening we need:

VSD4,5≥ VSG4,5

− VthP

−VD4,5> −VG4,5

− VthP

VG4,5> VD4,5

− VthP

10

Ibias

Vbias

Vout

RCCC

V+V−

+

−

> |Veff8|

+

−

> |Veff3|

+

−

> |Veff7|

+

−

VthN?

rout1

rout2

M1 M2 M3

M4 M5

M6 M7 M8

Figure 11: Operational Amplifier

For M1 and M2 to remain in saturation, we need VD1,2> VthN

, so VD4,5> VthN

VG4,5 > VthN− VthP

VCMmin = VthN− VthP

6.3.2 Maximum

If the input voltages are too high, M4 and M5 will turn off.

6.4 Slew Rate

The drain of M5 remains at an approximately constant voltage. Therefore, if the output voltagechanges very quickly, most of that voltage change will need to also happen across CC . (We’reneglecting RC for now.) The maximum rate of change of the voltage across CC is proportional tocurrent through M7 (Ibias). So

max

∣∣∣∣dVoutdt

∣∣∣∣ =IbiasCC

6.5 Transistor Sizing

The op amp in Figure 11 has 7 transistors, so there are 14 parameters to choose. Here is one wayof deciding the dimensions of each transistor:

1. Work out how much power you have available, and hence the available current. You alsoneed to consider

noise rejection: larger currents means less noise

speed: larger currents means faster circuits

matching: larger currents means better matching

2. Choose your effective voltage

11

3. Choose L (same for all transistors). Shorter means faster, but reduces gain. Choose at least2 times the minimum length.

4. Choose your widths based on the above.

5. Double check that all saturation currents ‘agree’. If this isn’t the case, one of the transistorswill go out of saturation.

6.6 Compensation Capacitor

The op amp shown in Figure 11 on the previous page has 2 stages, and therefore 2 poles. Therefore,if we want to connect this op amp with feedback (which we always do), the system would bemarginally stable, which is not good enough. That’s why we introduce the compensation capacitor(CC). It adds a 3rd pole, which is the dominant pole, thereby increasing the phase margin.

For now we’ll ignore RC . It is explained in Section 6.8 on page 14.

Because of the Miller Effect1, CC appears much larger to the node between the stages. It is ‘seen’as CC times the gain of the second stage. So Ceq = CC · gm3 · rout2.

The dominant pole is given by:

ω1 ≈1

rout1 · Ceq=

1

rout1 · gm3 · rout2 · CC

Therefore increasing CC will decrease the frequency of the dominant pole, which will increase thephase margin and increase stability.

The angular gain bandwidth product is given by:

ωta ≈ A0 · ω1 =gm5

CC

The transfer function therefore looks like Figure 12 on the following page. Neglecting non-dominantpoles because we’ll only use the op amp within it’s bandwidth, the transfer function can be ap-proximated by:

A(s) =A0

1 + sω1

≈ A0sω1

=A0 · ω1

s(3)

Note that the DC gain becomes infinite with this approximation. This corresponds to the dashedline in Figure 11 on the previous page.

Equation 3 was an approximation of the transfer function of the op amp. A more accurate modelwould include the 2nd pole.

A(s) =ωta

s(

1 + sω2

) Where ωta = A0 · ω1

It can be shown that:Phase Margin = 90◦ − tan−1

ωtω2

Where ωt is the point such that |A(ωt)| = 1. For ω2 � ωta we can approximate ωt ≈ ωta.

6.7 Small Signal Model

The small signal model for the op amp in Figure 11 on the previous page is shown in Figure 13 onthe following page.

1The Miller effect is described in Section 7 on page 15.

12

ω

|A(s)|

A0

ω1 ω2

gm5

CC

ω

∠A(s)

−90◦

−180◦

Phase Margin

Figure 12: Approximate op amp bode plot (without zero)

The gain of the first stage is really gm5 · V+ − gm4 · V−, but that is equal to gm5Vin since gm5 =gm4.

At high frequencies CC effectively becomes a short circuit, so Figure 13 becomes a 2 node circuit.The voltage across the 2nd stage current source becomes Vo1, so it acts as a resistor of value 1

gm.

We know that gmrds � 1, so we can assume 1gm3� rout1 + rout2.Therefore the 2nd pole can be

approximated as:

ω2 ≈1

RC=

gm3

Cout1 + Cout2(4)

This circuit has a zero. To work out it’s value, set Vout = 0, so the current through rout2 and CD2

+

−

Vin

CCVo1

Vout

gm5Vin rout1 Cout1 gm3Vo1 rout2 CD2

Figure 13: Small signal model of an op amp (without RC)

13

is zero. Therefore all the current through CC goes through the gm3Vo1 current source.

gm3Vo1 =Vo11

s0CC

s0 =gm3

CC(5)

6.8 Compensation Resistor

From equation 5 we see that by putting in the compensation capacitor, we have introduced a zeroin the right half plane (there was previously a zero at infinity).

Looking back at equations 5 and 4 on the preceding page we can figure out where the zero liescompared to ω2. Cout1 and Cout2 are just parasitic capacitances, and so they are far smaller thanCC . Therefore the zero lies to the left of ω2. Therefore the bode plot in Figure 12 on the previouspage is wrong. It should look like Figure 14, and the transfer function should look like:

H(s) =

A0

(1− s

gm3CC

)(

1 + sω1

)(1 + s

ω2

)

ω

|A(s)|

A0

ωtaω1

−45◦

ωz

−135◦

ω2

−225◦

ω

∠A(s)

−90◦

−180◦

−270◦

Figure 14: Op amp bode plot including zero, before adding RC

Clearly this is unstable, since the phase angle when the gain is 0dBis almost -270◦. This is definitelyunstable.

If a resistor RC is added in series with CC , the zero moves. Looking back to the small signal modelin Figure 13 on the previous page and mentally adding a resistor in series with CC , if we then

14

follow the same working that we used for equation 5 on the preceding page we get:

gm3Vo1 =Vo1

1s0CC

+RC

s0 =1

1gm3−RC

(6)

From equation 6 we see that by varying RC from zero (no resistor) to 1gm3

, we can move the zerofurther from the origin, past ω2 to ∞. So we can make the transfer function actually look likeFigure 12 on page 13.

If we choose RC > 1gm3

then the zero actually moves into the left half plane (s0 < 0). So thetransfer function looks like Figure 14 on the previous page, except the phase contribution from thezero is positive.

7 Miller Effect

Figure 15 shows the Miller Effect.

When a capacitor is placed across an element with large gain, a small change in the input voltageresults at a large change in voltage at the output. Therefore a small change in input voltage resultsin a large change in voltage across the capacitor, which results in a large amount of charge passingthrough the capacitor. Capacitance is measured in units of charge per volt, so the input ‘sees’ alarger capacitance than just C, it ‘sees’ C(1 + |(|A)) ≈ AC

Similarly the output ‘sees’ a slightly smaller value. The ratio of output voltage to input voltageis A−1, so the output ‘sees’ C

(1 + 1

|A|

)≈ C. Alternatively, a change in output voltage results

in a small change in input voltage, so the output ’sees’ a capacitor of value about C, tied toground.

Vin

C

Vout−A

(a) Capacitor across element with gain

Vin Vout

C(1−A) C(1− 1

A

)−A

(b) Capacitances ‘seen’ by input and output

Figure 15: The Miller Effect

8 Samplers

A basic sampling circuit can be seen in Figure 16 on the next page.

When the sampling signal (φs) goes high, the NMOS acts like a closed switch, so CH charges upto Vin. Then when the sampling signal goes low, the NMOS acts like an open switch, so Vout isjust the voltage across the capacitor, which is the value of Vin at the last falling edge of φs.

15

Vin

φs

Vout

CH

Figure 16: Basic sampling circuit

8.1 Sampling Jitter

The device is sampling the input as long as the gate voltage is at least one threshold voltage higherthan the input voltage. φs > Vin + VthN

. This is quite bad because φs has a finite fall time, sothe point at which the transistor turns off depends on the input. This can be seen more clearly inFigure 17.

t

V

Vin

VthN

φs

error

VthN

error

Figure 17: Sampling jitter

When the input voltage is high, it is sampled earlier than we intend2, and when the input voltageis low it is sampled later than the ideal spot. This error is called sampling jitter. The way tominimize this error is to minimize the fall time of the selection signal.

8.2 Charge Injection and Dummy Switches

When the transistor in Figure 16 is on, the total charge sitting in the channel is3

Qch = −Cch · VEFF = −W · L · COX · (VDD − Vin − VthN) (7)

The channel charge in an NMOS is negative.

When the transistor is turned off, that charge has to go somewhere. The transistor needs to beturned off very quickly (for reasons discussed in Section 8.1). So half the charge goes out the drain,

2Assuming we intend to sample when φs = 0V.3The magic 2

3factor which appears in techpar.pdf doesn’t appear here because we’re in the triode (switch) region.

16

and half goes out the source. When this charge passes to ground through CH , the voltage acrossCH drops. This introduces an error, equal to

∆Vout = −12Qch

CH.

Additionally, the gate-drain overlap capacitance introduces a similar error.

The speed of the sampling circuit is limited by τ = RonCH . If we multiply the speed and theaccuracy together we get:

1

|∆Vout|τ=

2CHQch

· 1

RonCH

Subbing in equation 7:

(8)

=2CH

W · L · COX · VEFF· 1

1µCOX

WL VEFF

CH

=2µ

L2(9)

Equation 9 tells us that we really want to minimise L in order to get a good sampler. It alsotells us that we can’t have both good speed and good accuracy. There is a trade off between thetwo.

An effective way to reduce charge injection errors is to add a dummy switch. Figure 18 shows asampling circuit with a dummy switch.

Vin

φs φSD

Vout

CH

(a) Circuit

t

φsVDD

t

φSDVDD

(b) Signal timing

Figure 18: Dummy Switch

The timing of the sampling signals is important. Figure 18b shows that the dummy switch signal(φDS) is an inverted and delayed version of the main signal (φs).

When φs goes low, charge is injected through CH into ground, increasing the voltage across CH .Then after a short delay, φSD goes high, so the dummy switch sucks up some charge into it’schannel, all4 from ground through CH , which decreases the voltage across CH . If the dummyswitch is half the width of the main switch, and the same length, the charges will approximatelycancel out, so the charge injection error will be drastically reduced.

8.3 Offset Cancellation

Figure 19 on the following page shows an example of a sampling circuit with offset cancella-tion.

4The main switch is now open, so no charge can pass through it.

17

−

+

Vout

0V

VOS

−

+

Vin − VOS

Vin

φ1 φ2

φ1

(a) Circuit

t

φs

VDD

t

φ2

VDD

(b) Signal timing

Figure 19: Sampling with offset cancellation

When φ1 is high, the op amp is configured as a unity gain buffer. Both input terminals are equal,so V− = 0V, so the bottom of the capacitor is at VOS (the offset voltage). Therefore the voltageacross the capacitor is Vin − VOS .

When φ1 is low and φ2 is high, the bottom of the capacitor is connected only to the negativeinput of the terminal, which is of infinite impedance. Therefore no current can flow through thecapacitor, so the voltage across it remains Vin−VOS . The top right NMOS is on, so the voltage atthe output equals the voltage at the top of the capacitor, which equals (Vin − VOS) + VOS = Vin.Hence, the offset voltage has not introduced an error.

9 Comparators

A basic offset-cancelling comparator can be seen in Figure 20.

−

+

VoutVOS

φ1

+−VOS

φ1

φ2

Vin

(a) Circuit

t

φs

VDD

t

φ2

VDD

(b) Signal timing

Figure 20: Basic comparator with offset cancelling

When φ1 is high, the left end of the capacitor is shorted to ground, so the capacitor is charged toVOS .

When φ1 is low and φ2 is high, no current can pass through the capacitor, since the right end isonly connected to the negative input of the op amp (which has infinite impedance). Therefore thevoltage across the capacitor remains VOS . The difference in voltage between the op amp input

18

terminals5 (including offset voltage) then becomes (Vin + VOS)− VOS . Assuming infinite gain, theoutput is high iff Vin > 0, which is not dependant on offset voltage.

9.1 Multi-Stage comparator

A multi-stage comparator can be seen in Figure 21.

φ1A1 φ1A2 φ1A3

Vout

φ1

φ2

Vin

(a) Circuit

t

φ1A1

t

φ2

t

φ1A3t

φ1A2

t

φ1

reset use

(b) Signal timing

Vg

Vd

Vg = Vd

Vtipping

(c) Per stage transfer function

Figure 21: A multi-stage comparator

Each of the 3 stages is a common source amplifier. When a gate voltage is high, most of the biasingcurrent passes through the dependant current source in the small signal model (Figure 2 on 5), sonot much passes through rds, so the drain voltage is low. When the gate voltage is low, most of thebiasing current passes through rds, so the drain voltage is high. Hence, each stage is an inverterwith a transfer function looking like Figure 21c.

During the reset phase, the gate of each NMOS is tied to the drain. This fixes each stage at theintersection of the dotted line Vg = Vd and the transfer function in Figure 21c (Vg = Vd = Vtipping).This is roughly the point of maximum gain. We will call this gain −A. The leftmost capacitor ischarged so that the voltage across it equals Vtipping. Similarly, the other two capacitors are chargedsuch that the input to the respective stage is also Vtipping. In this way all stages are set up to beat their points of maximum gain. This eliminates offset errors, and maximises speed.

5Because there is no feedback when φ1 is low, the input terminals aren’t at the same voltage.

19

Opening the switches between the gate and drain on each stage will cause an error due to chargeinjection into the capacitor to the left of that stage. This error will then be amplified by A. Thereason that there is a delay between φ1A1, φ1A2 and φ1A3 is so that each stage exists reset modeafter the previous. This ensures that the errors from charge injection in the previous stages areeliminated, since the voltage across the capacitor adapts to the error in such a way that the gatevoltage is still Vtipping. This eliminates each charge injection error, except the last.

The error due to charge injection in the last stage is amplified by A before reaching the output.In contrast, the input signal is amplified by AN before reaching the last stage (where N is thenumber of stages), so this error is negligible.

When φ2 goes high, the gate voltage on stage 1 becomes Vin +Vtipping. This means that a slightlypositive or slightly negative value of Vin will result in a very low or very high drain voltage Vd1.The gate voltage in stage 2 will therefore be Vd1 +Vtripping, which will result in an extremely highor extremely low drain voltage Vd2, and so on for the 3rd stage.

In this way, Vin is amplified by a factor of AN , with negligible errors due to offset and chargeinjection.

9.2 Latching comparator

Latching comparators use positive feedback to achieve infinite gain.

A very simple version is shown in Figure 22. Each inverter has a transfer function similar to6Figure 21c on the preceding page.

If, for example, the left node was at a slightly higher voltage than the right, the bottom inverterwould amplify that different, which would drive down the voltage of the right node. Then the topinverter would drive up the voltage on the left node even further, and so on.

Figure 22: Simplified latching comparator

This circuit has infinite gain. It could correctly compare any two arbitrarily close voltages (neglect-ing noise). However it has no inputs and no reset mechanism. This circuit is also very fast, becausethe poles are in the right half plane, so the voltage grows exponentially over time (V (t) ∝ et/τ ),instead of decaying over time (V (t) ∝ e−t/τ ).

A full latching comparator is shown in Figure 23 on the next page.

If we turn on the redNMOS and ignore (turn off) the other coloured components, Figure 23 on thefollowing page is the same as Figure 22.

The redpart is the reset sub-circuit. When the reset signal is high, the redNMOS turns off, therebybreaking the feedback. The redPMOS turns on, thereby shorting the drains of the black PMOSsto VDD. The drains of the black NMOSs fall back to ground, because nothing is keeping themup.

The bluepart is the circuit which inputs the voltages to be compared. When the reset input goeslow the whole circuit comes out of the reset mode, into the comparison mode. If one of the inputsis higher than the other, the circuit will become unstable.

6Replace Vg with Vin and Vd with Vout.

20

reset

Vina

reset

Vinb

Figure 23: Full latching comparator

Vinaand Vinb

could be the outputs of a pre-amp.

10 D/A and A/D Converters

Throughout this section, N will refer to the number of bits.

10.1 Errors

Figure 24 on the following page shows the most common types of errors in analog to digitalconverters (ADCs) and digital to analog converters (DACs).

essential non-linearity (ENL) is measured using the maximum deviation from the ideal output(in either direction).

differential non-linearity (DNL) is measured using the maximum deviation in the differencebetween 2 outputs (for a DAC) or between 2 inputs which result in different outputs (for aADC).

Offset errors can be easily calibrated out. Gain errors are normally not an issue. DNL and ENLare an issue because they cause a distortion which is very hard to remove.

10.2 Digital To Analog Converters

10.2.1 Multiplexed Resistor String

Figure 25 on page 23 shows a DAC which works by multiplexing the nodes of a voltage divider.If an actual analog multiplexer is used instead of 2N switches, there are O(log2(N)) switches, Nsignals and 2N − 1 resistors. The downside of this structure is that it requires a lot of resistors.The other downside is that it consumes a lot of static power, compared to capacitor structures (seeSection 10.2.3 on the following page.)

10.2.2 Binary Weighted Resistor Ladder

Figure 26 on page 23 shows a binary weighted resistor ladder ADC.

21

input

outputideal

Gain Error

(a) Gain Error

input

outputideal

Offset Error

(b) Offset Error

input

outputideal

EssentialNon-Linearity

(c) Essential Non-Linearity

input

outputIdeal

DNL

DifferentialNon-Linearity

(d) Differential Non-Linearity

Figure 24: ADC/DAC Errors

Each bit of information controls one switch.

This should be analysed using superposition.

For each bit which is a 1, the respective switch is closed and a current passes through the respectiveresistor, into the feedback resistor, which creates a voltage at the output. Since the voltage at eitherend of the resistor is fixed (when the switch is closed), it is essentially just a current source. Thecurrent is inversely proportional to the resistance, which is 2N−iR (where 0 is the most significantbit (MSB) and N − 1 is the least significant bit (LSB)). Hence, the voltage at the output isproportional to the sum of connected current sources, which is proportional to the sum of 2 to thepower of the bit’s significance.

The advantages of this system are that it only requires O(log2(N)) resistors and switches. Itconsumes less static power than the resistor string.

Because the value of a resistor is proportional to it’s area, the binary weighted resistor ladderrequires approximately the same amount of area as the resistor string. (O(2N )).

Note that this configuration is inverting, which is why the resistors are tied to negative Vref .

10.2.3 Binary Weighted Capacitor Ladder

Figure 27 on page 24 shows a binary weighted capacitor ladder ADC.

It is similar to the binary weighted resistor ladder, but it consumes no static power (aside fromthe op amp), since capacitors block DC.

The downside is that it is discrete time, since it requires a clock to reset it. During the reset phase,

22

Vout

D0

R

−

+

VLSB

D1

R

−

+

VLSB

D2

R

−

+

VLSB

D3

Vref

Figure 25: Multiplexed Resistor String DAC

−

+

Vout

−Vref

D0

8R

LSB

D1

4R

D2

2R

D3

R

MSB

Figure 26: Resistor binary weighted ladder ADC

the feedback capacitor7 is shorted, so that it fully discharges to 0V.

After the reset phase, each switch turns on if it corresponds to a 1. That means the respectivecapacitor charges up until Vref is across it. To do this, charge passes through the respectivecapacitor, which must pass through the feedback capacitor. The more significant bits correspondto larger capacitors which require more charge to reach Vref . This charge must pass throughthe feedback capacitor, which increases it’s voltage. In this way, after everything has settled, thevoltage at the output equals the voltage across the feedback capacitor, which is proportional tothe sum of 2 to the power of each bit which is a 1.

10.3 Analog To Digital Converters

10.3.1 Successive Approximation

Successive approximation ADCs use a binary search to find the highest value which is less thanor equal to the input. They use a DAC to generate an analog voltage, and then a comparator

7The horizontal one.

23

−

+

Vout

−Vref

reset

C

D0

LSB

2C

D1

4C

D2

8C

D3

MSB

Figure 27: Capacitor binary weighted ladder ADC

compares that to the input.

A high level schematic of this structure can be seen in Figure 28a on the next page.

The operation of this ADC is shown in Figure 28b on the following page. Note that the 2ndlast estimate is closer than the final estimate. However since it is higher than the input, thecomparator outputs a 0, so the successive approximation register saves a 0 into that respective bit.A workaround for this is to add half an LSB to the input value before comparing it.

10.3.2 Algorithmic

A single stage algorithmic ADC is shown in Figure 29 on the next page.

The input range should be −Vref

2 ≤ Vin ≤ Vref

2 .

For the first clock cycle, the leftmost switch is connects Vin to the sample and hold circuit.

The comparator then outputs a 1 if the input is positive and a zero if the input is negative. Thisgoes into the shift register as the MSB.

If the input to the shift register is a 1 or a 0, Vref

4 is subtracted or added from the output of thesample and hold circuit, respectively. The result is then amplified by a factor of two. The sameprocess is then repeated N − 1 times, with the left switch changing to connect the output of theamplifier to the sample hold input circuit.

The addition or subtraction and doubling is effectively a binary search. However, whilst thesuccessive approximation ADC implemented a binary search by changing the approximation, thisdevice implements it by recursively zooming in on the input. If the input to the sample hold circuitis positive, we know the input is somewhere from 0 to Vref

2 . So we subtract Vref

4 and double it.This changes 0Vto −Vref

2 , Vref

4 to 0Vand Vref

2 to Vref

2 . We have stretched the window that weknow the input is in, back into the maximum input range of the device. This is how we zoom inon half the input range.

This algorithm is shown in Figure 30 on page 26.

The resolution of this device is limited by the acuracy of the adder and multiplier.

24

−

+SampleHold

SuccessiveApproximation

Register

DAC

VinDout

Vestimate

(a) Schematic

clock cycles

V

Vin

0 1 2 3

Vestimate

(b) Operation

Figure 28: Successive Approximation ADC

10.3.3 Pipelined Algorithmic

A pipelined algorithmic ADC can be seen in Figure 31 on page 27.

It works in a very similar way to the normal algorithmic ADC. The single algorithmic ADC did thecomparing, addition and doubling using the same hardware, taking one clock cycle per bit. Thepipelined algorithmic ADC is made up of N single algorithmic converters, where the output of theamplifier feeds into the sample and hold sub-circuit of the next single algorithmic converter.

This structure is N times larger than the simple algorithmic converter. It works at the same speedper bit (same clock speed), but works on N samples at once, so it can sample once per clock cycle,whereas the simple one sampled once per N clock cycles. There is a delay of N clock cycles, butthis normally doesn’t matter very much.

−

+SampleHold

Shift Register Dout

Vin V+

+×21

0

−Vref

4

Vref

4

Figure 29: Single stage algorithmic ADC Schematic

25

V

0V

Vref

2

−Vref

2

Comparator Output

Clock Cycles

V+

1

1MSB

2

0

3

1

4

1LSB

Figure 30: Single stage algorithmic ADC operation

11 Digital Logic

11.1 Inverter

A basic inverter is shown in Figure 32 on page 28.

The transfer function of this inverter, and the drain current Ix is shown in Figure 33 on page 29.The drain current is called a crowbar current because the graph of Ix against Vin is shaped likethe slit on the end of a crowbar8.

11.2 Buffers

Most static CMOS logic can’t drive large loads. If we need to drive a large load, we insert abuffer9. If we need to drive a really large load, we insert several buffers of increasing size, asshown in Figure 34 on page 29. The reason we don’t use a single huge buffer is because the inputcapacitance of the buffer would be large compared to the input capacitance of a small buffer.

If A is too large, then we have the same problem that we get if we just had one huge buffer. IfA is too small, we’ll have heaps of buffers, which will consume lots of space and power and willincrease propagation delays.

As a rule of thumb:

A = N

√CLCin≈ 3 to 5

8Torsten said he didn’t know why it’s called that. The textbook doesn’t say, and I can’t find anything on theInternet on it. This is just my guess.

9An inverter may be used as a buffer, as long as you adjust the logic accordingly.

26

−

+SampleHold

D2(t) (MSB)

+×21

0

−Vref

4

Vref

4

Vin

−

+SampleHold

D1(t− 1)

+×21

0

−Vref

4

Vref

4

−

+SampleHold

D0(t− 2) (LSB)

Figure 31: Pipelined algorithmic ADC (3 bits)

27

Vin Vout

WN

L

WP

L

Ix

Figure 32: Inverter

11.3 Static CMOS Logic

11.3.1 Propagation Delay

Figure 35a on page 30 shows a basic NAND gate. To calculate the high to low10 propagation delay,we use the model in Figure 35b on page 30.

Propagation delay is the time difference between when an input has half changed, to when theoutput has half changed. To find this, we need to find the time constant τ seen by Vout in Figure35b. Calculating this exactly is quite challenging. There is a simple approximation we can makefor circuits of this form. We basically use superposition for each capacitor.

τ ≈N∑n=1

(CDN

N∑m=1

RDSm

)tpd = ln(2)τ

For the case of N = 3 shown in Figure 35b:

τ ≈CD1 ·RDS1

+ CD2 · (RDS1 +RDS2)

+ CD3 · (RDS1 +RDS2 +RDS3)

Low to high propagation delay is calculated the same way. Even if there are parallel branches, weonly calculate the propagation delay for one path at a time (don’t add the resistors in parallel).This is because before the transition, each parallel path would be off (open), and then the inputchanges. We assume this change only turns on (shorts) one branch, because if it turned on more,the logic is not optimised.

11.3.2 Sizing

There are several methods of sizing the transistors in logic gates. All lengths are normally theminimum length.

• If area is your main concern, set all dimensions to minimum.

• If speed (propagation delay) is your main concern, size so that the on resistances in eachbranch are equal.

10When the output goes from high to low.

28

VDD

VDD−Vth

P

VIH

VIL

Vth

N

Vin

Vout

Vin

Ix

Figure 33: Inverter transfer function and crowbar current

– Set all NMOS widths to their minimum

– Set all PMOS widths to twice the NMOS minimum (since carrier mobility in PMOStransistors is half that of NMOS)

– Where N transistors appear in series, multiply each of their widths by N .

– Where there are N parallel branches, scale one branch so that the total resistance ofeach branch is equal.

– Where there are N parallel transistors in series withM parallel transistors andM 6= N ,pick one single path from one end to the other, scale up the width of each transistorin that path to make the total resistance equal to the unit resistance. Then scale allthe other parallel branches so that the total resistance from one end to the other is thesame regardless of which path you take.

Vin

Cin

1 A2 A3 A4

CL

Figure 34: String of buffers of increasing size

29

Vin1

Vin2

Vin3

Vin2 Vin3Vin1

Vout

(a) Circuit

RDS3

CD3

RDS2

CD2

RDS1

CD1

Vout

(b) Model for propagation delays

Figure 35: Simple NAND gate and its propagation delay

– Scale every transistor down until the smallest PMOS is equal to the unit PMOS, or thesmallest NMOS is equal to the unit NMOS.

11.4 Transmission Gates

Transmission gates act just like switches. When the enable (EN) signal is high, both the NMOSand PMOS transistors turn on, shorting the two inputs. When the enable signal is low, they bothturn off, creating an open circuit between the two inputs.

The reason that both and NMOS and PMOS are needed (as opposed to just one) is because thedrain source resistance of an NMOS and PMOS becomes very high at VDD and 0V respectively.This is because |Vgs| is small, so ID is small11, so rDS is large12.

EN

EN

(a) Circuit

EN

EN

(b) Symbol

Figure 36: Transmission gate

11Refer back to equation 1 on page 4.12Refer back to equation 2 on page 6.

30

12 Flip Flops and Latches

12.1 Transmission Gate Flip Flop

Flip flops can be made using normal logic gates, as we learnt in ELEC2141. However they can bemade with fewer transistors using transmission gates, as shown in Figure 37.

E

E

E

EE

E

E

E

Vin

Q

Q

clkE

E

Figure 37: Flip flop implemented using transmission gates

Each half is just a pair of back to back inverters, which act as a memory element. The loop canbe broken by turning off the top transmission gate in the respective loop.

When the clk signal is low, Egoes high and E goes low. The left half of the flip flop becomesdisconnected from the right half. The input is connected through to the left loop. The left loopisn’t closed, since the top left transmission gate is open.

When clk transitions from low to high, the input is disconnected from the circuit, while the leftloop closes, thereby saving the input state in the left loop. The transmission gate joining thetwo loops turns on, thereby propagating the (inverted) input value into the right loop, which isnow opened. Due to the finite propagation delay of each element, a change in the input when clktransitions from high to low will not result in an erroneous output.

12.2 Timings

Propagation delay is the time between the rising edge of the clock, and a change in the output

Set up time is the time from a change in the input to the rising edge of clk, for the latest changein input which will successfully propagate to the output that clock edge. This value can benegative13.

Hold time is the time from a rising edge of clk to a change in input, for the earliest change ininput which not propagate to the output that clock edge. This value can be negative.

Contamination delay is equal to the minimum propagation delay.

12.3 Dynamic Latch

A dynamic latch is shown in Figure 38 on the following page. This is the smallest memory elementthat can be built. It is only 4 transistors.

13Since the clk signal must first pass through 2 inverters, the clock seen by the flip flop circuit is slightly delayedto the clock we measure at the input pin. Hence set up time can be negative

31

D Q

Cin

VX

ON

ON

Figure 38: Dynamic Latch

When the ON signal is high, the transmission gate turns on, and this circuit simply becomesan inverter. When the ON signal is low, the parasitic capacitance (Cin) of the inverter andtransmission gate means that the voltage stays at VX .

However even when the transmission gate is off, a tiny current trickles through the bulk-sourcejunction of one of the transistors, which slowly charges or discharges the parasitic capacitance.This causes the value to be corrupted after about 1ms. Consequently, this type of memory needsto be refreshed frequently.

13 Memory Elements

13.1 Overall Structure

Most random access memory (RAM) and read only memory (ROM) blocks use a structure similarto the one shown in Figure 39.

Each dotted square is one byte of memory. The 2N+M bytes are arranged in a grid. The N mostsignificant bits activate the row. The horizontal lines are called word lines, because we activatethe whole row, and throw away the bits we don’t care about.

The M least significant bits select the column. For reading, the voltage in the selected bit ispassed down the bit line (vertical line) to then output pin. For writing, the voltage from the I/Opin passes up the bit line and writes the only enabled cell, which is the selected bit.

2M Muliplexer

2N

Muliplexer

Address /N +M

/

M

/N

I/O

Figure 39: Overall structure for most memory

32

13.2 6 Transistor Static Memory Element

Figure 40 shows a common6 transistor memory structure.

Word Line

QQ

Data

read

Figure 40: 6 transistor static memory

The blue parts make up the memory element for a single bit. This is what the blue square inFigure 39 on the previous page represents. The dotted blue rectangles indicate that this structure(including the green word line) is repeated many times. The green connections make up the wordline. The red connections and components make up the bit line and the logic at the bottom ofeach bit line.

The 4 innermost blue transistors make up two back to back inverters. This is what saves thebit. The outermost blue NMOS transistors connect the bit and it’s compliment to the bit line.They are enabled by the word line. NMOS transistors are only good at transmitting zeros14, so totransmit a 1, we transmit a zero to/from the Q side.

When reading (read=1), the red tri-state buffers which are pointing up are disabled (hi impedanceoutput). If the saved bit is a 0, then the right (true) bit line (red vertical line) is pulled low, andthis value is buffered out onto the Data line with the right downwards pointing tri-state buffer. Ifthe saved bit is a 1, then the left (complementary) bit line is pulled low, and this value is bufferout onto the Data line with the downwards pointing inverting tri-state buffer.

14Due to a high impedance when transmitting voltages close to their gate voltage

33

When writing (read=0), the downwards pointing tri-state buffers are disabled. The right upwardspointing tri-state buffer buffers the value of Data onto the right (true) bit line. The left upwardspointing inverting tri-state buffer buffers the complimentary value of Data onto the left (compli-mentary) bit line. Whichever bit line is low will transmit a zero through the outermost blue NMOSinto the respective inverter, which will pull either Q or Q low.

13.3 Dynamic Memory Element

Sorry I haven’t written this bit yet.

Acronyms

ADC analog to digital converter

DAC digital to analog converter

DNL differential non-linearity

ENL essential non-linearity

LSB least significant bit

MSB most significant bit

RAM random access memory

ROM read only memory

About

All the diagrams in this document were drawn in LATEX, using the tikz and circuitikz pack-ages.

Table numbers, figure numbers, page numbers and the table of contents are all clickable hyper-links.

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