ELCT 501: Digital System Design Lecture 3: Memory and Programmable Logic (continue) Dr. Mohamed Abd El Ghany, Department of Electronics and Electrical Engineering
ELCT 501:
Digital System Design
Lecture 3: Memory and Programmable Logic (continue)
Dr. Mohamed Abd El Ghany,
Department of Electronics and Electrical Engineering
2 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
Memory Model
Flat Memory Model
0x0A
0xB6
0x41
0xFC
Lower Memory Address
0x00000000
Higher Memory Address
0x00000001
0x00000002
0x00000003
0xFFFFFFFF 0x0D
32-bit address space
can address up to 4 GB
(232) different memory
locations
ELCT 501: Digital System
Design
3 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
Endianness [Danny Cohen 91]
A byte ordering- How a multiple byte data word stored in memory
Endianness (from Gulliver’s Travels)
Big Endian
Most significant byte of a multi-byte word is stored at the lowest
memory address
E.g. Sun Sparc, PowerPC
Little Endian
Least significant byte of a multi-byte word is stored at the lowest
memory address
e.g. Intel x86
Some embedded & DSP processors would support both for interoperability
ELCT 501: Digital System
Design
4 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
Endianness Examples
Store 0x21436587 at address 0x0000
0x87
0x65
0x43
0x21
Lower Memory Address
Higher Memory Address
0x0000
0x0001
0x0002
0x0003
BIG ENDIAN
0x21
0x43
0x65
0x87
Lower Memory Address
Higher Memory Address
0x0000
0x0001
0x0002
0x0003
LITTLE ENDIAN
ELCT 501: Digital System
Design
5 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
“Permanent” binary information is stored
Non-volatile memory
Power off does not erase information stored
Read Only Memory (ROM)
2k words N-bit per work
ROM N-bit Data Output
K-bit address lines
N K
ELCT 501: Digital System
Design
6 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
32x8 ROM
32x8 ROM 8 5
0 1 2 3
28 29 30 31
D7 D6 D5 D4 D3 D2 D1 D0
A4
A3
A2
A1
A0
5-to-32 Decoder
Each represents 32 wires
Fuse can be implemented as a diode or a pass transistor
ELCT 501: Digital System
Design
Programming the 32x8 ROM
7
0 1 2
29 30 31
D7 D6 D5 D4 D3 D2 D1 D0
A4
A3
A2
A1
A0
5-to-32 Decoder
Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 1 1 0 0 0 1 0 1
0 0 0 0 1 1 0 0 0 1 0 1 1
0 0 0 1 0 1 0 1 1 0 0 0 0
… … … … … … … … … … … … …
1 1 1 0 1 0 0 0 1 0 0 0 0
1 1 1 1 0 0 1 0 1 0 1 1 0
1 1 1 1 1 1 1 1 0 0 0 0 1
ELCT 501: Digital System
Design
Example: Lookup Table
8 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
X F(X)=X2
0 0
1 1
2 4
3 9
4 16
5 25
6 36
7 49
X F(X)=X2
000 000000
001 000001
010 000100
011 001001
100 010000
101 011001
110 100100
111 110001
Design a square lookup table for F(X)=X2 using ROM
ELCT 501: Digital System
Design
Square Lookup Table using ROM
9 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
X F(X)=X2
000 000000
001 000001
010 000100
011 001001
100 010000
101 011001
110 100100
111 110001
0
1
2
3
F5 F4 F3 F2 F1 F0
X2
X1
X0
3-to-8 Decoder 4
5
6
7
ELCT 501: Digital System
Design
Square Lookup Table using ROM
10 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
X F(X)=X2
000 000000
001 000001
010 000100
011 001001
100 010000
101 011001
110 100100
111 110001
0
1
2
3
F5 F4 F3 F2 F1 F0
X2
X1
X0
3-to-8 Decoder 4
5
6
7
=X0
Not used
ELCT 501: Digital System
Design
Square Lookup Table using ROM
11 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
X F(X)=X2
000 000000
001 000001
010 000100
011 001001
100 010000
101 011001
110 100100
111 110001
0
1
2
3
F5 F4 F3 F2 F0
X2
X1
X0
3-to-8 Decoder 4
5
6
7
F1
ELCT 501: Digital System
Design
Classifying Three Basic PLDs
12 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
Fixed AND plane (decoder)
Programmable OR plane
Programmable Connections
(Programmable) Read-Only Memory (ROM)
INPUT OUTPUT
Programmable OR plane
Programmable Connections
Programmable Logic Array (PLA)
Programmable AND plane
INPUT OUTPUT
Programmable AND plane
Fixed OR plane
Programmable Array Logic (PAL) Devices PAL: trademark of AMD, use PAL as an adjective or expect to receive a letter from AMD’s lawyers
INPUT OUTPUT
F/F
ELCT 501: Digital System
Design
Programmable Logic Array (PLA)
13 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
C
B
A
C C B B A A
Programmable AND Plane
Programmable OR Plane
F2
ELCT 501: Digital System
Design
Example using PLA
14 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
m(0,5,6,7)C)B,F2(A,
m(0,1,2,4) C)B,F1(A,
CBAACABF2
BCACABF1
CBCABAF1
ELCT 501: Digital System
Design
Example using PLA
15 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
C
B
A
C C B B A A
CBAACABF2
BCACABF1
AB
AC
BC
A B C
F2 F1
ELCT 501: Digital System
Design
PAL Device
16 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
A
B
IO1
IO2
IO1 IO1 B B A A IO2 IO2
Programmable AND Plane
Fixed OR Plane
ELCT 501: Digital System
Design
PAL Device Design Example
17 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
A
B
IO1
IO2
IO1 IO1 B B A A
DCBADCADCBACABIO2
DCBACABIO1
D D C C
Not programmed
ELCT 501: Digital System
Design
CPLD and FPGA [brown & Rose 96]
18 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
Complex Programmable Logic Device (CPLD)
Multiple PLDs (e.g. PALs, PLAs) with Programmable interconnection
structure
Pioneered by Altera
Field-Programmable Gate Array (FPGA)
High logic capacity with large distributed interconnection structure
Logic capacity= number of 2-input NAND gates
Offers more narrow logic resources
CPLD offers logic resources with a wide number of inputs (AND planes)
Offer a higher ratio of Flip-flops to logic resources than CPLD
High Capacity PLD (HCPLD) is often used to refer to both CPLD and FPGA
ELCT 501: Digital System
Design
CPLD Structure
19 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
PLD PLD PLD PLD
PLD PLD PLD PLD
Logic block
Interconnects
I/O block
ELCT 501: Digital System
Design
FPGA Structure
20 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
Logic block
I/O block
Interconnects
ELCT 501: Digital System
Design
FPGA Programmability
21 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
Floating gate transistor
Used in EPROM and EEPROM
SRAM-controlled switch-Control
Pass transistors
Multiplexers (to determine how to route inputs)
Antifuse
Similar to fuse
Originally an Open-Circuit
One-Time Programmable (OTP)
ELCT 501: Digital System
Design
References
22 Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
Logic and Computer Design Fundamentals
by M. Morris Mano and Charles R. Kime. 4th
edition, Prentice Hall. 2008.
P. Marwedel: Embedded System Design,
Springer, 2006
“First Steps with Embedded Systems” Byte
Craft Limited
ELCT 501: Digital System
Design